EDK : FSL macros defined by Xilinx are wrong

[Peter Alfke]

fpga_toys@yahoo.com wrote:

Peter Alfke wrote:
Your wish has been granted...

Wow ... how did you make 6 years of smaller XC4K, Spartan and Spartan2
boards just disappear?

Are you trying to be nasty, funny or whatever?
I answered your complaint about the alleged lack of cheap boards with
dedicated multipliers.
I did not make anything older disappear. But those old boards have no
dedicated hardware-implemented combinatorial multipliers. That's all.
Peter Alfke, from home.

 

Are you sure you actually want the VGA specification (pretty plain and
limited) or do you want the specs for what it evolved into?

Also, what are you looking for - timing, electrical, programming?

 

[Mich]

Hi again

can anyone tell me where and how I can connect the outputpins of BRAM
in XPS7.1

Thanks
Mich

 

[Mich]

I have made my project with the wizzard and there I have added 2
BRAM-controllers with BRAM on the PLB bus
thenI have used the importe/create wizzard to add an IP who is
master/slave on the PLB bus

When I want to download this there is no problem with the connections
of the BRAM
but when I change the IP there are bath connections

Do you know how this is possible and how I can fix this?

Greets
Mich

 

Jerry Coffin wrote:

VESA has quite a few more standards as well, but without
more information about what you're doing, it's hard to
guess which would apply.

Yes, knowing the application is the key.

Depending on what you need to do, you can treat a VGA monitor is either
an analog, or a nearly digital device.

For just getting something on monitor, several of the FPGA intro boards
(spartan 3 kit, etc) have VGA connectors and sample projects that
demonstrate a state machine producing the timings. These typicall
drive the sync signals directly with LVCMOS outputs and the three color
lines either through a single resistor (270 ohms on the s3kit) or a
2-bit resistor ladder dac per channel, to give a few more digital
colors. A real DAC gives even more.

Trying to use an FPGA to make a "VGA card" for a pc would be a more
complicated project, in which case a lot of the register-level detail
of the basic VGA card would need to be known.

 

[Thomas Rudloff]

eehinjor wrote:

Thank you for your response so soon.
250ps is about 3inches,but the length of clk can not be longer than
2.5+0.1inches.
how can that meet the spec?

There is _no_ 250ps delay! The switch is equal to a 5Ohm resistor what
computes with 50pF load to a tau of 250ps. I do not know Altera parts in
detail but assume aprox 5pF on a dedicated clock input. Maybe 7pF.

So you are at 25ps to 35ps.

Be aware that your I/Os have more capacitive load than a dedicated input
and make sure that these do not violate their length.

 

[logjam]

fpga_toys@yahoo.com wrote:

logjam wrote:
I want to do all sorts of things. After this I want to build an 8bit
computer using transistors. I saw one on the internet, but it didn't
look like it ran any decent software.

Way to go Excellent way to gain grounding experience, as nobody
will pay you to build one today!! The oldie moldies here are likely to
enjoy gabbing about the past too.

Thats right. I've learned a lot about microcode and processor
instruction sets from trying to design my own ALU. For example, a
compare instruction is usually a subtract without store.

Probably the coolest thing I've done yet is add FFFFFFFFFFFFFFFF to 0,
apply the carry input, and watch the Altera simulator propagate the
carries.

One thing I have that 1975 didn't, is a P4 3.2GHz PCB autorouter, and a
way to test the design to pretty much guarantee it will work.

My home project has been taking a few thousand older FPGA's to build a
home super computer into a desktop sized box (with water cooling, and a
lot of memory, fibre channel disks, etc) .... It takes a lot of
current too .... a few thousand amps for even a "small" super computer.

That sounds very interesting. Do you have a project web page journal
or anything like that?

An interesting thing to think about...how long do you think it will be
before through hole devices are discontinued? What will the electronic
hobby look like? Computer programming classes today are in Java and
visual basic. I don't think the local university even has C.

One last note, I live in Alaska. Its cold and snowing right now. What
elese am I supposed to do?

 

[Peter Alfke]

logjam wrote:

An interesting thing to think about...how long do you think it will be
before through hole devices are discontinued?

For high-pincount and/or high-performance circuits, through-hole has
been dead for more than a decade.
Through-hole means 100 mi (~2.5 mm) pin spacing, which becomes hopeless
above 200 pins.
Add to that the bondwire and lead-frame inductance, and it just cannot
support today's top requirements of speed and signal integrity.
The trend is to flip-chip, bonding the chip surface directly to the
package, without any bondwires.
That then also means ball grid arrays, and is great for professional
assembly, but a killer for the hobbyist.
I am really feeling sorry for this, for I grew up designing and
soldering (ham) radio gear. The combined smell of hot solder and burned
fingertips is still in my nose. But it is not for the future.
Just like carburetors, generators, breaker points and grease nipples on
cars.
Fond memories, some not so fond...
Peter Alfke

 

[Isaac Bosompem]

logjam wrote:

fpga_toys@yahoo.com wrote:
logjam wrote:
I want to do all sorts of things. After this I want to build an 8bit
computer using transistors. I saw one on the internet, but it didn't
look like it ran any decent software.

Way to go Excellent way to gain grounding experience, as nobody
will pay you to build one today!! The oldie moldies here are likely to
enjoy gabbing about the past too.

Thats right. I've learned a lot about microcode and processor
instruction sets from trying to design my own ALU. For example, a
compare instruction is usually a subtract without store.

Probably the coolest thing I've done yet is add FFFFFFFFFFFFFFFF to 0,
apply the carry input, and watch the Altera simulator propagate the
carries.

One thing I have that 1975 didn't, is a P4 3.2GHz PCB autorouter, and a
way to test the design to pretty much guarantee it will work.

My home project has been taking a few thousand older FPGA's to build a
home super computer into a desktop sized box (with water cooling, and a
lot of memory, fibre channel disks, etc) .... It takes a lot of
current too .... a few thousand amps for even a "small" super computer.

That sounds very interesting. Do you have a project web page journal
or anything like that?

An interesting thing to think about...how long do you think it will be
before through hole devices are discontinued? What will the electronic
hobby look like? Computer programming classes today are in Java and
visual basic. I don't think the local university even has C.

One last note, I live in Alaska. Its cold and snowing right now. What
elese am I supposed to do?

I read a site somewhere that had a couple of students build a full
32-bit CPU out of standard 74 parts. Obviously it was a huge power
guzzler but it worked nonetheless!

For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
today :
I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
and 32KB of RAM and a single 8-bit output port. It is a nice
development system. I wrote some IEEE754 FP library in Z80 assembly. It
was relatively painless since I am fairly comfortable with the x86 and
scores other CPU's instruction set.

I just dont have the cash to purchase all the TTL components to do it
your way (broke student syndrome, it is well documented ). But I did
design a 16-bit CPU in VHDL and used the 200K gate Spartan3 to
implement it, it is working fine too, just tested it last night in the
FPGA. The thing is that the CPU I designed is relatively complex (its
ISA definitely has some CISC elements to it) and only took about 30-40%
of the space in my FPGA. So I have a TON of space to implement
peripherals and the like. I plan on writing an assembler and C compiler
for it. I definitely need to learn how those work.
Also I used BlockRAM to implement the registers (banked) and the stack
space so I took a speed hit (in terms of clks/instruction), but that is
no problem, it was my first CPU design. Also let me make it clear that
I DO NOT work for Xilinx. The Spartan3 devkit I bought was very
affordable, I am very happy with the amount of features you get for the
price.

Forge on, and show us pics, lots of juicy pics

 

[Jerry Coffin]

In article <1141005334.019869.143020
@j33g2000cwa.googlegroups.com>, dereks314@gmail.com
says...

I'm looking for a functional spec rather than a timing spec. I remember
reading an article that described some of the functionality of CGA, EGA
and VGA. When most people in this group inquire about a VGA adapter
what they are actually asking for is a frame buffer that generates
video timing signals for a multisync monitor for an IBM PC. I would
like references for the original IBM 256 Kb VGA adapter or something
newer (supporting the new video modes).

I'd really like to hear from somebody that was connected with or has
documentation from TSENG. I seem to remember back in the day their VGA
adapter's, for the cost, were a step a head of the competition.

_Programmer's Guide to the EGA, VGA, and Super VGA Cards_
by Richard Ferraro has pretty decent descriptions of most
of the graphics cards that were current when it was
published, including a couple from Tseng Labs. I haven't
checked, but I'd guess this has been out of print for a
while though, so you'll probably have to find a used copy
to get it. The ISBN is (was) 0-201-62490-7.

Of course, quite a bit of it won't be applicable to what
you're apparently doing, but it has register-level
descriptions of the interface the cards presented to the
rest of the machine, and for the VGA and similar cards,
that tells you quite a bit about its internal structure
as well.

I would note, however, that much of the design of the VGA
(for one example) was a long ways from ideal in a modern
system. Much of the architecture of the VGA centered its
connection to an 8-bit bus. If you're creating a graphics
controller in an FPGA, there's no reason to restrict your
bus to it to only 8 bits wide unless you're planning on
emulating an entire PC design so you can run PC software
on your system. Otherwise, you might as well use a wide
bus to connect the graphics to the rest of the system,
which will simplify the overall design a LOT. Believe me,
the VGA design really put a lot of effort into getting
decent performance in spite of a narrow bus, so if you
can start from a clean slate, you can do a LOT better.

--
Later,
Jerry.

The universe is a figment of its own imagination.

 

Peter Alfke wrote:

That then also means ball grid arrays, and is great for professional
assembly, but a killer for the hobbyist.

The funny thing is that BGA brings SMT to the hobbiest, where high
density flat packs have a pitch so narrow that parts can not be hand
placed on paste, or easily soldered by hand, even with a stereo
microscope that easily, but possible for smaller pin count devices like
memory.

I've shown that home brew computer group here how to reliably solder
BGAs, and reball them, so they can use salvage at low cost. Placing and
soldering a 400-700 ball bga is a piece of cake, hand soldering the
SDRAM and EEPROMS for the design is REALLY painful for TSOP's.

It's actually easier to do powerful hobby designs in BGA, than it was
in dip parts.

 

[Augast15]

hi,
There is 4.5 V supply for entire circuit throughout the board.

I am testing with schmitt trigger today
thanx guies
Augast15

 

[ALuPin@web.de]

hi bijoy ,

you could declare AW or even different AW (AW1, AW2, AW3 ...)
in a separate package (which could also be used for synthesis of
course)
By doing so Modelsim should have no
problems to identify the length of the std_logic vector in the
corresponding instantiation.

Rgds
André

 

[Antti]

all lines are 'single' line
the best info is to look with FPGA editor or then XDL file

 

[Nial Stewart]

That's probably true, and I expect to be using other tools as well as
VHDL in 5 years. However as John posted above, there's alot more to
implementing an FPGA design than the description used for the logic
and I think we'll still be using HDLs to get the most out of them for
a long time to come (to a bigger extent than with C/asm).

Probably the biggest change is that EE's will still be putting the
chips on boards as they have always done, and the FPGA programming will
shift to systems programming staff, which are frequently Computer
Engineering folks these days (1/2 EE and 1/2 CSc, or CSc types with a
minor in the digital side of EE).

That may be the case for large multi designer designs, for smaller
devices someone who understands the underlying architecture and
what they're actually trying to design to will be needed.

This is a quote from a current thread "Entering the embedded
world... help?" on comp.arch.embedded. I don't know how accurate
this is.

"If you meant to say "most everyone these days uses an HLL, and for
embedded applications most people choose to use C whereas a significant
minority choose to use C++" I would not have objected much - although,
in terms of code volume on the shelf, assembly language is still at
least 30% of all products. Consider that the really high-volume
projects use the really cheap micros. I've seen numbers that say asm
40%, C 40%, C++ 10%, other 10%, and I'm quite prepared to believe them.

The problem is, people who talk about this stuff get into their niche
and see everything else from that perspective. Few people routinely
work with a broad spectrum of systems from 4-bit to 64-bit and code
volumes from a few hundred bytes to a few dozen megabytes."


You seem to have a deeply entrenched view of the FPGA development future.
Only time will tell if you are correct or not, I don't believe you are
and I'll leave it at that.

Nial.

 

[Chris Francis]

Antti wrote:

all lines are 'single' line
the best info is to look with FPGA editor or then XDL file

Cheers!

 

[Falk Brunner]

fpga_toys@yahoo.com schrieb:

Peter Alfke wrote:

That then also means ball grid arrays, and is great for professional
assembly, but a killer for the hobbyist.


The funny thing is that BGA brings SMT to the hobbiest, where high
density flat packs have a pitch so narrow that parts can not be hand
placed on paste, or easily soldered by hand, even with a stereo
microscope that easily, but possible for smaller pin count devices like
memory.

I've shown that home brew computer group here how to reliably solder
BGAs, and reball them, so they can use salvage at low cost. Placing and
soldering a 400-700 ball bga is a piece of cake, hand soldering the
SDRAM and EEPROMS for the design is REALLY painful for TSOP's.

Naaa. Some yeas ago I did my own Spartan-II demoboard, using a TQ144
package with 0.5 mm pitch. It was not so difficult. OK, you need some
training and the right solder iron, but after a while if will be no big
deal.

It's actually easier to do powerful hobby designs in BGA, than it was
in dip parts.

I wouldnt agree. DIP is still easier to handle, but sure, if you want to
achive a given functionality, a BGA device this tons of power inside can
easy replace a bunch of standard euro cards filled with leagacy DIP stuff.

Regards
Falk

>

 

[Jan Panteltje]

On a sunny day (26 Feb 2006 15:33:20 -0800) it happened "Isaac Bosompem"
<x86asm@gmail.com> wrote in
<1140996800.146251.277360@e56g2000cwe.googlegroups.com>:

For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
today :
I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
and 32KB of RAM and a single 8-bit output port. It is a nice
development system. I wrote some IEEE754 FP library in Z80 assembly. It
was relatively painless since I am fairly comfortable with the x86 and
scores other CPU's instruction set.

Hey, Z80 cool.
I build a Z80 system in the eighties, needed an OS too, so I wrote a CP/M
emulator for it, disassembler, practically any application soft you can think
of, has even audio audio editor, and then wrote a multitasking kernel for the
z80 that ran text windows and mouse... then the 64 kByte was full.
http://panteltje.com/panteltje/z80/index.html
diagrams are there too, the thing is in the attic, 2 euro card backplanes
with CPU, IO (EPROM programmer), serial IO, DRAM RAM disk, VDU,
more, cannot remember.... lots of plug-in Euro cards.
But honestly I would not want to go back to Z80 today.
Should take some pictures some day, probably the EPROMS are duff by now...
For 1 M$ you can buy it and the rights to the CP/M emulator for embedded ;-)
However the multitasker is still on 5 inch flop, and I have no way these days
to make a copy..
That dz80 disassembler was actually one of my first C programs, and it shows....
People seem to be using it though.

 

[John_H]

Because of comments from others on this forum, I've gotten into the habit of
LOCing the BlockRAMs whenever relative placement is critical. While there
might be a slightly "better" location for the BlockRAMs than what I choose,
the place & route seems to do a better job filling the logic around the
memory rather than trying to figure out a good placement for both logic and
memory at the same time.

"sudheer" <ksudheerkumar@gmail.com> wrote in message
news:1141033138.838815.238520@v46g2000cwv.googlegroups.com...

XST is synthesising the following verilog code to a 8192x24-bit RAM.

code snipped

ISE is mapping this 8192x24bit RAM to 12 RAMB16s. But when the device
is occupying about 65% resources (with other modules integrated) the
RAMs are not placed as neighbors leading to different timing problems
on different compilations.

The requirement is to allow the ISE-map to place these RAMs closely,
either in a column or controlled rectangular array of RAMB16s, after
which PAR can place this group optimally anywhere in FPGA based on
other modules.

I am not able to use RLOC or RLOC_RANGE constraints to accomplish this.
Kindly let me know how to control the relative placement of RAMB16s.

Thank you and I await your inputs/ suggestions ASAP.
K Sudheer Kumar

 

[Duane Clark]

Duane Clark wrote:

bijoy wrote:
Hi I have made a generic component like below

entity fifo is generic( AW : integer; PROG_EMPTY_THD :
std_logic_vector(AW downto 0);...

The problem is that you are using AW within the generic declaration
area. The way you are doing that is a bit unusual too. Make
PROG_EMPTY_THD a signal instead of a generic, and the problem should go
away.

Oops, and of course also PROG_FULL_THD.