EDK : FSL macros defined by Xilinx are wrong

[Simon Peacock]

Most likely it slows down. I can't speak for Xilinx but the Modelsim Xilinx
tools get faster the more money you spend... up to a point... then they slow
down again. I have noticed the current release on Modelsim is considerably
slower the 5.x (which we still use at work). I believe they increased the
memory footprint and added geewiz which just caused it to run slower.
M2C

Simon


"Eric Smith" <eric@brouhaha.com> wrote in message
news:qhu0asx89k.fsf@ruckus.brouhaha.com...

Steve Lass wrote:
ISE Simulator Lite is included free with WebPACK and Foundation. It
has limit of around 10,000 lines of code.

ISE Simulator is only available to Foundation customers and costs $995.
It
has no line limit.

Does the Lite version have any other limitations relative to the full
version? For instance, is there any artificial slowdown?

Eric

 

[Simon Peacock]

Well if its the Linux of layer 2.. then you can't have an exclusive patent
and you have to release source code

It sounds an interesting idea. But the OSI model is there for a reason.
Its a fairly generic thing and you might have difficulty calling it 802.x
without it as its fairly well sprinkled around the spec.

But I have been designing Ethernet interfaces without any OSI model for
years... I wonder what makes your any better?

If you want to contact me... let me know.

Simon


"Perfect Queue" <jonathangael@hotmail.com> wrote in message
news:1140575213.319606.10180@f14g2000cwb.googlegroups.com...

We are a startup company of 6 employees (2 full time) which is the
exclusive licensee of the patented ideal optimum MAC protocol. Our
prototype PCI based network interface card hardware design has been
completed and we are looking for partners who can help with the
simulation and design of an Altera Cyclone FPGA. Unfortunately, our
R&D budget is running thin, so we must appeal to the FPGA community for
help.

The goal of this research project is to complete a 100Mbps proof of
concept system, so that we can attract significant investment. Initial
target markets for the production level 1/10Gbps networks will be
applied in HPC, wireless, and VoIP.

Conceptually, you can think of this technology as becoming the Linux of
layer 2. Just as Linux has prevailed in unseating Windows at the OS
layer, we will prevail in unseating Ethernet as well as all of the
middle hardware that Ethernet requires for its shortcomings.

Qualified individuals will be awarded with stock options for their
participation.

 

[Simon Peacock]

Oh I'm so shocked.. I couldn't even get as far as a map with 8.1.02

Simon

"johnp" <johnp3+nospam@probo.com> wrote in message
news:1140562495.058573.237870@o13g2000cwo.googlegroups.com...

Another user emailed me saying he also saw this problem. His
solution (which I tried successfully) was to re-create the project
from scratch.

So, if you upgrade from 8.1.01 to 8.1.02 you may see Map fail.

I've opened a Webcase with Xilinx.

John Providenza

 

[Sandro]

Hi,

Maybe you all know... if not... take a look to
<Path_Were_is_Xilinx>/Xilinx/vhdl/src/unisims/unisim_VITAL.vhd
there are the vhdl VITAL source code for unisim library used for
simulation purpose.

there are DIFF_OUT, IDDR... almost all

Sandro

 

[Hal Murray]

I think
what is suprising to some, is that low level software design is long
gone,

Back in the old days, it was common to build FSMs using ROMs. That
approach makes it natural to think of the problem as software - each word
in the ROM holds the instruction you execute at that PC plus the right
external conditions.

That still seems like a good approach to me Seems pretty low level too.


I've done a reasonable amount of hack programming where I count
every cycle to get the timing right. I could probably have done
it in c, but I'm a bottom up rather than top down sort of person.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Antti]

FSL links are connected to MB core and can not access the OPB
the OPB_MCH_SDRAM IP core has slave FSL ports so external FSL (XCL)
master can access the SDRAM over FSL (but not the rest of OPB bus)

so you have options
1) MB software will read FSL and translate it to OPB transaction in
software
2) you write your own FSL 2 OPB (master) bridge
3) if you want to access BRAM then you can access the second port of
the BRAMs but its rew BRAM port not FSL

Antti

 

[Antti]

FSL links are connected to MB core and can not access the OPB
the OPB_MCH_SDRAM IP core has slave FSL ports so external FSL (XCL)
master can access the SDRAM over FSL (but not the rest of OPB bus)

so you have options
1) MB software will read FSL and translate it to OPB transaction in
software
2) you write your own FSL 2 OPB (master) bridge
3) if you want to access BRAM then you can access the second port of
the BRAMs but its rew BRAM port not FSL

Antti

 

[fpga]

I want my coprocessor can access the BRAM diretly because there is a
lot data transfer between them. It will be very unefficient to send
these data back to MB through FSL and then put them into OPB RAM or
vise verso.
I don't want to put connected my coprocessor to the sceond port of the
BRAM either because the BRAM(64K) is shared between the MB and my
coprocessor and I want the OPB arbitrator to solve the contension
problem for me. Then I needn't program my own.
For the second choice, write my own FSL2OPB bridge, or as said by ivan:
"develop a FSL coprocessor with OPB Master interface" will be quite
time consuming because I need to take care of my customized circuit to
the OPB bus signals? But it seems the only choice I have.
Did I understand this correct?

Thank you very much for all the replies.

 

[Antti Lukats]

"Pszemol" <Pszemol@PolBox.com> schrieb im Newsbeitrag
news:dtk2h7.b44.0@poczta.onet.pl...

Anybody here with experiences with syntetising some 8051 core
with JTAG debugger in FPGA ? What core can you recommend ?

there is no standard JTAG debug for 8051 core,
quickcores had some 8051 ipcore and jtag debug interface
but quickcores is dead, so you cant obtain that source any more

I bet any other available 8051 does not include jtag debugger
and even it would there is no debug software that supports that
so you would end up writing the debugger and jtag unit yourself
anyway

easiest is to take some 8051 core and just connect chipscope
ILA's onto the bussses, that sufficent for many cases

Antti

 

If you use Altera parallel programmer (APU), yo can use ISP pins like
normal i/o pins. In this case you treat 7128S as MAX without JTAG (7128
without S).

For other MAXs with S sign and Cyclone I use Quartus II with Byte
Blaster II.
When I connect "blocked ISP" MAXs to BB and try to write code (sof), I
get the answer: ''Unable to scan device chain''.

Noway2 napisal(a):

I am not entirely certain what you mean by "blocked ISP. The ISP port
is set off."

The Max7128 can be programmed (modified) through the JTAG port. You do
not need to use Altera's programming tool, though I always have for
this purpose. One person I know made up their own JTAG programmer and
used that. You do not even need to use their programming software as
long as the tool you are using supports the proper file format.

 

[Pszemol]

"Antti Lukats" <antti@openchip.org> wrote in message news:dtkvl4$ent$1@online.de...

"Pszemol" <Pszemol@PolBox.com> schrieb im Newsbeitrag
news:dtk2h7.b44.0@poczta.onet.pl...
Anybody here with experiences with syntetising some 8051 core
with JTAG debugger in FPGA ? What core can you recommend ?

there is no standard JTAG debug for 8051 core,
quickcores had some 8051 ipcore and jtag debug interface
but quickcores is dead, so you cant obtain that source any more

I bet any other available 8051 does not include jtag debugger
and even it would there is no debug software that supports that
so you would end up writing the debugger and jtag unit yourself
anyway

There are companies like Cast/Evatronix or Digital Core Design
who make 8051 with JTAG supported by Keil tools but their core
is bloody expensive... the prices go into range of over 25000
USD if you want to use core in more than one project...

easiest is to take some 8051 core and just connect chipscope
ILA's onto the bussses, that sufficent for many cases

I was talking about source-level debugging like it is supported by
some silicon manufacturers like Silicon Labs CYGNAL C80F330 Cpu.

 

[Ivan]

fpga wrote:

Hello, Ivan:

Hi,

In your case, how do you deal with the contension when MB and the
Coprocessor to the BRAM?

I used one "BRAM memory" to write data from MB (PORT A) to coprocessor
(PORT B) and another to write data from the coprocessor (PORT A) to MB
(PORT B).

And I don't understand why do you use FSL interface to connect the BRAM
but not OPB?

If you need to share data from BRAM, you can use the OPB bus (as you
propose). However, FSL is faster than OPB, and if you only need to share
data between the MB and the coprocessor, this solution is more
efficient. Of course, you need to develop the "FSL-BRAM interfaces" and
the "BRAM-Coprocessor interfaces".

Each approach is correct, it depends of your performance/operation
requirements.

Thank you very much for your help.
I want to build a system as the following. So the OPB arbitrator can
deal with the contension when both MB and Coprocessor access the same
address in BRAM at same time.
MB(M1)<--->FSL Interface<--->Coprocessor(M2)
| |
| |
|---OPB(with arbitrator)-----------|----------------->BRAM

Regards,

Ivan

 

[Pszemol]

"Robert F. Jarnot" <jarnot@mls.jpl.nasa.gov> wrote in message news:dtl22v$73q$1@nntp1.jpl.nasa.gov...

quickcores has become SiliconLaude -- www.siliconlaude.com -- and
interesting 8051 cores with real-time JTAG debug are available.

I have just visited their website and could not find IP cores available.
Instead they offer radiation-hardened silicon...
I am looking for an IP core to be put into a generic FPGA device.

 

[Eric Smith]

logjam wrote:

Now on to my question. Is there a simple combinatorial design for
division?

No that I've ever heard of. If there was, everyone would be using it.

All of the conventional division algorithms (hardware or software) are
sequential, producing one or more bits of result per cycle. For one bit
per cycle, a simple shift-and-subtract method is easy. Beyond that,
typically a small ROM is involved.

Some high-speed dividers work by instead multiplying by the reciprocal,
presumbaly because a high-speed reciprocal unit is a either easier to
build or faster than a high-speed divider. But it still only gets you
a few bits of your result every cycle.

There are a lot of books on computer arithmetic, and a lot of published
papers.

 

[fpga]

Thanks a lot.

 

[Robert Finch]

"Eric Smith" <eric@brouhaha.com> wrote in message
news:qhy80169ru.fsf@ruckus.brouhaha.com...

logjam wrote:
Now on to my question. Is there a simple combinatorial design for
division?

No that I've ever heard of. If there was, everyone would be using it.

Sure there is, one can do a division by cascading stages together without
using registers and clock. However it a) is really, really, slow for
propagation delay. And b) uses a lot of hardware (2 to 3 times as much as
for multiplication). Since division is rarely used most designers seem to go
with a clocked divider.


Why not use use the built in multiply operation of most HDL's ? One can
usually code something like a = b * c, and it will generate an optimal
design for any given architecture.

rob<remove>@birdcomputer.ca

 

[TC]

<mnemo5@163.com> wrote in message
news:1140684469.024703.273840@p10g2000cwp.googlegroups.com...

I am looking for a VHDL/Verilog sample program of Kalman filters.
Anybody
can help?

Implemenation of Kalman filters are highly system specific. A Kalman filters
is typically processed algortihmically (cpus or dsps). I've never seen, or
heard of, an rtl implemenation.

TC

 

[logjam]

I want the ability to build the whole computer using TTL logic, but
also put it in an FGPA. I'm learning VHDL as I go. Since the code is
generated from my TTL schematic, I can test the giant circuit before I
produce a PCB and solder hundreds of chips.

Just a thought, but wouldn't the delay using cascading stages without a
clock take just as much time as if you used a clock? Instead of using
the same stage over and over again its just duplicated? I think what I
will do is use the 64bit ALU that supports subtraction and addition,
throw in two shift registers, and a state machine to control timing.

 

[TC]

"mk" <kal*@dspia.*comdelete> wrote in message
news:9amsv19bsqck4s6ai982nsvc0rka1lu0g3@4ax.com...

On Fri, 24 Feb 2006 00:41:09 GMT, "TC" <noone@nowhere.com> wrote:


mnemo5@163.com> wrote in message
news:1140684469.024703.273840@p10g2000cwp.googlegroups.com...
I am looking for a VHDL/Verilog sample program of Kalman filters.
Anybody
can help?


Implemenation of Kalman filters are highly system specific. A Kalman
filters
is typically processed algortihmically (cpus or dsps). I've never seen, or
heard of, an rtl implemenation.

TC


Check this one out: http://www.dspia.com/receiver/receiver.html. This
is an Extended Kalman filter and it has been implemented in Verilog.
The naive implementation has 33 multipliers in it. A reformulated one
needs 26 multiplications and the RTL implementation has two
multipliers scheduled over 16 cycles.

Thanks for the pointer!

TC

 

[Isaac Bosompem]

logjam wrote:

The whole ALU with multiplier will take around 2.5 amps.

WOW, ~13W ALU!!!

Why not use an FSM based divider?