EDK : FSL macros defined by Xilinx are wrong

OK, I'm getting somewhere. It seems there's a REAL impossible timing error
in there somewhere. Trouble is, when I run the timing analyser in the MAP
stage, I see all the carry chain errors with longer delays first, even
though they're not real errors. I now remember this is what happened last
time. Next time I'll be able to find this post!
Cheers, Syms.
"Symon" <symon_brewer@hotmail.com> wrote in message
news:43d141f8$0$15794$14726298@news.sunsite.dk...
Guys,
I'm using ISE 7.1.04i . In PAR I get this error:-

ERROR:par:228 - At least one timing constraint is impossible to meet
because component delays alone exceed the constraint. A physical timing
constraint summary follows. This summary will show a MINIMUM net delay for
the paths. The "Actual" delays listed in this summary are the UNROUTED
delays with a 100ps timing budget for each route, NOT the achieved timing.
However, it's only failing because the tool thinks there's 100ps delay
between each element in the carry chains. So, for a 32 bit carry chain the
damn thing's subtracting 3.2ns from my timing budget. ISTR having this
problem before and fixing it, can anyone remind me, Google couldn't.

Similar stuff in another project is fine.

TIA, Syms.
Click to expand...
 
<comp.arch.fpga.FAQ@gmail.com> wrote in message
news:1137789842.944573.325940@g14g2000cwa.googlegroups.com...
Yes, I KNOW about that one.

Do you really think our first time visitors visit that site before
doing their first post? Just cross-check the newsgroup and the FAQ and
you will notice that people does not seem to care much about that
site.Besides, it's on Fliptronics site. They can take it down when ever
they want.

In any case, you guys could come with comments and suggestions. We
could even send them to http://www.fpga-faq.org, if you like that
better.


By the way, your post reminded me of another thing in this newsgroup I
find VERY annoying: people that write you a response that contains a
link with no explanation at all. And most of the responses are
completely off topic or at best they have misunderstood the question.
Is it too much to ask for a decent answer? Did my questions really
sound that stupid or do you think I don't know how to use google?

(this was a general observation and not really about your post)
Click to expand...
Would you prefer "This is the site for an existing fpga faq:
www.fpga-faq.org" ?

If it's not obvious by context, don't bother with the link - the
information's not very useful so don't use it.

I also don't understand how a different FAQ would help out because there is
no "must view this FAQ before posting" capability here. It's become obvious
to me that things are much better here at comp.arch.fpga. I'v started
looking in on sci.electronics.design and can't stand the unrelated chatter,
insults, and mindnumbing topics that show up there. We've got it good here.
 
Why even bother with Ethernet? Two FPGA's from any vender will talk with
very little troubles. Do you need speed or distance?

Simon


<martinh@qualcomm.com> wrote in message
news:mfa2t15d98ot783c0i01p5n279nn3t0s4d@4ax.com...
Has anybody had any showstopping problems when interconnecting
Stratix-II and Virtex4 (EP2S180 & LX200) ? We just want to have a mass
differential interconnect for a source-synchronous interface on
'left-over' pins for future expansion. Have never used Altera before
but I realize the banking is quite different.
Also, any experiences good or bad with 10GB Ethernet MAC cores from
both Xilinx and Altera ?

Thanks,

-Martin
Click to expand...
 
Some topics I would like to see addressed in the FAQ:

Something about all the myriad file formats Xilinx's tools (ISE &
others)
use, e.g. what all these three-letter acronyms mean:

"... but the XDL (or NCD) does __not__ contain bitstream info, it does
hold the
design info that is not mapped to the bitstream by bitgen later.
NCD (that can be viewed as XDL after conversion) is used together
with BFD (NeoCad Bitstream Format Database ?) file by bitgen for
actual bitstream generation.
there are some other files for each family, like GRD, etc I am able to
view pretty much all of the files used by Xilinx tools, (NGC, NCD, etc)
but..."

(This was from Antti's recent message. And why not to add a whole
topic about bitstream generation as well?)

Other thing I (and many others) have needed:

Basics about using Xilinx's DCM-stuff. Concrete examples in VHDL and
Verilog.
And what one writes to UCF-files?

Yes, I know a lot's of this stuff can be found from their appnotes, if
one has time
to browse through them.


Yours,

Veli Igor
 
On Fri, 20 Jan 2006 21:14:35 -0000, "Symon" <symon_brewer@hotmail.com>
wrote:

comp.arch.fpga.FAQ@gmail.com> wrote in message
news:1137789842.944573.325940@g14g2000cwa.googlegroups.com...


Just cross-check the newsgroup and the FAQ and
you will notice that people does not seem to care much about that
site.Besides, it's on Fliptronics site. They can take it down when ever
they want.

Good point. I wouldn't trust them either. Probably run by some dodgy
fly-by-night bloke.
Click to expand...
I can hear Philip laughing from here.

(in case it's not obvious: he's left it up for about a decade to my
knowledge, maybe longer. I don't think he's in a hurry to take it down)

- Brian
 
Peter

Do not fuel the fire by alleging racism and the like, instead consider that
the originator of the posting has a valid point as far as he /she is
concerned and rebut solely in respect to the issue which is in my opinion
(only) 'whether sharing knowledge is a dangerous practice in respect to
maintaining a competitive edge'.

MFT

"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1137815335.194191.36320@o13g2000cwo.googlegroups.com...
Irrelevant, stupid, racist, and worse.
That's what the thread "shooting ourselves in thefoot" is.
But it received over 100 postings in a day, mostly from people that
have nothing meaningful to say.
Well, most of the idiotic postings come cross-posted from other
newsgroups.

Our best response will be to let this embarrassing nonsense burn out.
Just ignore it.
It would be a shame if our relatively sane newsgroup would get infected
by this brainless drivel.
Peter Alfke
Click to expand...
 
"Philip Freidin" <philip@fliptronics.com> wrote in message
news:6q33t15qjnc5cbekr7280lm95a64e2lv7i@4ax.com...
Symon Says:
Good point. I wouldn't trust them either. Probably run by some dodgy
fly-by-night bloke.
Good luck, Syms.

Thanks Syms. You owe me another lunch next time you are in town.
(And I notice you again posted "Freidin's Clock Aligner" circuit
again, and failed to give attribution. If you do it again you will
owe me a desert of my choosing (triple chocolate decadence cake)).

Hi Philip,
Click to expand...
OK, ok, I added proper credit to the thread! As penance, I'll still get the
dessert AND write a little article about it for the FAQ. (The fpga-org.com
FAQ that is!)
Cheers, Syms.
 
On a sunny day (20 Jan 2006 19:48:55 -0800) it happened "Peter Alfke"
<alfke@sbcglobal.net> wrote in
<1137815335.194191.36320@o13g2000cwo.googlegroups.com>:

Our best response will be to let this embarrassing nonsense burn out.
Just ignore it.
It would be a shame if our relatively sane newsgroup would get infected
by this brainless drivel.
Peter Alfke
Then dont write it.
Click to expand...
 
Hi Jaime,

Brian made a good point to run your design outside HDL designer. I had a
similar problem some time ago and fixed it by un-ticking the "Enable
Communication with HDS" tickbox which you find on the start Modelsim
dialogue box. I would also suggest to update HDS to 2005.2 if you are not
already running that version.

Hans.
www.ht-lab.com

"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:atk4t1pes94aspjl40ctfuns8mdkgrvvrn@4ax.com...
On 20 Jan 2006 17:01:12 -0800, "Jaime Andrés Aranguren Cardona"
jaime.aranguren@gmail.com> wrote:

Hello,

I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine.
However, if I use the "add wave *" command, ModelSim smply quits,
regardless of what I put in the "*" field.
Invoking it from FpgaAdvantage 6.1 shows me the following:

** Fatal: (SIGSEGV) Bad pointer access. Closing vsim.
** Fatal: vsim is exiting with code 211.
(Exit codes are defined in the ModelSim messages appendix
of the ModelSim User's Manual.)

How can I solve this?

I don't have the answer, but there are a couple of things to try.

(1) there may be problems in the interaction between HDS and Modelsim.
So try invoking ModelSim standalone, loading the design, and "Add Wave"
from its own GUI, and see if the problem persists.

(2) I vaguely remember at least one "bad Modelsim" around that era; it
may be worth finding out the latest Modelsim you are licensed to run. If
you are running it, then try a slightly earlier one...

My distributor was very good about helping to the extent they could on
an expired ("out of maintenance") licence, it ensured I came back to
them when the company had more money!

- Brian
Click to expand...
 
<yusufilker@gmail.com> wrote in message
news:1137862857.742434.245230@g43g2000cwa.googlegroups.com...
Jan Panteltje wrote:
On a sunny day (21 Jan 2006 05:18:15 -0800) it happened
yadurajj@yahoo.com
wrote in <1137849495.660143.123320@g49g2000cwa.googlegroups.com>:

Can I use an FPGA to control a programmable pwer supply..if so are
there any such implementations already available..or if it is a
feasible idea...any feedback greatly appreciated..
thnks

Eh... maybe wrong... you can use a FPGA you can use even a trained
monkey.
If the result is what you want depends in the case of the FPGA on the
programming, same for the monkey.

And on the interface too.... monkey should be able to twiddle knobs,
FPGA output should be compatible with power supply control input.

You do not need an fpga for this but

With PWM , simple closed loop control and a LC filter can solve your
problem.
A FPGA adds 7 segment display, a few buttons to adjust voltage manually
or
even RS-232 control is very feasable.
ok you have a fpga then you can make it multiple output power supply.

Just for fun add sinusoidal outputs to make it universal.(Again PWM)

yusuf
Click to expand...
Could do the same with a pic or even a cpld
 
"Olaf Petzold" <olaf@mdcc-fun.net> schrieb im Newsbeitrag
news:dqvdse$jnd$1@viper.mdlink.de...
Hello,

with the following code snipped I have Problems on synthese/fit process on
xst Web/ISE 8.1 (the behavioral simulation works fine) for a CPLD XC95000:

[snip]
Click to expand...

Hi Olaf,

this is what 8.1 does from your code (I copy pasted your code with NO
mods!!), XC9500 as target

--------

arm <= ((start AND NOT reset AND NOT stop) OR (NOT reset AND NOT stop AND
arm.LFBK));
FDCPE_en: FDCPE port map (en,arm.LFBK,clk,reset,'0');

--------

as you see the stop input is present and not optimized away !!

Antti
 
"Olaf Petzold" <olaf@mdcc-fun.net> schrieb im Newsbeitrag
news:dqvj42$kfi$1@viper.mdlink.de...
Thanks Antti,

this is what 8.1 does from your code (I copy pasted your code with NO

using the same (with sp1)

mods!!), XC9500 as target

--------

arm <= ((start AND NOT reset AND NOT stop) OR (NOT reset AND NOT stop AND
arm.LFBK));
FDCPE_en: FDCPE port map (en,arm.LFBK,clk,reset,'0');

--------

as you see the stop input is present and not optimized away !!

interesting, from what file is it? Attached my fitted file with entity.

I've got from Fitter report:
Click to expand...
Dear Olaf,

1) do not try to oversmart the tools, it doesnt work. I do not know what you
are doing, but when I tested your code in new project all default setting
all worked properly.

2) it looks like the code you have trouble is part of logic analyzer - so
call me killjoy, but XC95xx is not a part you would use for logic analyzer,
so select suitable device and the problem you are having would not be there
at all.

doing a logic analyzer (a simple one) is really piece of cake. doing a good
one just means doing the specifications the implementation is not an issue
at all.

I just feel that you have spend a lot of your time in your logic analyzer
project without having anything useable to demonstrate so far.

I just dont have enough fingers (only 37 on last count) to implement some
logic analyzer properly, I would do it targettable to any Xilinx FPGA using
configuration readback (capture storage reading ) and partial
reconfiguration (for trigger settings).



Antti
 
Hi, Olaf:
Please complete all the state in your if-else statement.


"Olaf Petzold" <olaf@mdcc-fun.net> ??????:dqvdse$jnd$1@viper.mdlink.de...
Hello,

with the following code snipped I have Problems on synthese/fit process on
xst Web/ISE 8.1 (the behavioral simulation works fine) for a CPLD XC95000:

---8<---
library ieee;
use ieee.std_logic_1164.all;

entity synchronized_gate is
generic (
RESET_ACTIVE : std_logic := '1');
port (
reset : in std_logic;
clk : in std_logic;
start : in std_logic; -- start synchronizing
stop : in std_logic; -- stop synchronizing
en : out std_logic);
end entity synchronized_gate;

architecture behavioral of synchronized_gate is
signal arm : std_logic;
begin
-- arming RS-FF (asynchronous, latch inference)
arming_ff : process (reset, start, stop) is
begin
if (reset = RESET_ACTIVE) then
arm <= '0';
-- stop has precedence before start!
elsif (stop = '1') then
arm <= '0';
elsif (start = '1') then
arm <= '1';
end if;
end process arming_ff;

-- edge triggered gate control FF
clk_gate : process (clk, reset) is
begin
if (reset = RESET_ACTIVE) then
en <= '0';
elsif rising_edge(clk) then
en <= arm;
end if;
end process clk_gate;
end architecture behavioral;
--->8---

The synthese say:
WARNING:Xst:737 - Found 1-bit latch for signal <arm>.
which is OK. The fitter message is:
WARNING:Cpld:1007 - Removing unused input(s) 'stop'. The input(s) are
unused
WARNING:Cpld:828 - Signal 'arm.RSTF' has been minimized to 'GND'.

Well, looking at RTL and Technology Schematics all is as expected. If I
have a look into the generated post fit vhdl file, the signal stop is
really missing.

What are xst doing here, why?

Using Fitter's "preserve unused input" preserves the signal self, but the
signal stop doesn't have any functionality any more.

Therefore all post-fit simulation fails. Any help here?

Regards,
Olaf
Click to expand...
 
"Olaf Petzold" <olaf@mdcc-fun.net> schrieb im Newsbeitrag
news:dqvdse$jnd$1@viper.mdlink.de...
Hello,

with the following code snipped I have Problems on synthese/fit process on
xst Web/ISE 8.1 (the behavioral simulation works fine) for a CPLD XC95000:
Click to expand...
http://bugs.xilant.com/view.php?id=7

Hi Olaf,

sorry - I did not pay enough attention to "8.1" - I do have 8.1 installed as
secondary ISE so I tested your code on 7.1

the code does invoke a PLD fitter bug that is new to 8.1, that is your code
works correctly when target arch is FPGA or ISE version is 7.x or earlier.

with XC95xx as target and 8.1 the input signal does get optimized away as
you describe. so I have added it to the public bug track database :)

antti
 
Hi John,

he is looking at DAC output not at LVDS signals. he said assume the wires
__and__ DAC are working properly, so hes oscilloscope is on the output of an
LVDS DAC

Antti

"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> schrieb
im Newsbeitrag news:dr0oor$gck$1@newsg2.svr.pol.co.uk...
Frank

Remember to check the scale on your oscilloscpe. The LVDS signal is very
small and easy to miss if setup for something like TTL levels. I've done
that before myself. If you are using Xilinx you can check if LVDS is
implemented from the pin file I think or do it my favorite way in by
looking at the design in FPGA editor.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

"Frank Schreiber" <frankschr@googlemail.com> wrote in message
news:dr0fec$kvu$1@anderson.hrz.tu-chemnitz.de...
Dear all
I'm starting with LVDS.
My task is sending 8-bits signal to LVDS Transmitter port on my board.
I declared a 8 bits vector, assigned pins, and changed values in 8-bits
signal, but nothing happended in my oscilloscope. Assume that pins-out
are
right assigned, all wires and DAC are working perfectly.
Can anyone advise me, how to make it works.
Many thanks
Frank
Click to expand...
 
Not entirely clear to me that he is looking at the DAC output from those
words. Didn't even say that the oscilloscpe was actually connected never
mind what to.

Frank give us all a bit more info. We might be assuming something or nothing
correctly. The old swing on the tree graphic is coming to mind.

John Adair
Enterpoint Ltd. - We're at DATE2006. Come and say hello.
http://www.enterpoint.co.uk


"Antti Lukats" <antti@openchip.org> wrote in message
news:dr0p4c$bs9$1@online.de...
Hi John,

he is looking at DAC output not at LVDS signals. he said assume the wires
__and__ DAC are working properly, so hes oscilloscope is on the output of
an LVDS DAC

Antti

"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> schrieb
im Newsbeitrag news:dr0oor$gck$1@newsg2.svr.pol.co.uk...
Frank

Remember to check the scale on your oscilloscpe. The LVDS signal is very
small and easy to miss if setup for something like TTL levels. I've done
that before myself. If you are using Xilinx you can check if LVDS is
implemented from the pin file I think or do it my favorite way in by
looking at the design in FPGA editor.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

"Frank Schreiber" <frankschr@googlemail.com> wrote in message
news:dr0fec$kvu$1@anderson.hrz.tu-chemnitz.de...
Dear all
I'm starting with LVDS.
My task is sending 8-bits signal to LVDS Transmitter port on my board.
I declared a 8 bits vector, assigned pins, and changed values in 8-bits
signal, but nothing happended in my oscilloscope. Assume that pins-out
are
right assigned, all wires and DAC are working perfectly.
Can anyone advise me, how to make it works.
Many thanks
Frank
Click to expand...
 
On 22 Jan 2006 08:03:53 -0800, "Sudhir Shetty"
<sudhirshettyk@gmail.com> wrote:

Hi ,
I create a instance of DCM as follows :

DCM i_DCM (...
...
...
) /* synthesis xc_props ="DLL_FREQUENCY_MODE =
LOW,DUTY_CYCLE_CORRECTION = TRUE, <more parameters > */; //note this
directive is on a single line without line-breaks


But I see that in the post-synthesis .vm file there is no defparams
added for these attributes.
Click to expand...
That's normal as there is no tool which would need those parameters at
that point. What's important is whether those parameters get written
to the EDF file which goes into the PAR correctly and whether the
Xilinx toolset uses the properly.
 
Tim wrote:
Guess I'm not the only one but I keep an excel file updated with all the key
xilinx and altera parts that I'll likely use.

There's also a handy part comparison generator (Xilinx only),
Click to expand...
brought to us by the friendly janitorial staff over at Fliptronics,
that can be found over here:

http://www.fpga-faq.org/compare/build_form.cgi

Brian
 
Thanks to all of you who replied. I played around a bit with the
subject, and finally could solve it. I had some problems with the
license environmental variable (WinXP Home). NOw runs flawlessly.

Regards,

JaaC
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top