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integrate the edk system in your own top level?Since you have System ACE CF in your system that is the easiest way to
load both bitstream and ELF file. Please read up in the EDK
documentation how to generate an ACE file for your system.
- Peter
Andi wrote:
Hi,
do you want to run the program out of sdram or out of the bram? What is
the size of the c-code? Do you use the edk system as top level? Or do you
The tool flow from edk supports the mechanism to fit the c-code -
elf-file in the bram during the bitgen procedure.
Then when the fpga is loaded the c-code starts directly.
I don't know who told you that the XBD for ML402 isn't included inHI Allan,
I am myself looking for the same. Am using EDK6.3/ISE6.3i. I am also
told that there is no XBD included even in EDK7.1 for the ML402 board.
Allan, were you able to build the reference design without any errors?
For me, the reference design generates lots of errors about unavailable
versions of peripherals referenced in the design. What service packs
are you using.
Any help appreciated.
TIA,
Abhishek
I've always like this paper as a good introduction to intra-domainI am attempting to get data (column_in) from a fast
clock domain(clk_wr) to a slow clock domain(clk_rd).
Hi,
how is the interrut signal specified? As low or high activ edge/level ?
How does the mhs file look like?
Austin Lesea <austin@xilinx.com> writes:
snip
http://www.xilinx.com/products/virtex4/overview/performance.htm
is a good review of V4, which illustrate how we beat all other FPGAs
in EVERY category.
Interesting - why did you not use Synplify for the Altera side of
things - was it worse than Altera's synthesiser?
Cheers,
Martin
Austin Lesea schrieb:
In order to remove or minimize the variation in timing in SOI from the
floating wells, one needs to add taps. The addition of the taps to
every well, results in the area increasing dramatically. That makes the
FPGA cost too much, hence the process is not commercially viable. This
has been one of the reasons for its non-use.
Also, without knowing as much detauls as austin, I suspect that in a
design as heavily dominated by interconnect as an FPGA the area increase
results in longer wires which increases capacitance and therefore power
consumption and delay. This mitigates the two main advantages of SOI.
Kolja Sulimma
equivalent bits you get. You'll have to parallel a bunch of pins to getI'm playing around with sigma-delat ADC and DAC for audio. It's amazing
how good this works without any active components. Just Rs and Cs.
The sigma-delta works really well, and the faster you clock it the more
Yes, you have to initialize the mouse. Read this document for informationI've visited the xess website; however, there's only one example for
mouse and the source codes are in Spanish. Anyways, I tried to figure
out what those codes mean and downloaded the bitstream to the fgpa;
however, that doesn't work. I am not sure whether the code is not
working or I have set something wrong. Anybody has experience using
the PS/2 port of XSA-3S1000 board with XST 3.0?
If I just wanna read the mouse, do I have to initialize the mouse
first? If then, how?
Austin Lesea <austin@xilinx.com> writes:
snip
http://www.xilinx.com/products/virtex4/overview/performance.htm
is a good review of V4, which illustrate how we beat all other FPGAs
in EVERY category.
Interesting - why did you not use Synplify for the Altera side of
things - was it worse than Altera's synthesiser?
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Especially when the final (newer) Stratix II timing models have DSPs &Also kind of funny that they used a Quartus version three revisions old,
and the latest ISE and Synplify?
integrate the edk system in your own top level?Since you have System ACE CF in your system that is the easiest way to
load both bitstream and ELF file. Please read up in the EDK
documentation how to generate an ACE file for your system.
- Peter
Andi wrote:
Hi,
do you want to run the program out of sdram or out of the bram? What is
the size of the c-code? Do you use the edk system as top level? Or do you
The tool flow from edk supports the mechanism to fit the c-code -
elf-file in the bram during the bitgen procedure.
Then when the fpga is loaded the c-code starts directly.
Amen.and how well the feature set of that chip augment your design. Both are
good products, and
you won't go wrong with either as long as you pay attention to the
device architecture as you
develop your design.
Ray -- please don't take a job working for any of the FPGA vendors!Paul Leventis (at home) wrote:
basically, "mine is bigger"
*Sigh*, here we go again.