EDK : FSL macros defined by Xilinx are wrong

I did this with 63 inputs all 32bits wide in a plain virtex 800 many
yrs ago

If you are building a syncronizer for a 64 bit sync field, if you can
cut off 1 bit either the 1st or last and use 63 bits, you can save the
last row of adders. Since mine was 32 wide it save alot more than 6
adders. The 1 bit loss probably wouldn't affect a syncronizer
application.

I wouldn't want to replicate 3 BRAMs 32 times though.

Whats the application?
 
Brad Smallridge wrote:
Hello Group,

What is the best way to count 64 incoming simultaneous
bit signals to determine the number of 1s (in VHDL)?
I have clock cycles to spare but the result must be pipelined
so that each clock cycle produces a new count.
Click to expand...
In case you haven't found it yet, VHDL code for 30 bits (without
pipelining, that should be easy to add as a bunch of registers at the
end, which XST or Synplify may apply register re-timing to) was posted
at:

http://groups-beta.google.com/group/comp.arch.fpga/tree/browse_frm/thread/d838401f654184a8/bc0f119b852d8a5b?rnum=11&hl=en&q=counting+ones&_done=%2Fgroup%2Fcomp.arch.fpga%2Fbrowse_frm%2Fthread%2Fd838401f654184a8%2Fef8589c7332f93f9%3Fq%3Dcounting+ones%26rnum%3D1%26#doc_7480e49da22bae56

Should be straightfoward to extend to 64 bits.

If it's not too much trouble, can I ask what is the application?
I thought the circuit was neat, but wonder how folks use it.

John
 
JJ, I hope you realize that 3 BRAMs is all you need. Nobody would
suggest to replicate them. For what??
Peter Alfke
 
< Using 63bits rather than 64 bits takes precisely 63 adder cells>

Should say
Using 63bits rather than 64 bits takes precisely 63-6 adder cells and
64 bits take 63.

Its been awhile.
You probably didn't realize I was using 32x for oversampling
 
Doesn't ML401 board come with a ucf?

Jim

"Nenad" <n_uzunovic@yahoo.com> wrote in message
news:1121968704.986524.226490@g47g2000cwa.googlegroups.com...
Has anyone activated this yet?

i found this ddr controller on the xilinx website: memory interface
generator (MIG). it was on demos on demand as well. it is a simple
program that supposedly generates everything you need. it seems neat,
hdl seems ok. though it's done on ML461 board and it gives wrong .ucf
files even for ML461 itself (there is another sample code of pretty
much same controller there (xapp709) so i compared it with the
generated one).

can someone please help me with the pinouts here. i've figured out data
and address pins (well, i think i have) and now i am left with
controls.

thanks
Click to expand...
 
Well it comes in a form of schematic diagram which is messy to read. i
couldn't find table of pinouts like i had for other boards i worked
with.

but i think i worked it out this way. i went trough some crazy files
and extracted what i needed.

thanks for answering
 
I have a UCF file for ML401. If you'd like please contact me directly
(remove all capital letters in my email address) and I will send it to
you.

Jim
 
im.de napisał(a):
Hi, there

I am creating a project with Spartan 3 board. and wanna add DCM into
the XPS 6.2 project under menu "project- add/edit cores(dialog)"

What I want is to get the clock down to clock/2.
There are 3 moduls in the DCM, I am using the digital frenquency
synthesizer (DFS).

I added 3 ports: "clkin", "rst" as input, "clkfx" as output in the
internal ports connections, didnot add anything into the external ports
connections.

connected the "clkin" to "sys_clk"=50mMHz of the external ports,
reconnected the clock input ports of other components who HAD "sys_clk"
as input to the output port "clkfx"

the parameters I have
c_clkfx_multiply = 1
c_clkfx_divide = 2
c_clkin_period = 40.000000 <----- which i am not sure the use of this
parameters.

But it did not work out.
Click to expand...
Is that any special needs to use DCM?
If I were You I would use just flip-flop.
It'll be faster for lock - instant,
and 50%-50% low-high.

If you must use DCM, make it like Antti Lukats wrote.

Best regards

Jerzy Gbur
 
Jedi wrote:
Moro

Back from a successful trip in .ch I have to change
my contact details at Altera and they provide
an email address for doing this:

csecom@altera.com

which just leads into nirvana and bounces back
with "user unknown"...

Any other address to use? Or why is it not allowed to
change address online?
Click to expand...
I guess nobody at Altera discovered this or don't care?


rick
 
"Jedi" <me@aol.com> schrieb im Newsbeitrag
news:i74Fe.125$Sg3.58@read3.inet.fi...
Jedi wrote:
Moro

Back from a successful trip in .ch I have to change
my contact details at Altera and they provide
an email address for doing this:

csecom@altera.com

which just leads into nirvana and bounces back
with "user unknown"...

Any other address to use? Or why is it not allowed to
change address online?

I guess nobody at Altera discovered this or don't care?


rick
Click to expand...
they dont care
 
I think that the problem is in multiply settings, as the minimum value of M
is 2.
But did not you get a warning in the synthesis about this?

Vladislav


"im.de" <im.de@gmx.de> wrote in message
news:1122255963.249305.307550@o13g2000cwo.googlegroups.com...
Hi, there

I am creating a project with Spartan 3 board. and wanna add DCM into
the XPS 6.2 project under menu "project- add/edit cores(dialog)"

What I want is to get the clock down to clock/2.
There are 3 moduls in the DCM, I am using the digital frenquency
synthesizer (DFS).

I added 3 ports: "clkin", "rst" as input, "clkfx" as output in the
internal ports connections, didnot add anything into the external ports
connections.

connected the "clkin" to "sys_clk"=50mMHz of the external ports,
reconnected the clock input ports of other components who HAD "sys_clk"
as input to the output port "clkfx"

the parameters I have
c_clkfx_multiply = 1
c_clkfx_divide = 2
c_clkin_period = 40.000000 <----- which i am not sure the use of this
parameters.

But it did not work out.


Anyone has some idea?
thanks
Click to expand...
 
Antti Lukats wrote:

Excalibur is DEAD.
dont use it.
Click to expand...
I recently had a discussion with a manager at a large company that
wanted to build a system based on an ARM. This manager was thinking
about Excalibur until finding out it was not recommended for new
designs, and that there wasn't a replacement.

He had one question I couldn't answer:

Why?

ARM seems to be very popular. An ARM in an ram-based FPGA with enough
gates to make the interfaces required would have made a nice product.
Not worth rewriting a bunch of software to fit it into a V4 with a
PPC.

Why did Excalibur die?


--
Phil Hays
Phil-hays at comcast.moc (remove moc and add net) should work for
email
 
"Phil Hays" <Spampostmaster@comcast.net> schrieb im Newsbeitrag
news:lb2ae1l5i3gj9nnbhg00cfr9eikfd3shr2@4ax.com...
Antti Lukats wrote:

Excalibur is DEAD.
dont use it.

I recently had a discussion with a manager at a large company that
wanted to build a system based on an ARM. This manager was thinking
about Excalibur until finding out it was not recommended for new
designs, and that there wasn't a replacement.

He had one question I couldn't answer:

Why?

ARM seems to be very popular. An ARM in an ram-based FPGA with enough
gates to make the interfaces required would have made a nice product.
Not worth rewriting a bunch of software to fit it into a V4 with a
PPC.

Why did Excalibur die?


--
Phil Hays
Phil-hays at comcast.moc (remove moc and add net) should work for
email
Click to expand...
you possible need to ask the lawers of ARM, and you possible do not get an
answer.

Actel is promising soft-core ARM licensing for their PA3 family. But there
is no PA3 silicon shipping as of today.

the chinese nnARM softcore nnARM core, it does synthesise ok, but its very
huge :(, well at least the register
array is done badly as it alone occupies 50% of Virtex-4 LX25, I havent
looked if the rest of the nnARM
is useable if the register bank would be optimized

Antti
PS the nnARM source code should be easy to locate with google if anyone has
interest in it.
 
Amr, there is no exact time, only a statistical probability.
ICs do not suffer from a clearly defined wear-out mechanism that would
allow us to predict the end-of-life.
There is a wide variety of factors that affect reliability, and there
is the Arrhenius model that describes the dependence on temperature,
but all predictions are statistical.
And at "normal" temperatures, ICs live a very long life, 20 to 100
years or more.
Most failures are the result of overstress, mostly in the I/O.
Peter Alfke, Xilinx
 
"Phil Hays" <Spampostmaster@comcast.net> schrieb im Newsbeitrag
news:gk6ae19lkccq0c5prrse7b7kqg34etu025@4ax.com...
"Antti Lukats" wrote:

"Phil Hays" wrote:

I recently had a discussion with a manager at a large company that
wanted to build a system based on an ARM.

Why did Excalibur die?

PS the nnARM source code should be easy to locate with google if anyone
has
interest in it.

Right. But large companies are not interested in attracting sharks...
I mean lawyers.

Also the clock rate would need to be higher than I think that a
softcore processor written as a student project is likely to achieve.


--
Phil Hays
Phil-hays at comcast.moc (remove moc and add net) should work for
email
Click to expand...
yes you are right, the core would possible run at 10..20MHz
I am still wondering ARM sharks did run off at those students, its not a
real useable core,
well the reason was possible that the core was not 100% as ARM had license
some source
code to china universities and those students had access to that code

Antti
 
The simulation models for block RAMs use an array to store memory
content. You can view the content of the array like you view any other
variables.

Jim
 
Hi Martin,

I figured out the problem. The driver that Xilinx releases isn't the
best, and very fragile. It compiled today with no issues, but
yesterday it didn't.

The windrvr.o didn't want to build due to an error with rights of the
files. I just chmod 777 the whole directory and re-made it and it
works.
 
"arie" <aries@wisair.com> schrieb im Newsbeitrag
news:1122326731.202651.187530@g44g2000cwa.googlegroups.com...
I know the device is not recomended for new designs, i use it for
prototyping,
final product will be based on ASIC with ARM core inside. i dont know
of any other protoyping solution that can offer 200MHZ ARM9 processor +
fpga.

Arie

try STW22000 from ST and forget Altera
Click to expand...
ARM926 300MHz + FPGA

Antti
 
Antti Lukats wrote:

"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag
news:42e540a2$0$8024$3b214f66@tunews.univie.ac.at...

Xilinx FPGA's are nice but all of them (after XC4K?) do not have any
more
access to the OnChipOscillator - it is not usually required also, but in
some rare cases it may be useful to have some OnChip Clock available in
case
all external clock sources fail, or do have emergency Watchdog timer to
monitor some events also in the case of external clock circuitry
failures.
For this purpose we are developing OnChip Oscillator IP Cores.

http://gforge.openchip.org/frs/?group_id=32
Click to expand...
Interesting - any data on Vcc and temp variations, and on other
frequencies ?

Power consumption ?
Seems to me, it would be better to create a clock as low as possible,
before driving the high-load clock buffers. - thus a cell that is
both OSC and Divider could be better ?


An advantage of on chip Osc, is they self-margin, so track Vcc and Temp.
If I've understood your results, they show quite close correlation
across the die.

This would also be a good way to see if faster speed grades REALLY are
faster, or just stamped to match the market :)


Just looked at the sources - There are binary VHDL files. What does
this mean?

Martin


This means they can only be used by ISE tools. There should be no problems
using those files with ISE 6.2 to 7.1, just add to your project and
synthesise as normal. If there are any problems let me know.
Click to expand...
?! - do you mean you cannot save as ASCII source code, or use any other
editor ?
Surely this nonsense can be disabled ?

-jg
 
Hi Austin,

If I understand you correctly, the FIT numbers given in reliability
reports are not representative of actually anything useful. It is just
provided for complying with the industry standard.

One more thing, according to the Arrhenius relatonship and the way the
thermal acceleraion factor is calculated, there is only one stress
junction temperature for testing the device. In other words, the
devices are exposed to constant stress loading as opposed to step or
random stress. is that right?

One last issue: Is the Voltage accelaration factor used in calculating
the FIT numbers given in the Xilinx reliability report? or is it just
the thermal acceleration factor? I'm not sure you are allowed to answer
this last question :)

Thanks,

Amr
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top