need a cheap student edition FPGA

glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
glen herrmannsfeldt wrote:
Jason Zheng wrote:

Has anyone compiled cver on a sparc platform?


I tried to compile it on a sun blade 1000 workstation, but i get the
following error:


(snip)

Undefined first referenced
symbol in file
strerror_r ../objs/v_ex.o
ld: fatal: Symbol referencing errors. No output written to ../bin/cver


strerror_r is the reentrant version (with an extra argument) of
the C library strerror routine. It seems that Solaris doesn't have one.

It might be that source is readily available, though I am surprised that
to configuration script didn't figure it out.

-- glen

cver source tarball didn't come with a configure script. Do you know of
Click to expand...
any detour to this issue?

thanks,

Jason Zheng
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS :) But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...
SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi
Click to expand...
 
Chris Briggs wrote:
For simulation tools check out Cliff Cummings' Verilog-2001
scoreboard
doc at http://www.sunburst-design.com/papers/.
Click to expand...
It should be noted that this paper was written early in 2003, and is
a couple of years out of date by now. Tool vendors have not been
sitting still during that time.
 
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