C
Chris F Clark
Guest
I apologize for suggesting it might be a homework problem. It's
actually not school time and so the suggestion was unwarranted. (I
might have missed your first post also (or atleast not connected it).)
If it is a mismatch between simulation and physical implementation,
perhaps there is something in the physical implementation your model
doesn't account for. For example, perhaps the dip switch "Bounces".
What you are trying to build, where the switch acts as a toggle would
be susceptible to that. Using the dip as a reset wouldn't have the
same tempermentalness, as if one sees two (or more) rests in a row,
one isn't going to "notice", since in the end the signal still gets
reset. Tow toggles in a row are a different story.
If you could tie an indicator (e.g. an led) to the "state" part of the
design, so that the led would indicate which state the toggle is in,
you might see that it doesn't actually toggle (or toggles more than
once per push). Of course, if the problem is too quick, it might go
by to quick for you to see it.
Assuming that bounce is the problem, you could then ask how to
de-bounce your circuit (i.e. make it less sensitive to bounce). I
don't know what solutions are available there, but one possibility is
to make the circuit insensitive to a 2nd button push until a specific
amount of time (say a specific number of clock cycles) after the
first. Iamgine how you would change your circuit model so that the
dip button could only cause one change of the toggle per cycle.
Implement that and see if it effects your problem. If bounce is the
problem, whether that change will help depends on how fast your cycle
is relatively to how fast bounces settle.
If bounce isn't the problem, you need to keep looking until you can
find out what is. You're right about the differences between
unrealistic "academic" models and the real-world implementation.
Verilog models are a simplification of the real world and do not model
it completely faithfully. There are things which can happen in the
real world that your model is likely to miss and vice-versa: sometimes
the model can have artifacts that can never heppen in the real world.
Hope this helps,
-Chris
*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------
actually not school time and so the suggestion was unwarranted. (I
might have missed your first post also (or atleast not connected it).)
If it is a mismatch between simulation and physical implementation,
perhaps there is something in the physical implementation your model
doesn't account for. For example, perhaps the dip switch "Bounces".
What you are trying to build, where the switch acts as a toggle would
be susceptible to that. Using the dip as a reset wouldn't have the
same tempermentalness, as if one sees two (or more) rests in a row,
one isn't going to "notice", since in the end the signal still gets
reset. Tow toggles in a row are a different story.
If you could tie an indicator (e.g. an led) to the "state" part of the
design, so that the led would indicate which state the toggle is in,
you might see that it doesn't actually toggle (or toggles more than
once per push). Of course, if the problem is too quick, it might go
by to quick for you to see it.
Assuming that bounce is the problem, you could then ask how to
de-bounce your circuit (i.e. make it less sensitive to bounce). I
don't know what solutions are available there, but one possibility is
to make the circuit insensitive to a 2nd button push until a specific
amount of time (say a specific number of clock cycles) after the
first. Iamgine how you would change your circuit model so that the
dip button could only cause one change of the toggle per cycle.
Implement that and see if it effects your problem. If bounce is the
problem, whether that change will help depends on how fast your cycle
is relatively to how fast bounces settle.
If bounce isn't the problem, you need to keep looking until you can
find out what is. You're right about the differences between
unrealistic "academic" models and the real-world implementation.
Verilog models are a simplification of the real world and do not model
it completely faithfully. There are things which can happen in the
real world that your model is likely to miss and vice-versa: sometimes
the model can have artifacts that can never heppen in the real world.
Hope this helps,
-Chris
*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------