need a cheap student edition FPGA

On Monday, April 12, 1999 12:30:00 PM UTC+5:30, Liang Tao wrote:

Hi,

I am a new learner of Verilog and want to study it from a big example,
I want to know if anyone know such an example, eg., a RISC with source code and
detailed document?

Thank you veru much.

hi
plz send me vhdl code for mux d full scan cell

 

[rickman]

Not trying to be a jerk, but have you considered asking in a Verilog
group? This is a VHDL group. I'm just sayin'...

Tell you what, I've cross posted it for you.

Rick


On 4/6/2014 5:40 PM, sandhya pochiraju wrote:

Hi All, I have few questions in verilog. please can someone here help me understand this.


Let's say, db_count = debounce_cnt at 10th positive edge.
will "IF" condition in second always block be true at 10th positive edge?

or will "IF" condition in second always block be true at 11th positive edge? but on 11th positive edge db_count will be set to 0 by first always block.


what is order of operation between "IF" and "Case" ?
Though everything is in one always block and non blocking statements are used, "IF" and "Case" are two seperate blocks in themselves. Is the non-blocking behaviour of statements not confined seperately to "IF" and "Case" blocks? i.e. statements inside "IF" are non-blocking but are they non-blocking to statements inside "case" and vice versa?

Code:



`timescale 1 ns / 1 ns
module debounce (
//inputs
// what value is stored in pbtn_in and switch_in
input clk, // clock
input [3:0] pbtn_in, // pushbutton inputs
input [7:0] switch_in, // slider switch inputs

//outputs
output reg [3:0] pbtn_db = 3'h0, // debounced outputs of pushbuttons
output reg [7:0] swtch_db = 8'h0 // debounced outputs of slider switches
);
parameter simulate = 0;
// these are two ways to simulate.
// simulate is a parameter.
// what is the difference in two waits.

localparam debounce_cnt = simulate ? 22'd5 // debounce clock when simulating
: 22'd4_000_000; // debounce count when running on HW

//shift registers used to debounce switches and buttons
reg [21:0] db_count = 22'h0; //counter for debouncer
// 8 switches.
// 5 buttons.
reg [4:0] shift_pb0 = 5'h0, shift_pb1 = 5'h0, shift_pb2 = 5'h0, shift_pb3 = 5'h0, shift_pb4 = 5'h0;
reg [3:0] shift_swtch0 = 4'h0, shift_swtch1 = 4'h0, shift_swtch2 = 4'h0, shift_swtch3 = 4'h0;
reg [3:0] shift_swtch4 = 4'h0, shift_swtch5 = 4'h0, shift_swtch6 = 4'h0, shift_swtch7 = 4'h0;

// debounce clock
// at positive edge, count is incremented
always @(posedge clk)
begin
if (db_count == debounce_cnt) // it is 5 for simulation.
db_count <= 1'b0; //takes 40mS to reach 4,000,000
else
db_count <= db_count + 1'b1;
end

always @(posedge clk)
begin
// if this always and one is line 51 race condition.
// if 51 runs first, then db_count will be set to szero when below condition is true.
if (db_count == debounce_cnt) begin //sample every 40mS
//shift registers for pushbuttons
// i am shifting left once and doing a bitwise OR it with 0th bit of pbth_in
// why
// what is the value in pbtn_in
shift_pb0 <= (shift_pb0 << 1) | pbtn_in[0];
shift_pb1 <= (shift_pb1 << 1) | pbtn_in[1];
shift_pb2 <= (shift_pb2 << 1) | pbtn_in[2];
shift_pb3 <= (shift_pb3 << 1) | pbtn_in[3];
shift_pb4 <= (shift_pb4 << 1) | pbtn_in[4];

//shift registers for slider switches
// i am doing same operation here.
// all these happen at same time.
// what is the value in switch_in
shift_swtch0 <= (shift_swtch0 << 1) | switch_in[0];
shift_swtch1 <= (shift_swtch1 << 1) | switch_in[1];
shift_swtch2 <= (shift_swtch2 << 1) | switch_in[2];
shift_swtch3 <= (shift_swtch3 << 1) | switch_in[3];
shift_swtch4 <= (shift_swtch4 << 1) | switch_in[4];
shift_swtch5 <= (shift_swtch5 << 1) | switch_in[5];
shift_swtch6 <= (shift_swtch6 << 1) | switch_in[6];
shift_swtch7 <= (shift_swtch7 << 1) | switch_in[7];
end

//debounced pushbutton outputs
// if first four bits are zero then bit zero is set to 0
// if first four bits are one then bit zero is set to 1
case(shift_pb0) 4'b0000: pbtn_db[0] <= 0; 4'b1111: pbtn_db[0] <= 1; endcase
case(shift_pb1) 4'b0000: pbtn_db[1] <= 0; 4'b1111: pbtn_db[1] <= 1; endcase
case(shift_pb2) 4'b0000: pbtn_db[2] <= 0; 4'b1111: pbtn_db[2] <= 1; endcase
case(shift_pb3) 4'b0000: pbtn_db[3] <= 0; 4'b1111: pbtn_db[3] <= 1; endcase
case(shift_pb4) 4'b0000: pbtn_db[4] <= 0; 4'b1111: pbtn_db[4] <= 1; endcase

//debounced slider switch outputs
case(shift_swtch0) 4'b0000: swtch_db[0] <= 0; 4'b1111: swtch_db[0] <= 1; endcase
case(shift_swtch1) 4'b0000: swtch_db[1] <= 0; 4'b1111: swtch_db[1] <= 1; endcase
case(shift_swtch2) 4'b0000: swtch_db[2] <= 0; 4'b1111: swtch_db[2] <= 1; endcase
case(shift_swtch3) 4'b0000: swtch_db[3] <= 0; 4'b1111: swtch_db[3] <= 1; endcase
case(shift_swtch4) 4'b0000: swtch_db[4] <= 0; 4'b1111: swtch_db[4] <= 1; endcase
case(shift_swtch5) 4'b0000: swtch_db[5] <= 0; 4'b1111: swtch_db[5] <= 1; endcase
case(shift_swtch6) 4'b0000: swtch_db[6] <= 0; 4'b1111: swtch_db[6] <= 1; endcase
case(shift_swtch7) 4'b0000: swtch_db[7] <= 0; 4'b1111: swtch_db[7] <= 1; endcase
end
// if and case happen in parallel as it is non blocking statement. right.
// for simulation i am not waiting for as much as i am waiting for synthesis.
endmodule

--

Rick

 

вторник, 22 февраля 2000 г., 12:00:00 UTC+4 пользователь Tanya Brethour написал:

I am attempting to convert a MPEG decoder written in C to a Verilog version.
I am new to Verilog as you probably can guess This is a senior design
project so.. I can not just find one already written in Verilog on the
Internet.

Does anyone have any links to translators or compilers to accomplish this
task?

Thanks
Tanya

try to use russian project http://www.vsyn.ru (i hope they make english version)

 

[Gabor]

On 5/30/2014 9:53 PM, kaiyutony@gmail.com wrote:

Any Help Will Be Appreciated!

I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value.

The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count)

Is there any logical error? Or is there any Verilog Error that I missed?

Thank you very much!

module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2);
input Clock, Reset;
input signed [3:0] pt_0, pt_1, pt_2, pt_3;
output [6:0] hex1, hex0, hex3, hex2;

wire signed [6:0] count;
wire signed [6:0] maxcount;
score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);

display(count, maxcount, hex1, hex0, hex3, hex2);

endmodule

module display (count, maxcount, hex1, hex0, hex3, hex2);
input [6:0] count, maxcount;
output [6:0] hex1, hex0, hex3, hex2;

wire [4:0] unit, unit_m;
wire [4:0] tens, tens_m;

assign unit = count % 10;
assign tens = count / 10;

assign unit_m = count % 10;
assign tens_m = count / 10;

seg7 ud (unit, hex0);
seg7 td (tens, hex1);
seg7 umd (unit_m, hex2);
seg7 tmd (tens_m, hex3);


endmodule

module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);
input Clock, Reset;
//input signed [3:0] sum;
input [3:0] pt_0, pt_1, pt_2, pt_3;
parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110;
//input zero, negative, carry, overflow;

output signed [6:0] count, maxcount;
reg signed [6:0] count, maxcount;

////wire PS;
//reg NS;

always @(posedge Clock)
if (Reset) begin
count <= 7'b0;
maxcount <= 7'b0;
end else begin
if (count > maxcount) begin
maxcount <= count;
end
if (pt_0 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_0;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_1 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_1;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_2 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_2;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_3 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_3;
if (count > 7'b100010) begin
count <= 7'b0;
end
end
end
endmodule

There's nothing obvious to me. Is it failing in behavioral simulation
or only in hardware (you did simulate, right)?

I've had issues with signed arithmetic in Verilog, but in this
case count and maxcount have the same type, so I don't see
an issue with the logic. Could there be a problem with synchronization
to the clock? All inputs need to be synchronous to the clock,
especially Reset. Obviously a Reset pulse could cause maxcount
to go down.

--
Gabor

 

[rickman]

On 6/1/2014 9:12 PM, Gabor wrote:

assign unit_m = count % 10;
assign tens_m = count / 10;

I think the problem are these lines. He didn't say how he was checking
the result, but I bet it was by looking at the display of unit_m and
tens_m.

I bet we never hear back from him...

--

Rick

 

Hi Nicole,

I just stumbled on the name of the business, which started by a dear friend of mine, Judy O'brien. I wounder if she is still working there, I'd like to say hello to her.

take care,

Alex


On Tuesday, June 11, 1996 at 12:00:00 AM UTC-7, Sosplus wrote:

A high profile, cutting edge start-up is looking for a director of
software to lead a team of engineers in the development and deployment of
fast (gigabyte ethernet) network switching products. The group develops
network kernels, device drivers, and network management software. When
integrated with the company's innovative hardware, the system offers
dramatic performance improvement over existing products. Candidates must
have good interpersonal skills, an entrepreneurial drive, and be able to
contribute technically.

Requirements:

-Degree requirement: M.S.CS(minimum) or Ph.D.-CS (preferred)
-10+ years of overall S/W experience consisting of at least 6 years of
design and 4 years of management.
-extensive background in Object Oriented Design.
-a thorough understanding of network principles including bridging,
routing, and switching. Must be familiar with layer 2 and layer 3
networking issues.
-must have delivered a S/W product to market, both as an individual
contributor and as a manager.

If interested and qualified, please fax or mail your resume to:
Nicole Marie
Rainier Resource Group
951-2 Old County Rd. #201
Belmont, CA 94002
fax # 415/345-4077
or phone us at: 415/577-9768

 

On Wednesday, March 24, 1999 at 10:00:00 AM UTC+2, thefi...@my-dejanews.com wrote:

What are the main differences between timing and gate level simulation ?

Cheers...

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own

The gate level simulation purpose is to see that after synthesis your design works in simulation. Gate level with actual timing is usually used.
Please see an example with the free VHDL simulator GHDL, which only support gate level without timing (post NGD with xilinx flow)
http://bknpk.ddns.net/my_web/IP_STACK/synt_xst_1.html

 

[Ravali Thangellapalli]

On Monday, May 13, 2002 at 10:01:24 AM UTC+5:30, Chuck Benz wrote:

For anyone interested, I have completed an 8b/10b implementation,
per Widmer and Franaszek (IBM JRD, Sep '83). I've posted it
at http://asics.chuckbenz.com.

You can use it quite freely, I only ask that you keep my copyright
header notice intact, even if you change the module name, or merge
it into your verilog code, or even if you translate it to VHDL
(shouldn't be hard). It's coded as a combinational block, so you
would add your own flop external to each block to latch disparity.

Logic designers might find a few other interesting things at my site,
and I hope to continue to add useful stuff - please feel free to offer
any feedback.

\chuck

Chuck Benz
ASIC and FPGA design
newsbenz@chuckbenz.com
Sir..this code of output is not getting ....give me other simple type of code..iam presently working on this encoder.

 

[Nicolas Matringe]

Le 11/01/2016 16:21, Ravali Thangellapalli a ĂŠcrit :

On Monday, May 13, 2002 at 10:01:24 AM UTC+5:30, Chuck Benz wrote:
[...]
Sir..this code of output is not getting ....give me other simple type of code..iam presently working on this encoder.

Have you noticed this post is almost 14 years old ?

 

[Aleksandar Kuktin]

On Mon, 11 Jan 2016 21:33:05 +0100, Nicolas Matringe wrote:

Le 11/01/2016 16:21, Ravali Thangellapalli a ĂŠcrit :
On Monday, May 13, 2002 at 10:01:24 AM UTC+5:30, Chuck Benz wrote:
[...]
Sir..this code of output is not getting ....give me other simple type
of code..iam presently working on this encoder.

Have you noticed this post is almost 14 years old ?

The post may be 14 years old, but the site is still up and I'm kind of in
a market for free/open source hardware.

OTOH, the website features a writeup with a code example of a fifo which
does not do what the author thinks it does.

 

On Wednesday, September 5, 2001 at 6:23:57 AM UTC-7, Chun-Hung Lin wrote:

Dear Group

How do I write a "Edge Detection Logic"?
1. Detect a rising edge or falling edge of a signal, such as an event
detection for interrupt triggering.
2. Once an edge has been detected, it will be stored in a register.
3. A clear signal is required to clear the register.

I am thinking about using the signal pin as a clock.
However, it does not seem to work. What is wrong?

Thanks in advance.

Chun-Hung Lin
chlin007@my-deja.com

assign nsignal = ~signal;
always @(posedge signal or negedge nclear)//rising edge
begin
if(~nclear)//clear interrupt
r_status_reg <= 1'b0;
else
r_status_reg <= 1'b1;
end

always @(posedge nsignal or negedge nclear)//falling edge
begin
if(~nclear)//clear interrupt
f_status_reg <= 1'b0;
else
f_status_reg <= 1'b1;
end

Dear Mr.Chin-Hung,

I hope you're doing good.I am currently pursuing my Master's In Electrical Engineering and learning FPGA this semester. I understood the concept of Falling Edge & Rising Edge & how to implement with Quartus II.Now i want to implement both rising & falling edge detection at same time,can you help me out to do the same.



Thank you in advance for your time & consideration.


Regards,
Brijesh Darji
linkedin.com/in/darjibrijesh

 

[rickman]

On 1/27/2016 9:57 PM, brijeshdarji138@gmail.com wrote:

On Wednesday, September 5, 2001 at 6:23:57 AM UTC-7, Chun-Hung Lin wrote:
Dear Group

How do I write a "Edge Detection Logic"?
1. Detect a rising edge or falling edge of a signal, such as an event
detection for interrupt triggering.
2. Once an edge has been detected, it will be stored in a register.
3. A clear signal is required to clear the register.

I am thinking about using the signal pin as a clock.
However, it does not seem to work. What is wrong?

Thanks in advance.

Chun-Hung Lin
chlin007@my-deja.com

assign nsignal = ~signal;
always @(posedge signal or negedge nclear)//rising edge
begin
if(~nclear)//clear interrupt
r_status_reg <= 1'b0;
else
r_status_reg <= 1'b1;
end

always @(posedge nsignal or negedge nclear)//falling edge
begin
if(~nclear)//clear interrupt
f_status_reg <= 1'b0;
else
f_status_reg <= 1'b1;
end

Dear Mr.Chin-Hung,

I hope you're doing good.I am currently pursuing my Master's In Electrical Engineering and learning FPGA this semester. I understood the concept of Falling Edge & Rising Edge & how to implement with Quartus II.Now i want to implement both rising & falling edge detection at same time,can you help me out to do the same.



Thank you in advance for your time & consideration.

Is this something you will use in a test bench? There is no hardware
that corresponds to a dual edge detection, so such logic will not be
synthesizable.

--

Rick

 

[Johann Klammer]

On 01/28/2016 04:07 AM, rickman wrote:

Is this something you will use in a test bench? There is no hardware that corresponds to a dual edge detection, so such logic will not be synthesizable.

He could use 2 FFs and or the outputs

 

[rickman]

On 1/28/2016 8:51 AM, Johann Klammer wrote:

On 01/28/2016 04:07 AM, rickman wrote:

Is this something you will use in a test bench? There is no hardware that corresponds to a dual edge detection, so such logic will not be synthesizable.


He could use 2 FFs and or the outputs

That is not really "dual edge detection" in that it will produce two
signals that will need to be combined in some relevant manner. I'm not
sure any arbitrary logical function using two clock edges can be
reproduced with two separate FFs.

--

Rick

 

I have the same problem.Can you elaborate what did u do to include library??
PrimeTime couldn't linked the library file
I added following code for linking library
set search_path "/home/projects1/scl/stdlib/fs120/liberty/lib_flow_ss/ /home/users/mahesh/Desktop/synthesis/encoder/synth_try6/rtl/"
set link_path "* tsl18fs120_scl_ss.db"
output:
Loading db file '/home/projects1/scl/stdlib/fs120/liberty/lib_flow_ss/tsl18fs120_scl_ss.db'
Error: File is not a DB file. (DB-1)
Information: Errors reading file '/home/projects1/scl/stdlib/fs120/liberty/lib_flow_ss/tsl18fs120_scl_ss.db'. (DBR-002)
Error: Problem in read_db: No designs were read. (DBR-011)
Loading verilog file '/home/users/mahesh/Desktop/synthesis/encoder/synth_try6/rtl/op_data/encoder_synth.v'
Warning: Design 'encoder' (file '/home/users/mahesh/Desktop/synthesis/encoder/synth_try6/rtl/op_data/encoder_synth.v')
is already registered. Remove the design before rereading. (DBR-003)
Unlinking design encoder...
Warning: All timing information (backannotation, exceptions, etc.)
is being removed from design 'encoder'. User-created annotations
must be restored after relinking this design. (LNK-024)
Loading db file '/home/projects1/scl/stdlib/fs120/liberty/lib_flow_ss/tsl18fs120_scl_ss.db'
Error: File is not a DB file. (DB-1)
Error: Cannot read link_path file 'tsl18fs120_scl_ss.db'. (LNK-001)
Linking design encoder...
Warning: Unable to resolve reference to 'dfprb1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'dfcrq1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nr02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'inv0d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd12d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'inv0d2' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'mi02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd03d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd03d2' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'xn02d7' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'inv0d0' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd02d0' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nr02d0' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd02d2' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nd12d2' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'nr02d2' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'or02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'ora21d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'xn02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'mx02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'oai211d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'oai21d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'xr02d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'aoi31d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'aoim21d1' in 'encoder'. (LNK-005)
Warning: Unable to resolve reference to 'oaim22d1' in 'encoder'. (LNK-005)
Creating black box for U151/oai211d1...
Creating black box for U165/aoi31d1...
Creating black box for U166/oai211d1...
Creating black box for U170/oaim22d1...
Creating black box for U176/oai211d1...
Creating black box for R_0/dfprb1...
Creating black box for R_3/dfcrq1...
Creating black box for R_5/dfcrq1...
Creating black box for R_7/dfcrq1...
Creating black box for R_9/dfcrq1...
Creating black box for R_11/dfcrq1...
Creating black box for R_13/dfcrq1...
Creating black box for R_14/dfprb1...
Creating black box for R_16/dfprb1...
Creating black box for R_18/dfprb1...
Creating black box for R_20/dfcrq1...
Creating black box for R_23/dfprb1...
Creating black box for R_24/dfcrq1...
Creating black box for Dff2/Dout_reg/dfcrq1...

 

On Monday, September 30, 1996 at 12:00:00 AM UTC-7, Dmitri Fomine wrote:

Hello All,

Does anybody know an ASIC news group?

Thank You.

Dmitri Fomine

fomin@module.vympel.msk.ru

you mofoo

 

On Saturday, January 16, 2016 at 5:43:50 AM UTC-8, Aleksandar Kuktin wrote:

Have you noticed this post is almost 14 years old ?

It may be old, but this is a great 8b10b encoder / decoder. I use it all the time.

 

IP author can encrypt an IP as per IEEE Std 1735™-2014 (IEEE P1735 v2) standard with IP Encrypter tools. IP author can provide the level of protection through protect directives in common and tool blocks.

https://ipencrypter.com/wp-content/uploads/2016/11/ipe1735v2-1610-1-0-ug01.pdf

 

On Thursday, April 4, 2002 at 12:53:23 AM UTC+5:30, Edwin Grigorian wrote:

There's a minor bug with this code in that the LSB will never be granted
access.
To fix this, change i>0 in the conditional test of the FOR loop to i>=0..
-EG

"VhdlCohen" <vhdlcohen@aol.com> wrote in message
news:20020331210031.01801.00001394@mb-cg.aol.com...
I am very new to Verilog world. But i am eager to learn.
Can anybody refer me a verilog code for bus arbiter that i can use to
control CPU access and Ethernet controller access(which is using DMA) to
32-bit adress 32-bit data bus.
Your question is not really a verilog question because the first question
to
address is:
What are your requirements? There are several styles of bus arbiters,
fixed
priority, rotating priority, programmable priority, enables, etc...
Below is an example of a fixed priority, with MSB winning over lower order
bits.

module leadone (
// Outputs
ack,
// Inputs
req
);
parameter WIDTH = 8;
input [WIDTH-1:0] req; // bus request
output [WIDTH-1:0] ack; // bus acknowledge
reg [WIDTH-1:0] ack;
integer i; // loop index

always @ (req ) begin : priority
ack = {WIDTH{1'b0}};
for (i=WIDTH-1; i>0; i=i-1) begin
if (req) begin
ack = 1'b1;
disable priority;
end
end
end
endmodule

--------------------------------------------------------------------------
--
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
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sir i want to design a display using encoder in which i have to design a quiz buzzer ...in this once a person gets priority if two persons simulataneously hit the button..he will not get again and thus the other person gets priority...sir can you plzz tell me how to do it..i tried it using a flag in which i toggle it after each iteration...

 

[rickman]

yudhvirsingh1607@gmail.com wrote on 6/20/2017 9:49 AM:

On Thursday, April 4, 2002 at 12:53:23 AM UTC+5:30, Edwin Grigorian wrote:

sir i want to design a display using encoder in which i have to design a quiz buzzer ...in this once a person gets priority if two persons simulataneously hit the button..he will not get again and thus the other person gets priority...sir can you plzz tell me how to do it..i tried it using a flag in which i toggle it after each iteration...

You are replying to a 15 year old post.

What you describe is exactly how I would do it. The state of the flag
indicates which user gets priority. The point that is not entirely clear to
me is how the flag is changed. Is it only changed when the two buttons are
pressed simultaneously? Or every time the button is pressed?

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Rick C