need a cheap student edition FPGA

Michael A. Terrell wrote:

barbara@bookpro.com wrote:

And some keep following shiny things back and forth through Usenet's
murky waters.
Click to expand...
Won't someone please think of the SHINY HAPPY PEOPUMS?

Really? Then you should climb back on the short bus, and go back to
the nut hatch. Your doctors have some shiny new toys for you to play
with, wile they test more experimental drugs. They say you're the
perfect Guinea Pig, other than the fact you shed more than the real
thing. :).
Click to expand...
Mmmmm Kibo Ultra!
 
"Marvin J. Mooney" <ms99cc77@newsfroup.net> wrote

And some keep following shiny things back and forth through Usenet's
murky waters.

Won't someone please think of the SHINY HAPPY PEOPUMS?
Click to expand...
Whiney sappy peopums holding hams.

--oTTo--
 
On Mon, 10 May 2010 19:57:31 +0100, Adam Funk <a24061@yahoo.com> wrote:

On 2010-05-10, krw@att.bizzzzzzzzzzzz wrote:

Speaking of pots...

Aren't they usually called variable resistors these days?
Click to expand...
No.
 
On Mon, 10 May 2010 17:15:11 -0500, "krw@att.bizzzzzzzzzzzz"
<krw@att.bizzzzzzzzzzzz> wrote:

On Mon, 10 May 2010 19:57:31 +0100, Adam Funk <a24061@yahoo.com> wrote:

On 2010-05-10, krw@att.bizzzzzzzzzzzz wrote:

Speaking of pots...

Aren't they usually called variable resistors these days?

No.
Click to expand...
Woosh...

--
************* DAVE HATUNEN (hatunen@cox.net) *************
* Tucson Arizona, out where the cacti grow *
* My typos & mispellings are intentional copyright traps *
 
On Mon, 10 May 2010 18:25:55 -0700, Hatunen <hatunen@cox.net> wrote:

On Mon, 10 May 2010 17:15:11 -0500, "krw@att.bizzzzzzzzzzzz"
krw@att.bizzzzzzzzzzzz> wrote:

On Mon, 10 May 2010 19:57:31 +0100, Adam Funk <a24061@yahoo.com> wrote:

On 2010-05-10, krw@att.bizzzzzzzzzzzz wrote:

Speaking of pots...

Aren't they usually called variable resistors these days?

No.

Woosh...
Click to expand...
Idiot
 
Otto Bahn <Ladybrrane@GroinToHell.com> wrote:
"Adam Funk" <a24061@yahoo.com> wrote
Speaking of pots...

Aren't they usually called variable resistors these days?

Potentially.
Click to expand...
"Hello, $WORKER speaking. This is a flip-flop!"

Dave "...read me, Doctor Memory?" DeLaney
--
\/David DeLaney posting from dbd@vic.com "It's not the pot that grows the flower
It's not the clock that slows the hour The definition's plain for anyone to see
Love is all it takes to make a family" - R&P. VISUALIZE HAPPYNET VRbeable<BLINK>
http://www.vic.com/~dbd/ - net.legends FAQ & Magic / I WUV you in all CAPS! --K.
 
Otto Bahn wrote:
"Hatunen" <hatunen@cox.net> wrote

The subject at issue is the previous statement:
[deleted by Otto so no one will know what he's talking about]

It was already deleted by someone else.

Yeah, Bush II served in the military, so maybe his blanket statement
about people who served is a tad off.
There questions about just how much serving Bush did while in the
military...

Deletion of Bush I and JFK noted. General statement about those
who served has been trashed.
Click to expand...
They also serve who only wait at table.

--
Peter Moylan, Newcastle, NSW, Australia. http://www.pmoylan.org
For an e-mail address, see my web page.
 
I would guess a majority of the people reading this group do FPGA work so they can afford to be sloppy in their code and just redo it if they make a size mistake that causes an error. However, if you're doing huge ASICs that cost over $1million for NRE and to re-spin if you make a mistake, you sure as hell better be sizing your constants and running every compile and lint checker you can think of!

David
 
On Wednesday, February 16, 2011 6:12:51 PM UTC-5, Andy wrote:
On Feb 5, 2:59 pm, gabor <ga...@alacron.com> wrote:
One thing I don't miss is strong typing.  It seems
draconian that you need to write a constant for
a 5-bit quantity in binary, or use a type conversion.
I almost never size constants in Verilog.  I understand
that some people do it to remind themselves of the
actual number of bits being used in the context,
but I just find the code more readable without
all the 3'd7 notation, instead of just plain 7.

Good luck on your new ventures,
Gabor- Hide quoted text -

- Show quoted text -

I'm sure whoever gets to maintain your code will appreciate all the
unlabeled, unexplained, unbounded literals for which you saved so much
time and effort by not bothering to define constants.

Defining a constant with a useful name gives the value a purpose and a
reason why it is what it is. Giving the constant a type gives the
value a context in which it may be interpreted. Giving the constant a
constrained type gives the value a range within which it might be
changed should the need arise.

Yes, you could accomplish all that with equally verbose comments that
are ignored by anything but human readers, if only they could trust
that the comments had been kept up to date.

If developers thought more about maintaining their code than typing
it, they'd spend far less time chasing their tails when it does not
work than they'd spent on a few extra keystrokes.

Andy
Click to expand...
The point I was making has nothing to do with comments
and everything to do with human readability of the code
itself. I have had to do a lot of maintenance of
strongly typed VHDL code with few or no comments in it,
and constants like "01011" are NOT in my opinion helpful
in showing the intent of the variable to which it is
assigned or compared. My code is liberally littered
with comments, as much for my own use when I need to
make updates in the future as for anyone else who might
need to understand it. The exact number of bits in
a signal or variable is always readily available in
the declaration, and I don't need to be reminded of
it each time it appears in the behavioral code.

Just my 2 cents,
Gabor
 
Yes, it is easy to write bad (unmaintainable) code in both vhdl and
verilog.

The point I was trying to make is that just using 7 or 3'd7 is just as
bad as "111" in far too many cases.

Why is it 7 instead of 5? What is significant about 7? Or is it just
"all bits are set"? Is it a maximum value, a minimum value, an initial
value, "everything is on", "everything is off", or what? Does/should
the value track something else? A constant's declaration can tell the
reader all of that with code that gets verified by the tool every time
it is run.

I actually agree with your comment about being reminded of the exact
number of bits every time it appears. The code should be written such
that if the exact number of bits needs to change, it should require as
few manual changes to as few places in the code as practical. In that
regard, 7 may be preferable to 3'd7, but not to a well-defined
constant.

Andy
 
Almost any embedded numerical constants are a sign of bad code. As you wrote, it doesn't tell you what it means. They should almost always - except in extremely trivial cases - be predefined (e.g. header file) constants using macros, parameters, enums, etc.
 
On Donnerstag, 17. Februar 2011 04:08, unfrostedpoptart wrote:

I would guess a majority of the people reading this group do FPGA work so
they can afford to be sloppy in their code and just redo it if they make a
size mistake that causes an error. However, if you're doing huge ASICs
that cost over $1million for NRE and to re-spin if you make a mistake, you
sure as hell better be sizing your constants and running every compile and
lint checker you can think of!
Click to expand...
You are putting a straw man up. I've done >$1M ASICs, and of course one of
the actions you should take is to implement a prototype in an FPGA, which
allows to exercise your design much better than simulation. Certainly, you
*also* should do simulations to test your design under artificial, but
controlled border conditions. And finally, using other tools to gather
informations for you can't be wrong.

The impression you are generating however is that compile+lint do 90% of the
work to achieve a good design. Never. Closer to 1%, I'd say. "If it
compiles, it's good" is a typical VHDL attitude, and can't be further from
the truth. It's probably a psychological problem: "because it was hard to
compile, it now must be good", but that's false reasoning. Writing VHDL
properly is just so much harder than writing proper Verilog.

--
Bernd Paysan
"If you want it done right, you have to do it yourself!"
http://www.jwdt.com/~paysan/
 
On Tuesday, February 22, 2011 5:10:59 AM UTC-8, Bernd Paysan wrote:
On Donnerstag, 17. Februar 2011 04:08, unfrostedpoptart wrote:

I would guess a majority of the people reading this group do FPGA work so
they can afford to be sloppy in their code and just redo it if they make a
size mistake that causes an error. However, if you're doing huge ASICs
that cost over $1million for NRE and to re-spin if you make a mistake, you
sure as hell better be sizing your constants and running every compile and
lint checker you can think of!

The impression you are generating however is that compile+lint do 90% of the
work to achieve a good design.
Click to expand...
Not at all. I'm just saying one important part of having a good design database is that it's syntactically clean. I didn't give any percentages of how important this is versus other testing, but even if it's only 1%, that's still a big deal in the face of NRE/re-spin costs and time-to-market.

David
 
On Friday, March 18, 2011 1:19:12 AM UTC-4, aldorus wrote:
Thanks guys. I have to go re-read the section on wire/net and reg/int.
This assignment rules have me confused
Click to expand...
I find that having a simplified view of Verilog as a
simulation language helps me understand the rules a
bit better. If you think like a simulator, then a
reg or integer implies that the simulator needs storage
to compute the current value. A wire does not need
storage because it is continuously assigned or
connected to some other value for which the simulator
already has storage. This has nothing to do with the
type of procedural block within which the reg or integer
is assigned. For example a "reg" does not necessarily
imply storage in the actual hardware. If you were to
translate the Verilog procedure to a C program, however
the "reg" would require a variable.

Hope that isn't more confusing than helpful.

-- Gabor
 
Hi,

I want to found my image file width and height of pixels . please let me know if any sample source available links.
 
> I want to found my image file width and height of pixels . please let me know if any sample source available links.

Hi,

please stop spamming the forum with your homework/job task help requests.

If you really want to work with image formats, I suggest you learn about PBM, PGM, PPM which are essentially plain data. I have extended Martin J. Thompsons PGM package for PBM and PPM images (thanks MJT for the great package). I suggest you work your way through your problem doing something similar..
 
Hi Hemi Thaker,

Thanks for a nice work. Could you please send me the tared version of verilog-preprocessor. It would be very helpfull to me.

Thanks & Regards
Anil
 
On 12/13/2013 6:24 AM, anilk.gajjala@gmail.com wrote:
Hi Hemi Thaker,

Thanks for a nice work. Could you please send me the tared version of verilog-preprocessor. It would be very helpfull to me.

Thanks & Regards
Anil
Click to expand...

This must be some kind of record - responding to a 17-year-old thread
about adding features to Verilog, many of which have since been
incorporated into the language.

--
Gabor
 
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