need a cheap student edition FPGA

<parag_paul@hotmail.com> wrote in message
news:4926bb48-067b-48d7-a82e-5f58c607c2d3@h17g2000prg.googlegroups.com...
or we just follow this one
Click to expand...
I checked the newsgroups available on the three newsgroups servers
I use, and the only other newsgroup with verilog in the name on any
of them is fj.comp.lang.verilog . I'm unable to find anything at all
posted to it, though, and the first part of its name suggests that it uses
a language other than English.

So if there's any other group, it's unlikely to be a newsgroup.

I often see System Verilog mentioned in the comp.lang.verilog
newsgroup, though.
 
"Marwan" <marwanboustany@gmail.com> wrote in message
news:a43d48c2-d518-4533-83d6-69f4c96228dd@79g2000hsk.googlegroups.com...
Peace,

Consider: -

The following represents the kind of code I am dealing with.

Task A:
(Clocked) Iterative structure (value of iteration)
begin
c <= a*b;
d <= b*f;
g <= c/a;
k <= g+d;
end

(Ignore the sizes of the following variables and any fixed point
arithmetic considerations, they are straight forward to deal with and
besides the point for my question.)

In the particular case of Task A, see if you can apply the following
Click to expand...
optimization:

g <= c/a;

g <= a*b/a;

g <= b;

Won't work in all similar tasks, though.
 
<d_s_klein@yahoo.com> wrote in message
news:76d3ffb1-8b2f-4daa-abc3-921097c66838@s1g2000pra.googlegroups.com...
spam
Click to expand...
Most of us know it's spam and don't need to be told. If you
want to tell someone what's spam, you might try the abuse
department of the sender's ISP.

http://www.whatsmyip.org/spam/

http://www.whatsmyip.org/whois/

http://spamcop.net/fom-serve/cache/19.html

http://www.spamcop.net/

http://headertool.apelord.com/

http://www.google.com/contact/spamreport.html

http://getpopfile.org/

http://www.keir.net/k9.html

http://help.yahoo.com/tutorials/mail/mail/spamguard1.html

http://www.geobytes.com/IpLocator.htm?GetLocation
 
<d_s_klein@yahoo.com> wrote in message
news:beaa7e98-3cfb-47ab-8763-95b36abcf190@s1g2000pra.googlegroups.com...
The useful action is to change the subject to 'spam' so that it's
trivially easy to filter out the messages.

The OP is a GoogleGroups user. Complaining to Google about their
users spamming usenet is much like trying to drain the ocean with a
teaspoon.

Cheers!
Click to expand...
I've found that If you complain to groups-abuse@google.com about
various messages from the same spammer for about 6 weeks, they
usually finally decide to do something about it. Unfortunately, usually
not enough.
 
"kb33" <kanchan.devarakonda@gmail.com> wrote in message
news:148cf446-25ee-40e1-996c-a25671a4dab1@j22g2000hsf.googlegroups.com...
Hi,

I have been always been taught so and try to strictly follow the
practice of splitting my design into combinational and sequential
blocks (see example below). However, I have been asked to look at
somebody's design at my workplace that does not do so, and I do not
know whether I should ignore his style or bring it to the notice of
the manager. I am looking for the most convincing explanation as to
why the second style is not good.

----------My style----------------------

Sequential
---------------

always @(posedge clock)
data_out <= data_out_comb;

Combinational
---------------------

always @(reset_n or data_a or data_b)
if (~reset_n)
data_out_comb = 0;
else
data_out_comb = data_a + data_b;




-------Mixed sequential and combinational design----------------

always @ (posedge clock or negedge reset_n)
begin
if(~reset_n)
data_out <= 0;
else
data_out <= data_a + data_b;
end



P.S The second coding style doesn't even have the signals data_a and
data_b in the sensitivity list.


Thanks
kb33
Click to expand...
There is nothing wrong with either style. They both synthesize, simulate and
read. It is style and there are many different syles that people have. It's
personal preference.

Mike
 
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote in
news:i45vb4d1nn8sh5vimv03cg442pn7m18sje@4ax.com:

On Wed, 3 Sep 2008 08:23:13 -0700 (PDT), laserbeak43 wrote:

Alternatively, use the FPGA’s Digital Clock Manager
(DCM) to generate or synthesize other frequencies
from the on-board 50 MHz oscillator.

And then you will find that 50MHz*3/7 is rather close
to 21.48MHz - only about a quarter of a percent error.
Good enough? I couldn't find any other accessible
M/N values that were closer.
Click to expand...
The exact ratio is 537 / 1250, which can't be done using a DCM.
Nor can it be done with a conventional phase accumulator type
fractional-N divider.

It's simple enough to do with an FSM though.

Regards,
Allan
 
John_H <newsgroup@johnhandwork.com> wrote in news:b61ffd76-b12a-4a87-
984f-9e14d7033e59@r35g2000prm.googlegroups.com:

On Sep 4, 8:14 am, Allan Herriman <allanherri...@hotmail.com> wrote:

The exact ratio is 537 / 1250, which can't be done using a DCM.
Nor can it be done with a conventional phase accumulator type
fractional-N divider.

It's simple enough to do with an FSM though.

Regards,
Allan

A fractional N PLL can do this fine. An integer-N PLL can do this
fine with a 40kHz phase comparator frequency. No FSM will eliminate
the jitter. A DDS is better than an FSM given the number of states
involved.

You leave me very confused as to what your intent was with your
comments beyond the DCM.

If by "conventional phase accumulator type fractional-N divider" you
mean DDS, even that can provide an "exact" frequency using a non-2^n
modulus if the sub-ppb inaccuracy of a 32-bit DDS isn't sufficient.
Click to expand...
"[C]onventional phase accumulator type fractional-N divider" have a
2^n modulus. I was merely pointing out that the exact frequency ratio
can't be achieved with a 2^n modulus.

BTW, a DDS is an FSM (but not all FSMs are DDSs), so I'm not sure about
your statement that a DDS can be better than an FSM.

Several years ago I wrote a fractional-N divider generator program. It's
still on the web:
http://fractional-divider.tripod.com/
It still works, too. The resultant code is not a DDS, but it does
produce an identical output.

However, I now use a more compact implementation (written directly in
HDL) for those rare cases when I need a fractional-N divider in a design.

Regards,
Allan
 
gtalk.nikhil@gmail.com wrote:
On Sep 12, 1:59 am, Andy <jonesa...@comcast.net> wrote:
On Sep 11, 2:14 pm, nikhil_...@yahoo.co.in wrote:
If i am implementing a gray counter and first i increment a binary
count and then convert it to gray count will there be any glitch??

It is really hard to get rid of glitches with combinatorial logic. If
you have a register after the conversion, clocked by the same clock
used for the binary counter, then you will not have glitches
(assuming timing constraints are met), but your gray code will be
one clock behind the binary code.

Andy

Then generally how do we do it if we have to get rid of glitches and
also meet the timing??
Click to expand...
Build a Gray counter instead of a binary one. If you need a binary value,
convert Gray->binary instead of the other way round.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.
 
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:ga3p9j$puv2@cnn.xsj.xilinx.com...
designer wrote:
Hi all,
I have a define like
#define N_THREADS 4
I want to have another define depending on N_THREADS which should be
log (N_THREADS) to the base 2.
In the above example it becomes 2.Is there any such way...
Thanks,
Vittal
You can sort of do this with defines, but it's messy and much better to do
it with parameters and constant functions, which most tools support now.
As in:

parameter N_THREADS=4;
parameter log2_N_THREADS=clog2(N_THREADS);

...

function clog2(...
Click to expand...
Systemverilog-2008 will add a standard system-task $clog2(), which returns
log2() of its argument.
Unfortunately, no tools today support it yet. And you can bet industrywide
support is
years away...

function integer clog2;
input integer argument;
...
endfunction
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
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