need a cheap student edition FPGA

"Alex" <enginven@gmail.com> wrote in message
news:05bd2c8f-8660-49f3-8140-16baa048898f@n1g2000prb.googlegroups.com...
On May 18, 1:29 pm, Ben Bradley <ben_nospam_brad...@frontiernet.net
wrote:
In the newsgroups comp.arch.fpga, comp.lang.verilog,
comp.arch.embedded, sci.electronics.design and comp.lang.vhdl, I saw a
thread in which the following words were approximately attributed to
the following posters:

On Wed, 7 May 2008 17:19:31 -0700, "BobW"



nimby_NEEDS...@roadrunner.com> wrote:

"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in
message
news:eek:1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com...
On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H
newsgr...@johnhandwork.com> wrote:

John Larkin wrote:

To Lattice:

We dumped Lattice over buggy compilers and dinky performance. Now
that
you're spamming our group, I'll make the ban permanent.

To the group:
Whenever anybody spams us, please

1. Blackball them as a vendor

2. Say bad things about their companies and products, preferably
with
lots of google-searchable keywords.

John

Was this really necessary?

Yes.

If there were technical webcasts from any of the big vendors, I'd like
to know about them though preferably more than 8 minutes beforehand.

Email them, and sign up for subscriptions to all their blurbs. A
confirmed opt-in email list is a good way to disseminate such info. If
they don't have such a list or don't announce events timely, tell them
you'll only consider sources from companies who do.

If the posts of this nature got to be more than a couple a month from
any one source I'd agree with the spam catagorization but it isn't
that frequent.

"Well, there's spam egg Lattice and spam, that's not got much spam
in it."

In other words, "they're not breaking the rules THAT often." With
the thousands of suppliers that provide products and services relevant
to even one of the cross-posted newsgroups, there could be hundreds of
posts per day of "legitimate" commercial posts.

I'm disappointed that you had problems with them in the past and won't
trust them for future designs because of your history; competition is
almost always good. But is it reason to be publicly vocal?

It's always good to be vocal about inappropriate posts. As for the
poster airing his previous problems with Lattice, perhaps they would
be better put in a blog or in a post where someone asks about using
Lattice, but that's a minor thing compared to the original post.

Kill-lists are easy to manage if bart's messages offend you.

I have better things to do than manage kill lists. I've got "better
things to do" than write this, but but c.a.e and especially s.e.d have
been useful to me a while back, and between all the spam and splorge
in recent years, it's a pleasant surprise to see these groups are
still viable. So I'm doing my little part to help keep them alive.





- John_H

If we don't discourage commercial posts, newsgroups will be flooded
with them. I can't kill-file the tens of thousands of companies who
would spam newsgroups if they thought it would pay off. So let's make
sure it *doesn't* pay off.

If they want to advertise, let them pay for it somewhere else.

John

For what it's worth, I agree with John.

It's a real shame that we, now, have to go out of our way to filter
commercial and sexual posts. There are proper places for both of those.
Usenet is not one of them, in my opinion.

Just to make a slight correction, THESE NEWSGROUPS (see crosspost
list at the top of my post) are not the proper place for commercial
posts. There are "marketplace" and "sex" newsgroups - if he's going to
spam, perhaps Bart Borosky of Lattice would do well to post to those
instead. There's no telling where a lonely engineer might go in his
spare time, and after all, "posting to Usenet is free" (as in both
beer AND speech).

Post, drink and speak responsibly.



Bob

Guys,

I read this thread after it was created and just wanted to ask a
couple of questions (while completely agreeing with the generally
accepted conclusion):
Was all this 'hot air' necessary?
Was all this bad-mouthing coming from some of the authors proper for
the group?

With respect,
Click to expand...
Which group? It was crossposted to 5 different newsgroups, and is
unwelcome in at least one of them.
 
"faz" <fazulu.vlsi@gmail.com> wrote in message
news:d4318538-a472-495e-b7df-09d3fa7c89f4@d19g2000prm.googlegroups.com...
On May 21, 5:18 am, "bigcaterpil...@gmail.com"
bigcaterpil...@gmail.com> wrote:
I give your a suggestion that you can read a book called "verilog HDL
synthesis A Parctical Primer" written J.Bhasker
I think synthesis is so important for logic design.

flypig

hai,

it is always advised that FOR loops are not to be
used in RTL coding

for example:

for(int i=2; i>=0; i--) {
c+ = a*b[i+1];
};

In this case it is probably a much better idea to write a small
state
machine
for example:
case (state)
first:
begin
c+ = a[2]*b[3];
c+ = a[1]*b[2];
c+ = a[0]*b[1];
state=output;
end
.......

I would like to know the difference between number of clock
cycles,adders and multipliers required when "for" loop is used and
"state machine" is used??

Wat is the advantage i get interms of number of clocks,resources if i
have more number of states the above example is divided as 3 states
instead of 1 as follows.??

case (state)
first:
begin
c+ = a[2]*b[3];
state=second;
end
second:
begin
c+ = a[1]*b[2];
state=third;
end
third:
begin
c+ = a[0]*b[1];
state=output;
end

regards.
faz
Click to expand...

You really do need to read a good book on basic digital circuit design,
because I think you are very confused. In particular, you seem to be
confusing the concept of a state machine with a case statement!

A state machine is a mechanism that allows a circuit to exist in any one of
a number of different states, the state potentially changing on each clock
cycle. A classic example often used for teaching is that is a traffic light
controller in which the states correspond to the possible light colors.
Inputs to the state machine, along with the current state, determine what
the next state is. The outputs are determined either entirely by the current
state, or by a combination of the current state and the inputs.

As regards the use of FOR loops in synthesis, there is nothing wrong with
them as long as you understand what they are doing. They are merely a
shorthand form of writing out a set of related statements. Your example
above will therefore create three entirely separate multipliers.

The reason people are suggesting using a state machine is that you may not
want indivdiual multipliers that can produce indepedent results
continuously. Instead, you may only need to generate all the results within
a certain time, in which case a single multiplier can be used sequentially
to generate the results which are then stored. Because this involves
different actions over time, state is needed to control this.
 
"faz" <fazulu.vlsi@gmail.com> wrote in message
news:d4318538-a472-495e-b7df-09d3fa7c89f4@d19g2000prm.googlegroups.com...
On May 21, 5:18 am, "bigcaterpil...@gmail.com"
bigcaterpil...@gmail.com> wrote:
I give your a suggestion that you can read a book called "verilog HDL
synthesis A Parctical Primer" written J.Bhasker
I think synthesis is so important for logic design.

flypig

hai,

it is always advised that FOR loops are not to be
used in RTL coding

for example:

for(int i=2; i>=0; i--) {
c+ = a*b[i+1];
};

In this case it is probably a much better idea to write a small
state
machine
for example:
case (state)
first:
begin
c+ = a[2]*b[3];
c+ = a[1]*b[2];
c+ = a[0]*b[1];
state=output;
end
.......

I would like to know the difference between number of clock
cycles,adders and multipliers required when "for" loop is used and
"state machine" is used??

Wat is the advantage i get interms of number of clocks,resources if i
have more number of states the above example is divided as 3 states
instead of 1 as follows.??

case (state)
first:
begin
c+ = a[2]*b[3];
state=second;
end
second:
begin
c+ = a[1]*b[2];
state=third;
end
third:
begin
c+ = a[0]*b[1];
state=output;
end

regards.
faz
Click to expand...

You really do need to read a good book on basic digital circuit design,
because I think you are very confused. In particular, you seem to be
confusing the concept of a state machine with a case statement!

A state machine is a mechanism that allows a circuit to exist in any one of
a number of different states, the state potentially changing on each clock
cycle. A classic example often used for teaching is that is a traffic light
controller in which the states correspond to the possible light colors.
Inputs to the state machine, along with the current state, determine what
the next state is. The outputs are determined either entirely by the current
state, or by a combination of the current state and the inputs.

As regards the use of FOR loops in synthesis, there is nothing wrong with
them as long as you understand what they are doing. They are merely a
shorthand form of writing out a set of related statements. Your example
above will therefore create three entirely separate multipliers.

The reason people are suggesting using a state machine is that you may not
want indivdiual multipliers that can produce indepedent results
continuously. Instead, you may only need to generate all the results within
a certain time, in which case a single multiplier can be used sequentially
to generate the results which are then stored. Because this involves
different actions over time, state is needed to control this.
 
"FP" <FPGA.unknown@gmail.com> wrote in message
news:cbbceb8f-1f94-4a4c-a5ad-cb6a64789fa4@k13g2000hse.googlegroups.com...
I have an input pulse which can be high for more than one clock cycle.

I want to stay in wait state after i detect the posedge and switch to
armed state after i detect the negative edge. How do I do this in
verilog? I dont want to use wait statements as they are not
synthesizable. I am using an FSM to do this. I have tried using if
statements but it wont work.

Thanks in advance

If you have a state-machine based solution that works then why change it?
Click to expand...
There are a couple of points you should consider though:
1. If the input is not synchronous to the state machine clock then you must
synchronize it otherwise all hell will break lose.
2. What happens if your input pulse is less than one clock cycle wide (which
your comment seems to imply it could be)?

One way to handle the second caveat is to have two flip-flops clocked by the
input itself, one on the rising edge and one on the falling edge. Tie the D
inputs high and control the asynchronous resets from your state machine.
Remember to synchronize the outputs of these flip-flops instead of the input
signal though.
 
"FP" <FPGA.unknown@gmail.com> wrote in message
news:cbbceb8f-1f94-4a4c-a5ad-cb6a64789fa4@k13g2000hse.googlegroups.com...
I have an input pulse which can be high for more than one clock cycle.

I want to stay in wait state after i detect the posedge and switch to
armed state after i detect the negative edge. How do I do this in
verilog? I dont want to use wait statements as they are not
synthesizable. I am using an FSM to do this. I have tried using if
statements but it wont work.

Thanks in advance

If you have a state-machine based solution that works then why change it?
Click to expand...
There are a couple of points you should consider though:
1. If the input is not synchronous to the state machine clock then you must
synchronize it otherwise all hell will break lose.
2. What happens if your input pulse is less than one clock cycle wide (which
your comment seems to imply it could be)?

One way to handle the second caveat is to have two flip-flops clocked by the
input itself, one on the rising edge and one on the falling edge. Tie the D
inputs high and control the asynchronous resets from your state machine.
Remember to synchronize the outputs of these flip-flops instead of the input
signal though.
 
"lei" <leisun124@gmail.com> wrote in message
news:c7a85d99-81f4-4438-8466-bdfe65522784@z24g2000prf.googlegroups.com...
On May 26, 2:43 am, tersono <ethel.thef...@ntlworld.com> wrote:
On Sun, 25 May 2008 22:43:49 -0700 (PDT), lei <leisun...@gmail.com
wrote:
snip



always @(posedge clk_in)
begin
clk_acc = clk_acc[19:0] + CLK_ACC_INC;
clk_out = clk_acc[20];
end
endmodule

The code passed synthesis step,

It seeems to be an attempt to get 60Hz clock from 50MHz input; the
CLK_ACC_INC is calculated to get such a result.

I suspect you didn't look at the warnings.

They tell you that data_in isn't used, and that clk_acc[20] isn't
assigned.

clk_acc = clk_acc[19:0] + CLK_ACC_INC;

increments clk_acc[19:0], but leaves clk_acc[20] unchanged.

A 20-wide accumulator is actually

reg [19:0] clk_acc;

CLK_ACC_INC_WIDTH is specified as 20, and yet the number "20" is used
instead of this parameter in the code. Why not use the parameter
rather than the number?

The following works:

####################

module led(clk_in, clk_out);
input clk_in;
output clk_out;

reg clk_out;

parameter INPUT_CLK = 50000000; //input clock is 50MHz
parameter OUTPUT_CLK = 60; //60Hz to refresh
the LED.
parameter CLK_ACC_INC_WIDTH = 24; //Use 24 bit accumulator.
parameter CLK_ACC_INC = (OUTPUT_CLK << CLK_ACC_INC_WIDTH) /
INPUT_CLK;

reg [CLK_ACC_INC_WIDTH-1:0] clk_acc;

initial
begin
clk_acc = 0;
clk_out = 0;
end

always @(posedge clk_in)
begin
clk_acc = clk_acc[CLK_ACC_INC_WIDTH-1:0] +
CLK_ACC_INC;
clk_out = clk_acc[CLK_ACC_INC_WIDTH-1];
end

endmodule
#############

Note that I've changed CLK_ACC_INC_WIDTH to 24. If you leave it at 20,
CLK_ACC_INC is 1.258. It gets truncated to 1, and clk_acc just counts
up. CLK_ACC_INC_WIDTH = 24 gives CLK_ACC_INC=20.132, truncated to 20,
and so the accumulator overflows (irregularly) at a 60Hz rate. A
longer accumulator would give a less irregular output.

As Guenter says, do think about how long you'll have to run the sim to
see output changes.
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.

Hi tersono:
Thank you very much for your inputs! It's right that using 24 bit
accumulator, I should get 60hz from 50mhz input clock. However, my
simulation still fail, basically, the input clock is "Z", I guess it
would be hard to tell what the problem is, I've uploaded my project
(about 379K zipped file) into:
http://www.MegaShare.com/418855
I am starting to wonder if my ISE got problem or not. I appreciate
if anyone can download the project and run a sim. see if it behave
differently on your machine.
Thank you!

Regards
lei
Click to expand...
If your input clk is "z" .. would not the solution be to add a stimulus to
your testbench to get that to "wiggle"? Usually not much happens in a
synchronous design if there is no clock.

Mike
 
"lei" <leisun124@gmail.com> wrote in message
news:c7a85d99-81f4-4438-8466-bdfe65522784@z24g2000prf.googlegroups.com...
On May 26, 2:43 am, tersono <ethel.thef...@ntlworld.com> wrote:
On Sun, 25 May 2008 22:43:49 -0700 (PDT), lei <leisun...@gmail.com
wrote:
snip



always @(posedge clk_in)
begin
clk_acc = clk_acc[19:0] + CLK_ACC_INC;
clk_out = clk_acc[20];
end
endmodule

The code passed synthesis step,

It seeems to be an attempt to get 60Hz clock from 50MHz input; the
CLK_ACC_INC is calculated to get such a result.

I suspect you didn't look at the warnings.

They tell you that data_in isn't used, and that clk_acc[20] isn't
assigned.

clk_acc = clk_acc[19:0] + CLK_ACC_INC;

increments clk_acc[19:0], but leaves clk_acc[20] unchanged.

A 20-wide accumulator is actually

reg [19:0] clk_acc;

CLK_ACC_INC_WIDTH is specified as 20, and yet the number "20" is used
instead of this parameter in the code. Why not use the parameter
rather than the number?

The following works:

####################

module led(clk_in, clk_out);
input clk_in;
output clk_out;

reg clk_out;

parameter INPUT_CLK = 50000000; //input clock is 50MHz
parameter OUTPUT_CLK = 60; //60Hz to refresh
the LED.
parameter CLK_ACC_INC_WIDTH = 24; //Use 24 bit accumulator.
parameter CLK_ACC_INC = (OUTPUT_CLK << CLK_ACC_INC_WIDTH) /
INPUT_CLK;

reg [CLK_ACC_INC_WIDTH-1:0] clk_acc;

initial
begin
clk_acc = 0;
clk_out = 0;
end

always @(posedge clk_in)
begin
clk_acc = clk_acc[CLK_ACC_INC_WIDTH-1:0] +
CLK_ACC_INC;
clk_out = clk_acc[CLK_ACC_INC_WIDTH-1];
end

endmodule
#############

Note that I've changed CLK_ACC_INC_WIDTH to 24. If you leave it at 20,
CLK_ACC_INC is 1.258. It gets truncated to 1, and clk_acc just counts
up. CLK_ACC_INC_WIDTH = 24 gives CLK_ACC_INC=20.132, truncated to 20,
and so the accumulator overflows (irregularly) at a 60Hz rate. A
longer accumulator would give a less irregular output.

As Guenter says, do think about how long you'll have to run the sim to
see output changes.
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.

Hi tersono:
Thank you very much for your inputs! It's right that using 24 bit
accumulator, I should get 60hz from 50mhz input clock. However, my
simulation still fail, basically, the input clock is "Z", I guess it
would be hard to tell what the problem is, I've uploaded my project
(about 379K zipped file) into:
http://www.MegaShare.com/418855
I am starting to wonder if my ISE got problem or not. I appreciate
if anyone can download the project and run a sim. see if it behave
differently on your machine.
Thank you!

Regards
lei
Click to expand...
If your input clk is "z" .. would not the solution be to add a stimulus to
your testbench to get that to "wiggle"? Usually not much happens in a
synchronous design if there is no clock.

Mike
 
"rickman" <gnuarm@gmail.com> wrote in message
news:3253a340-9804-4fd5-b6d8-df9dd706ae86@c58g2000hsc.googlegroups.com...
[snip]
Independant of the UI issues, a program really shouldn't crash when it
reads a data file... of any nature. Of course that is a theoretical
goal and can be difficult to achieve in practice. But certainly
crashing on startup without visible error messages is not a good thing
either. I had to start it from a DOS box to get anything useful from
it... maybe that is more of a Java issue... and don't get me started
complaining about Java. Does *anything* written in Java actually
work?

I suggest that any program for Windows Vista that uses Java should
Click to expand...
start with a check to see if Java is even installed, and if so, whether
the version installed is suitable for what the program needs. My version
of Vista came without Java, and the Microsoft version is no longer
available. I installed the Sun version, but still have problems with
getting
all the programs that use Java to run correctly.

http://www.java.com/en/
 
"rickman" <gnuarm@gmail.com> wrote in message
news:3253a340-9804-4fd5-b6d8-df9dd706ae86@c58g2000hsc.googlegroups.com...
[snip]
Independant of the UI issues, a program really shouldn't crash when it
reads a data file... of any nature. Of course that is a theoretical
goal and can be difficult to achieve in practice. But certainly
crashing on startup without visible error messages is not a good thing
either. I had to start it from a DOS box to get anything useful from
it... maybe that is more of a Java issue... and don't get me started
complaining about Java. Does *anything* written in Java actually
work?

I suggest that any program for Windows Vista that uses Java should
Click to expand...
start with a check to see if Java is even installed, and if so, whether
the version installed is suitable for what the program needs. My version
of Vista came without Java, and the Microsoft version is no longer
available. I installed the Sun version, but still have problems with
getting
all the programs that use Java to run correctly.

http://www.java.com/en/
 
"Robert Miles" <robertmiles@bellsouthNOSPAM.net> wrote in message
news:_tU1k.736$RY.138@bignews8.bellsouth.net...
"rickman" <gnuarm@gmail.com> wrote in message
news:3253a340-9804-4fd5-b6d8-df9dd706ae86@c58g2000hsc.googlegroups.com...
[snip]
Independant of the UI issues, a program really shouldn't crash when it
reads a data file... of any nature. Of course that is a theoretical
goal and can be difficult to achieve in practice. But certainly
crashing on startup without visible error messages is not a good thing
either. I had to start it from a DOS box to get anything useful from
it... maybe that is more of a Java issue... and don't get me started
complaining about Java. Does *anything* written in Java actually
work?

I suggest that any program for Windows Vista that uses Java should
start with a check to see if Java is even installed, and if so, whether
the version installed is suitable for what the program needs. My version
of Vista came without Java, and the Microsoft version is no longer
available. I installed the Sun version, but still have problems with
getting
all the programs that use Java to run correctly.

http://www.java.com/en/

When getting the URL for that last message, I noticed that Sun now has
Click to expand...
a version of Java newer than the one I had before, and decided to install
this update. The Google Toolbar program is offered at the same site,
so I thought I'd let you know that if you're using the Windows Mail
program that comes with Vista, you should avoid installing the Google
Toolbar program unless you want to see what problems it causes in
Windows Mail, although it often doesn't cause them immediately.
Web sites that offer to let you do Google searches don't cause the same
problems.
 
"Robert Miles" <robertmiles@bellsouthNOSPAM.net> wrote in message
news:_tU1k.736$RY.138@bignews8.bellsouth.net...
"rickman" <gnuarm@gmail.com> wrote in message
news:3253a340-9804-4fd5-b6d8-df9dd706ae86@c58g2000hsc.googlegroups.com...
[snip]
Independant of the UI issues, a program really shouldn't crash when it
reads a data file... of any nature. Of course that is a theoretical
goal and can be difficult to achieve in practice. But certainly
crashing on startup without visible error messages is not a good thing
either. I had to start it from a DOS box to get anything useful from
it... maybe that is more of a Java issue... and don't get me started
complaining about Java. Does *anything* written in Java actually
work?

I suggest that any program for Windows Vista that uses Java should
start with a check to see if Java is even installed, and if so, whether
the version installed is suitable for what the program needs. My version
of Vista came without Java, and the Microsoft version is no longer
available. I installed the Sun version, but still have problems with
getting
all the programs that use Java to run correctly.

http://www.java.com/en/

When getting the URL for that last message, I noticed that Sun now has
Click to expand...
a version of Java newer than the one I had before, and decided to install
this update. The Google Toolbar program is offered at the same site,
so I thought I'd let you know that if you're using the Windows Mail
program that comes with Vista, you should avoid installing the Google
Toolbar program unless you want to see what problems it causes in
Windows Mail, although it often doesn't cause them immediately.
Web sites that offer to let you do Google searches don't cause the same
problems.
 
On 2008-06-05, rickman <gnuarm@gmail.com> wrote:
On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com
wrote:

Do you work in the NHS, or for one of their equipment suppliers?
All the CUI references (includinghttp://www.mscui.net/seem to be
associated with the health care sector.

I have no idea what you are talking about... I am an electronic
design engineer and have never worked in the health care sector. What
exactly is NHS? Is that a government agency or a company?
Click to expand...
NHS = National Health Service, the state run healthcare provider
here in the UK. Unlike state healthcare provision in the US the
NHS is fairly comprehensive and covers the entire population (paid
for out of general taxation). As a result it is a massive organisation
- it dwarfs the entire Ministry of Defence, for instance. ISTR it
is Europe's biggest employer.

I'm really not trying to bash the tool. I expect there are those who
like it and use it. I have often wanted a good tool for drawing
waveforms and timing diagrams. But the very first and most important
feature is that it has to be easy and intuitive to use. I feel that I
should be able to sit down and use it without reading a manual or
taking a tutorial. Many years ago I did that with a Mac! I expect
most people do that with the iPhone and iPod. A timing diagram editor
is not a complex tool. I should be able to draw simple waveforms
without learning a complex interface. I currently use Visio and I
find that to be a burdensome tool for simple things. It also has its
own ways in which it doesn't work. I just wanted something a bit
simpler.
Click to expand...
Interesting that you mention Macs. For many years Apple have
published user interface guidelines that document exactly how UIs
should behave. I recall looking through the one for the Newton a
few years ago and it was very prescriptive and quite forceful in
places. I remember it was full of things like "This UI component
has square corners. This other component has rounded corners. If
you need to reimplement them for some reason you stick to those
conventions or your users will be swamping your helpdesk with
support enquiries." This might not give designers as much leeway
to create "really cool" interfaces but I suspect it is more in
tune with what many users actually want.

This is also an area where Microsoft have completely lost the plot.
Since Windows 95 every major release of Windows has been accompanied
by a new interface. Applications are even worse - I don't know
how many style of toolbar have been played with over the last 15
years. Microsoft always make great play of the new interface but
who exactly does it benefit? Users are forced to learn new interfaces
every upgrade and application developers are forced to 'upgrade'
their programs with the new UI or risk being considered outdated.

The only people I can see benefiting are Microsoft themseleves (it
provides a very obvious reason to upgrade, even if it does lack
clear benefits) and hardware manufacturers (the upgrade needs newer
faster hardware). For all the talk of enhancing the user's experience
it seems obvious to me that MS don't give a shit about users. All
that matters is ensuring that the revenue keeps coming in from
repeated meaningless upgrades.

--
Andrew Smallshaw
andrews@sdf.lonestar.org
 
On 2008-06-05, rickman <gnuarm@gmail.com> wrote:
On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com
wrote:

Do you work in the NHS, or for one of their equipment suppliers?
All the CUI references (includinghttp://www.mscui.net/seem to be
associated with the health care sector.

I have no idea what you are talking about... I am an electronic
design engineer and have never worked in the health care sector. What
exactly is NHS? Is that a government agency or a company?
Click to expand...
NHS = National Health Service, the state run healthcare provider
here in the UK. Unlike state healthcare provision in the US the
NHS is fairly comprehensive and covers the entire population (paid
for out of general taxation). As a result it is a massive organisation
- it dwarfs the entire Ministry of Defence, for instance. ISTR it
is Europe's biggest employer.

I'm really not trying to bash the tool. I expect there are those who
like it and use it. I have often wanted a good tool for drawing
waveforms and timing diagrams. But the very first and most important
feature is that it has to be easy and intuitive to use. I feel that I
should be able to sit down and use it without reading a manual or
taking a tutorial. Many years ago I did that with a Mac! I expect
most people do that with the iPhone and iPod. A timing diagram editor
is not a complex tool. I should be able to draw simple waveforms
without learning a complex interface. I currently use Visio and I
find that to be a burdensome tool for simple things. It also has its
own ways in which it doesn't work. I just wanted something a bit
simpler.
Click to expand...
Interesting that you mention Macs. For many years Apple have
published user interface guidelines that document exactly how UIs
should behave. I recall looking through the one for the Newton a
few years ago and it was very prescriptive and quite forceful in
places. I remember it was full of things like "This UI component
has square corners. This other component has rounded corners. If
you need to reimplement them for some reason you stick to those
conventions or your users will be swamping your helpdesk with
support enquiries." This might not give designers as much leeway
to create "really cool" interfaces but I suspect it is more in
tune with what many users actually want.

This is also an area where Microsoft have completely lost the plot.
Since Windows 95 every major release of Windows has been accompanied
by a new interface. Applications are even worse - I don't know
how many style of toolbar have been played with over the last 15
years. Microsoft always make great play of the new interface but
who exactly does it benefit? Users are forced to learn new interfaces
every upgrade and application developers are forced to 'upgrade'
their programs with the new UI or risk being considered outdated.

The only people I can see benefiting are Microsoft themseleves (it
provides a very obvious reason to upgrade, even if it does lack
clear benefits) and hardware manufacturers (the upgrade needs newer
faster hardware). For all the talk of enhancing the user's experience
it seems obvious to me that MS don't give a shit about users. All
that matters is ensuring that the revenue keeps coming in from
repeated meaningless upgrades.

--
Andrew Smallshaw
andrews@sdf.lonestar.org
 
"testbench" <k.gopi.krish@gmail.com> wrote in message
news:be499484-cb46-4e6f-abeb-4dd5ba9e721f@j33g2000pri.googlegroups.com...
Hi
I started a portal www.testbench.in
On this portal , I presented materials for Systemverilog, Vera,
SystemVerilog Randomization, Systemverilog Assertions and Testbech
concepts for beginners.
I tried to explain Methodologies like VMM, RVM and AVM with a simple
Ethernet-Switch example, It will also helps you to understand the
Verification Environment structure.
I presented the complete verification for Ethernet in Systemverilog
and Vera using VMM and RVM methodologies.
I also covered the basic Verilog for beginners and verilog,
Systemverilog, Specman Interview questions .

"I believe the best and easiest way to learn any complex subject is
through examples and that is the reason why I tried to explain the
subject through many examples".

Please visit www.tesbench.in and give your valuable feedback and help
me to improve the quality of the content.

Thanks
Gopi
www.testbench.in
Click to expand...
You might at least spell your site name consistently
 
"testbench" <k.gopi.krish@gmail.com> wrote in message
news:be499484-cb46-4e6f-abeb-4dd5ba9e721f@j33g2000pri.googlegroups.com...
Hi
I started a portal www.testbench.in
On this portal , I presented materials for Systemverilog, Vera,
SystemVerilog Randomization, Systemverilog Assertions and Testbech
concepts for beginners.
I tried to explain Methodologies like VMM, RVM and AVM with a simple
Ethernet-Switch example, It will also helps you to understand the
Verification Environment structure.
I presented the complete verification for Ethernet in Systemverilog
and Vera using VMM and RVM methodologies.
I also covered the basic Verilog for beginners and verilog,
Systemverilog, Specman Interview questions .

"I believe the best and easiest way to learn any complex subject is
through examples and that is the reason why I tried to explain the
subject through many examples".

Please visit www.tesbench.in and give your valuable feedback and help
me to improve the quality of the content.

Thanks
Gopi
www.testbench.in
Click to expand...
You might at least spell your site name consistently
 
In article <to7964tcofj91iu10mrsn4hmke0smgiu4r@4ax.com>,
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:
On Fri, 27 Jun 2008 00:54:58 -0700 (PDT), Michael wrote:

always @(*)
begin
if (something_happened) begin
do_something
end
end

You should aware of the tasks and functions used in such "always". If
your task/function uses a signal not defined as an input of the task
and no other construction of the "always" uses it either, the
simulation result will be wrong.

Yes, that's probably the most important of the "wrinkles"
I mentioned; thanks for emphasising it.

This is one of the reasons why SystemVerilog's "always_comb"
is such a big improvement over "always @*" for design.
Many tools now support always_comb, and you should use it
if you can.
Click to expand...
Another problem with always @*: shared loop induction variables:

integer x;

always @*
begin
if (z)
for (x = 0; x != 10; x = x + 1)
... y = ...
end

always @*
begin
if (foo)
for (x = 0; x != 10; x = x + 1)
... z = ...
end

When foo happens, always block 2 writes to z. This triggers always block 1
which writes to y. All is well. Oh wait: x is written to by always block 1
and is in always block 2's sensitivity list due to the @*, so always block 2
is re-triggered, which triggers block 1, ... the simulation locks up, but
synthesis will work fine.

Basically each always @* block needs to have its own induction variables.
Do not share them.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
 
<aishwaryagroup1@gmail.com> wrote in message
news:aafc5643-5f52-494b-859e-07026498f226@y38g2000hsy.googlegroups.com...
FREE DOWNLOAD SOFTWARE

http://freesoftware20.blogspot.com
Click to expand...
What if any free software related to Verilog does it offer?
I didn't see any.
 
"timinganalyzer" <timinganalyzer@gmail.com> wrote in message
news:90d4289c-fa23-43c0-b569-ac969df7ccf8@l64g2000hse.googlegroups.com...
Hi All,
You can download the TimingAnalyzer now and read all about it at:
Click to expand...
You have too much faith in my abilities.
The only download reference I could find (Beta 0.70) was a dead link.

I tried editing the link in the obvious way:

http://members.aol.com/linuxr2d2/ta_b86_install.jar

but that didn't work either.

Pete
 
The other suggestions of simulating first are appropriate; most of the time,
it is a coding error that could cause such a problem.

Do you have access to another synthesis tool? If you do, you could see how
it behaves. Some 4 or 5 years ago, with a much earlier version of
Precision, I had a similar problem. They fixed that bug (which incorrectly
optimized out lots of stuff.)

JTW


"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:6cvosvF45mkU1@mid.individual.net...
robquigley@gmail.com wrote:

I'm using Precision Synthesis and i want to stop it optimizing some
code that results in shared registers being used, say for example
where i have a 32 bit register initialized on reset to all 1's it's
being replaced by a single register set to 1 shared 32 times. These
registers are just assigned to all 1's for a default as they are later
populated with data read from memory.

I would run a sim to see why this is not happening.

The subsequent assignment of data read from memory to these registers
seems to be ignored.

Or they aren't described correctly.

There probably is some other issue at play here but if i can rule out
the synthesis tool being the problem then i can confirm it's my dodgy
code! :-O

I wouldn't blame synthesis until
I had a working sim on a synchronous design.


-- Mike Treseler
Click to expand...
 
tiwari <tiwari.naveen@gmail.com> wrote in news:c5d255b6-abf6-425a-a9c2-
ddf45c3cdaec@1g2000pre.googlegroups.com:

On Jul 26, 3:56 am, benn <benn...@hotmail.com> wrote:
I have a 25Mhz clock that I wish to divide down to around 1.5Mhz..

I tried looking for examples, but it seems they all use PLLs!     Is
something like this the way its normally done:

wire oClk_1p5MHz;
reg [16:0] Counter;

always@ (posedge iClk_25Mhz)
begin
        Counter <= Counter + 1'b1;
End

assign  oClk_1p5MHz = Counter[3]; // Counter[0] = Input/2, Counter[
1]
= Input/4, Counter[2]/8; Counter[3]/16

Is this normally considered the preferred (safe) method, or will this
blow up when things wrap around?

Actually, this method will not generate a accurate 1.5Mhz clock. For
exact 1.5MHz clk, first you have have to generate a 75Mhz clk from
25mhz clk and then divide 75MHz clock by 50 to get exact 1.5MHz clock.
Click to expand...

I'm betting it's 1.544MHz anyway. Are there any other commonly
encountered frequencies close to 1.5MHz?

Allan
 
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