need a cheap student edition FPGA

<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
<info2@rayed.de> wrote in message
news:94bfff2e-4928-48de-97fb-e622abab0cd1@j22g2000hsf.googlegroups.com...
How are the experiences of others with tools claiming to support SV?
Click to expand...
Modelsim-PE
PE ... has basically the same language-parser as the much more
expensive Modelsim-SE, minus the 'advanced verificaton/testbench' features.

The best thing is, Xilinx's OEM version (XE 6.3c) is a great, free way to
practice Systemverilog synthesis-constructs. Ironically, Xilinx ISE/webpack
doesn't support systemverilog yet. (Altera Quartus-II does!)
I'm hoping the next release of ISE/Webpack (11.x?) comes with XE 6.3h or
later -- that'll let me practice OVM 2.0

Synopsys VCS used to be the premier simulator for Systemverilog. Now that
Cadence has finally stopped dragging their feet, and partnered with Mentor
to
offer a competing "de-facto" verification environment (OVM), I'd say Cadence
IUS
is *finally* usable for Systemverilog simulation.

Cadence IUS81
This is the only commercial simulator I have regular access to.
As of 8.1, it's still missing a ton of little things the competition
handles --
let's see, unions, constant-expressions in enum-declarations (must be
'literal'
constants), etc. Nothing major, but all these small annoyances add up.
For example, using the $cast(dest_var, source_var) operator on an enum
ALWAYS fails. Here's an example:
if ( ! $cast( my_enum, my_int) )
$display( "ERROR, can't cast %0d to my_enum!", my_int );
else
$display( "my_int -> my_enum = '%s'", my_enum.name() );

The same code runs fine in Modelsim PE 6.2 (and Questasim/SE, I assume.)

Aldec Active-HDL 7.3sp1 -
I only tried to web-evaluation, but it's far behind Modelsim-PE. It
doesn't even
support package/endpackage, which renders it unusable for any kind of
shared-code organization. (Why would you leave such a critiical language
feature
out for this long?!?) I have high hopes, though. Earlier this year, Aldec
announced future (planned) support for OVM -- so at least Aldec's
flagship, Riviera Pro, is due for more overhauling.

Altera Quartus-II 8.0sp1:
I'm impressed with the level of systemverilog-support...outstanding for a
free tool! Some limitations but very usable for smaller projects. Too bad
Altera's Modelsim (AE 6.1g) is so old, it's not usable for Systemverilog
design.

Synopsys Design Compiler:
Well, definitely the gold-standard in Systemverilog synthesis. (I'd like
to know
how Cadence's RTL Compiler compares.) In terms of comprehensive
Systemverilog
support, Synopsys has it all from top to bottom (synthesis, simulation, LEC,
LINT, etc.)
 
sharp@cadence.com> wrote in message
news:36dc98f7-96f9-4132-aa70-72bf3d94cb51@u6g2000prc.googlegroups.com...
On Jul 24, 6:11 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
Does anybody know how to save the result of the ncverilog preprocessor
to a single file? Thanks in advance.

NC-Verilog does not use a separate preprocessor or preprocessor pass.
Things like macros and `includes are handled by the parser as they are
encountered.
Click to expand...
I don't suppose there are plans to add this functionality to irun 8.2?

Some of the OVM-macros are so complicated, it's very hard for a
human to visualize the macro-scattered code without being to
see the preprocessor's output.

At the moment, we're using Novas verdi-2008 to get around this.
As long as the code compiles successfully, Verdi-2008's GUI source-browser
paints the macro-substitited text side-by-side with the original text.

(IUS81's source-browser only does a 'first-level' substitution. It
doesn't auto-recurse nested macros, so it's very limited in usefulness.)
 
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