need a cheap student edition FPGA

[David Brown]

Chloe,

If you are designing the circuit as an ASIC implementation, you should also
take into account testability issues. In many cases the internal clock needs
to be a divide by of the main clock for for power reduction, but doesn't
need to be a symetrical clock. The following circuit provides the divide-by
function with a 25/75 duty clock, allows easy clock balancing, and easy
implementation of scan since the clock path has a constant delay whether in
scan or functional mode.

It might be worth drawing out the circuit to get a better understanding on
it's operation.

Hope this helps!

David Brown

////////////////////////////////////////////////////////////
// Divide by 2 clock
////////////////////////////////////////////////////////////

module div_by_2(
clk, // system clock input
resetb, // async reset (low true input)
test_enable, // Used for scan testing, turns clock on at 1x
clock rate
clk_div_by_2_out // Divide by 2 clock output
);

// INPUTS

input clk;
input resetb;
input test_enable;

// OUTPUTS

output clk_div_by_2_out;

// PARAMETERS

parameter DELAY = 1; // unit delay used to mimic structural netlist
// delays
// Wires

wire clk_div_by_2_out;
wire clk_enable;

// Registers

reg div_by_ff;
reg clk_en_ff;

//////////////////////////////////////
// CODE
//////////////////////////////////////

// Toggle Flip Flop

always@(posedge clk or negedge resetb)
begin
if(!resetb)
div_by_ff <= #DELAY 1'd0;
else
div_by_ff <= #DELAY ~div_by_ff;
end

// Clock Enable Flip Flop

always@(negedge clk or negedge resetb)
begin
if(!resetb)
clk_en_ff <= #DELAY 1'd0;
else
clk_en_ff <= #DELAY div_by_ff;
end

assign clk_enable = test_enable | clk_en_ff;

assign clk_div_by_2_out = clk_enable & clk;

endmodule


//////////////////////////////////////
// Test Bench
//////////////////////////////////////

module test();

reg clk; // Clock input
reg resetb; // Async Reset Input (Low true)
reg test_enable; // Test Enable Input used for scan testing

wire clk_div_by_2_out; // Clock divide by 2 output 25/75 duty cycle

// Code

always #10 clk = ~clk;

// Initialization

initial
begin

$dumpfile("test.vcd");
$dumpvars(0,test);
$dumpon;

clk = 1'b0;
test_enable = 1'b0;
resetb = 1'b1;

#22 resetb = 1'b0; // reset circuit (offset from clk)
#20 resetb = 1'b1; // release reset

#1000 resetb = 1'b0; // place back in reset
#10 test_enable = 1'b1; // place in test mode
#20 resetb = 1'b1; // release reset

#1000 $finish; // End of test

end

div_by_2 div_by_2(
.clk(clk),
.resetb(resetb),
.test_enable(test_enable),
.clk_div_by_2_out(clk_div_by_2_out)
);

endmodule





"Chloe" <chloe_music2003@yahoo.co.uk> wrote in message
news:1118193616.986756.67250@f14g2000cwb.googlegroups.com...

Hello everyone,

I'm very new to Verilog and hardware design, so any help or advice
given would be appreciated.

I have 2 clocks in my design. First clock is running at 60MHz, and the
other one is generated at a divided frequency of 2 from the first
clock, ie at 30MHz. Because its frequency is only divided by two, I
don't see the need for a counter. But please check and let me know if
I'm thinking wrongly:

-----------------

module FreqDivider(in_clk, out_clk, rst);
input in_clk;
input rst;

output out_clk;
reg out_clk;

always @(posedge in_clk or negedge rst)
begin
if (!rst)
begin
out_clk <= 1'b0;
end
else
out_clk = ~out_clk;
end
endmodule

-------------------------

testbench :

module FreqDiv_tb();

wire out_clk;
reg in_clk;
reg rst;

initial
begin
rst = 0;
in_clk = 0;
forever #10 in_clk = ~in_clk;
end

initial
begin
#1000;
rst = 1;
#1000;
rst = 0;
#1000;

#10000 $finish;
end

FreqDivider freqdiv_inst (in_clk, out_clk, _rst);
endmodule


------------------------------

It's an asynchronous design.
Would the RTL (not the testbench) be synthesizable? What about the race
conditions?

Thanks very much in advance.

 

[Jason Zheng]

seektm@hotmail.com wrote:

Is it useful to use this directive in the case statements included in
sequetial always block(that is, always @(***edge ...))?

for a more complete answer, see cliff cumming's notes:

http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf

Hopefully it will resolve all the doubts that you have about "full case"
and "parallel case" directives.

cheers,

jz

 

[Matthieu MICHON]

Giox wrote:

can you provide me some reference to the documentation that documents
that?
Moreover a LUT of 256 byte has an acceptable size or is too big?
I know this is a stupid question, but I'm a newbye
Thanks a lot

Hi


I may be mistaken but, from where I sit, it seems that you are trying to
implement a a 8:8 LUT (8-bit wide input, 8-bit wide output) ? If this
is the case, I guess that a simple 256 bytes ROM would do the job.

 

[Ray Andraka]

Giox wrote:

Hello everybody, I'm a newbye in FPGA so I need some help in a simple
problem.
I would like to implement a 256 byte LUT on a Virtex 300 E FPGA.
Can you suggest me some on line resource that explains how to implement
this LUT, how to select the memory resources that I want use for this
task etc?
Thanks a lot for any help, Giovanni



Unless you don't have the BRAM to spare, I'd use a BRAM for this. The

easiest method is to use the core generator and an initialization file.
Alternatively, you can instantiate a RAMB16 and set up the INIT
attributes with your data.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Chris F Clark]

Yes, you can use non-blocking assignments in Verilog and fill the
values through VPI. However, becuase you are modeling a clocked flop,
you have to make sure the "clock" is run (your always block is
conditioned on posedge clock) to see the output get moved to its
destination.

Note, that even after you cause a posedge on clock to occur, due to
the "update event" nature of non-blocking assignments, you may still
have to wait a (teeny) bit to get to the point when the update events
are processed (it will still be at the same "time", but it is later in
the event queue). What, I'm trying to say here, is if you use VPI to
change the value of the clock and you immediately (in the same routine
calling VPI functions, without waiting for a later callback) check the
value of the output. It won't have changed. However, if you get the
Verilog time value at the point where you set the clock, and then wait
for the "value change" callback on the output and get the Verilog time
value again. The two values of time should be the same. Time hasn't
advanced, but the simulator did do some more work within the same
point of time. The standard tells the simulator exactly when it is
allowed to do that work, and it makes sense, once you understand the
model. However, the way certain things work only makes sense once you
understand the model.

-Chris

 

[Hal Murray]

Moreover a LUT of 256 byte has an acceptable size or is too big?
I know this is a stupid question, but I'm a newbye

Get the data sheet for the chip you are considering using.

Most recent FPGAs have blocks of RAM. If you aren't using them
for anything else then a big LUT/ROM is a great use for them.
If you have better uses for all of the then maybe you should do
something else for this part of the problem.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[John_H]

comp.lang.verilog wrote:

Can't I pass array of signals (each signal having two bits) to a
module.
i tried lot on this ,is it possible in verilog.
Here is what i tried:

module traffic_controller(light[3:0],clk,reset);
//port declaration
output [1:0]light[3:0]; //I require to output 4 signal lines with each
signal having 2 bits
input clk;
input reset;

This is not working .What is the way to do this?

The example code is Verilog2001. Multi-dimensional arrays are not
supported in Verilog so we just have to work around the restriction by
sticking with one-dimensional arrays.


wire [1:0] light [3:0];

traffic_controller my_instance
( .lights( {light[3],light[2],light[1],light[0]} )
, .clk( clock )
, .reset( rst )
);

....

endmodule

module traffic_controller
( output [7:0] lights
, input clk
, input rst
);

wire [1:0] light [3:0];
assign {light[3],light[2],light[1],light[0]} = lights;

....

endmodule

 

[Rob Dekker]

Verilog 95 and Verilog 2001 don't allow multi-dimensional arrays (or array-of-arrays) on the port list.
In System Verilog, all these restrictions are lifted, and no more work-arounds are needed to
model ports of any data type.

So if you can get your hands on System Verilog tools, you'll have a lot less restrictions.

Rob

"comp.lang.verilog" <pankaj.nagpal@gmail.com> wrote in message news:1119438062.091301.79200@o13g2000cwo.googlegroups.com...

Can't I pass array of signals (each signal having two bits) to a
module.
i tried lot on this ,is it possible in verilog.
Here is what i tried:

module traffic_controller(light[3:0],clk,reset);
//port declaration
output [1:0]light[3:0]; //I require to output 4 signal lines with each
signal having 2 bits
input clk;
input reset;

This is not working .What is the way to do this?

 

[Ira Baxter]

"Hendrik Greving" <hendrik.greving@rwth-aachen.de> wrote in message
news:3gt1biFe728cU1@news.dfncis.de...

does someone know by any chance a (free) VHDL parser/compiler which is
able to produce boolean expressions from VHDL code?

Not free, but able to extract arbitrary well-structured code fragments
(including booleans).
Can even apply boolean equational operations (composition, simplification).
Options to process Verilog, SystemVerilog, VHDL, and SystemC.
See http://www.semdesigns.com/Products/FrontEnds/index.html


--
Ira D. Baxter, Ph.D., CTO 512-250-1018
Semantic Designs, Inc. www.semdesigns.com

 

[Eyck Jentzsch]

priya wrote:

Hi all,

I am working in Verilog Vpi .Here i am pasting boyh verilog and
verilog vpi code.

verilog code


module Sendoutput(du1,out);
input out;
output du1;
wire [0:7]out;
reg du1,a;
initial
begin
du1=0;
a=1;
$Sendoutputs_to_VerilogPLI(top.se1);
end
endmodule


verilog vpi code


#include <stdlib.h
#include <stdio.h
#include "vpi_user.h"
#include "veriuser.h"
int PLIbook_ShowNets_calltf1();
void PLIbook_ShowNets_register(void)
{
p_vpi_systf_data systask_ptr;
s_vpi_systf_data systasks[] =
{
{ vpiSysTask, 0, "$Sendoutputs_to_VerilogPLI",PLIbook_ShowNets_calltf1
, NULL, NULL, NULL },


0

};

systask_ptr = &(systasks[0]);

while (systask_ptr->type)

vpi_register_systf(systask_ptr++);

}
int PLIbook_ShowNets_calltf1(char *user_data)
{
int i=0;
char *a,*b;

vpiHandle systf_handle, arg_iterator, module_handle,
net_iterator, net_handle,net_handle1;

s_vpi_time current_time;
s_vpi_value current_value;
systf_handle = vpi_handle(vpiSysTfCall, NULL);
arg_iterator = vpi_iterate(vpiArgument, systf_handle);
current_value.format = vpiBinStrVal;
if (current_value.format == vpiBinStrVal)
{
if (net_iterator == NULL)

vpi_printf(" no regs found in this module\n");
else
{

module_handle = vpi_scan(arg_iterator);

vpi_free_object(arg_iterator);

net_iterator = vpi_iterate(vpiReg, module_handle);

net_handle = vpi_scan(net_iterator);

vpi_get_value(net_handle,&current_value);

a=current_value.value.str;

printf("the first reg values is %s",a);

net_handle1 = vpi_scan(net_iterator);

vpi_get_value(net_handle1,&current_value);

b=current_value.value.str;

printf("the second reg values is %s",b);
printf( "the reg value is %s %s ",a,b);

}

}

}
return 0;
}




here output of the program

the first reg value is 1
the second reg value is 0

the reg values is 0 0


here my doubt is third printf statement

actually it will print the value is 1 0
but i got the output is 0 0

Here i Dont know why its was coming like this....

could anyone plz clarify my doubts....


Regards,
Priya.

You assign assign a and b the same value, the pointer to the string

representation inside of current_value.
If you want a copy (and you want) tha do a strdup:
a=strdup(current_value.value.str);
and don't forget to free the memory after usage.
regards

-Eyck

 

[Avrum]

The original poster asked what happens when two different blocks assign to
the same "reg". Having two different drivers on a wire can result in
contention, but not so with a reg...

A reg will hold the value most recently assigned to it via a procedural
assignment (an = or <= inside a procedural block). The concept of "most
recently" can be somewhat complex depending on what triggers the procedural
blocks.

As far as the verilog LANGUAGE is concerned, this is perfectly legal, and
the rules for the value for this reg during simulation are clear; the reg
has the most recent value as determined by the order of execution of the
different procedural statements, with appropriate delays. When the two
procedural statements take effect during the same time tick, the language
specifies which, if either, occurs "later" in the time tick; in some
circumstances (i.e. two similar assignments in different blocks) it even
states that the result may be implementation specific - the simulator may
choose which one to do first, and both orders are "correct" even though they
will result in different values at a given time tick.

Synthesis, however, is an entirely different matter. A synthesis tool
attempts to create logic that will produce the same results as the verilog
code. However, only a subset of what is possible in the verilog language
maps to logic. Furthermore, there is a limit to what synthesis tools can do
to in terms of understanding the code to create logic.

For the most part, what you are describing is not synthesizable. Many pieces
of code that have this structure simply do not map to any real hardware;
many will result in something like a flip-flop with multiple clocks -
something which doesn't really exist (except for things like DDR registers
in certain FPGAs). While some pieces of code with this structure can be
modelled using logic, synthesis tools don't try and figure out which ones
can and which can't... For example

always @(posedge clk)
if (sel) my_reg <= valuea;

always @(posedge clk)
if (!sel) my_reg <= valueb;

CAN be modelled using real logic - a flop with a MUX in front of it
selecting valuea or valueb based on the value of sel. However, most (all?)
synthesis tools will not allow this and will produce an error message. For
synthesizable structures, a reg should only be given a value in ONE
procedural block (like the code below).

always @(posedge clk)
my_reg = sel ? valuea : valueb; // or many variations on this theme...

Avrum


"Andy Peters" <Bassman59a@yahoo.com> wrote in message
news:1119898164.481367.133200@g47g2000cwa.googlegroups.com...

perltcl@yahoo.com wrote:
Hi

What's gonna happen when two conccurent blocks of logic writing into
the same reg. I have run simulations, and iverilog allows it-- at least
in the case of updating the same counter. What's gonna happen to the
synthesized hardware? I don't see how such logic can get synthesized...

Your simulation will show driver conflicts. If both assignments drive
the same value, then the result is the driven value. If the
assignments are different, you get a Big Red "X."

May I ask why you have more than one block assigning your reg?

-a

 

[Rob Dekker]

"Davy" <zhushenli@gmail.com> wrote in message news:1119850701.883679.257500@g49g2000cwa.googlegroups.com...

Hi all,

There is a problem on How to write FSM in
Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
Most synthesis tools recommend second "Using Two Always Blocks" style.
But I would like to use third "Single Always" style. It seems more
compact.

The "single always" style allows you to model only Moore machines
(there is always a clock cycle between inputs and outputs).

With the "two always" style, you can model either Moore or Mealy machines,
(there can be combinational paths from inputs to outputs)
so it is a bit more versatile.

The "two always" style is a bit 'dangerous', in that you should NEVER forget
to assign all output and state variables in the combinational (case) always statement,
because that could create unintended 'latches'. A safe thing to do is to assign some value
(even 'x' will do) up-front in the combinational (before the case statement starts)
to all the variables that are going to be assigned in the case statement itself.

Synthesis tools should not care which style you use. There should not be a
difference in frequency or critical path (except for the architectural register differences
between Moore and Mealy machines).

What's the pros and cons between the two styles? I see that the third
style may have state transition latency. But does the third style gain
higher frequency and shorter critical path?
Thanks!

Best regards,
Davy

 

[John_H]

<harshal38@gmail.com> wrote in message
news:1119981955.752051.266230@g43g2000cwa.googlegroups.com...

i have written verilog code for following logic. if someone can tell if
is it right?? i am not allowed to use clock here. it has to be latch
based design.

"IF predecessor and successor differ in state
THEN copy predecessor's state
ELSE hold present state."

<code snipped>

Are you tracking a sequence and if that sequence changes you want to report
the value that it changed from?

You have R_in and A_1 as inputs to the module. Aren't you supposed to only
be looking at one input and perform an action when it changes?

Your inputs and outputs are single bits. If the desire IS for single bits,
wouldn't the resulting output be an invert of the input? When predecessor
is 0 (latched to maintain what the predecessor is) and the successor - the
new information - changes to a 1, copy the predecessor (0 until just now) to
the output. When the successor changes back to 0 where the predecessor was
now a 1, copy the predecessor (1 until just now) to the output. Output is
the invert of the input.

If you intend to track more than one bit for this to make more sense, what
happens when more than one bit changes but not at the same femtosecond?

 

[John_H]

<harshal38@gmail.com> wrote in message
news:1119991078.718147.278790@f14g2000cwb.googlegroups.com...

<snip>

the truth table for this block is as follows.

R_in A_1 A_in
-----------------------------
0 0 A_in
0 1 0
1 0 1
1 1 A_in

<snip>

If this is the truth table that your function intends to implement, your
inclusion of A1 = ~A_1 doesn't work with the if( R_in!=A1 ) conditional.
You'd want either (R_in==A1) or (R_in!=A_1) or another possibility
(R_in^A_1).

Can you see that in your code?

 

[Rob Dekker]

<harshal38@gmail.com> wrote in message news:1119991078.718147.278790@f14g2000cwb.googlegroups.com...

thank you very much for your reply.

now, the logic i am trying to implement if for C-element. this
C-element is an asynchronous design building block. the way it works is
explained below.

A C-element can be thought of as an "AND-gate" for events. An event is
generated on the output of the C-element only after an event has been
received on both of the inputs. Thus, the C-element acts as a
synchronizer - if an event occurs on one of the inputs, the C-element
will wait until an event occurs on the other input before changing the
output.

the truth table for this block is as follows.

R_in A_1 A_in
-----------------------------
0 0 A_in
0 1 0
1 0 1
1 1 A_in


The output of an C-element is held whenever the inputs both have the
same value. If the values are different, the output is set to the value
of the R_in input.

and I have not thought about what happens when more than one bit
changes but not at the same femtosecond.
but the way this C_element is put into asynchronous pipeline I think
that would not happen.

again thank you very much for your reply. it would defenitely help.

Should work. Both in simulation and synthesis.
Just beware of a possible race-condition on the latch via R_in (if synthesized).
R_in controls both the input and the gate.

Rob

 

[Peng Cong]

task should be included in a module

"Davy" <zhushenli@gmail.com> ????
news:1120267950.546086.253040@g47g2000cwa.googlegroups.com...

Hi all,
I want to use OVL (http://www.eda.org/ovl/) to start learning assert.
Verilog version was used.
The .h and .vlib file has been changed to .v.
But the file seems have compile error.

(Modelsim 5.6)ERROR: D:/Modeltech_5.6/test/ovl_task.v(1): near "task":
expecting:
MACROMODULE MODULE PRIMITIVE (*

//------- part of ovl_task.h-----------
task ovl_error;
input [8*63:0] err_msg;
begin
error_count = error_count + 1;
`ifdef ASSERT_MAX_REPORT_ERROR
if (error_count <= `ASSERT_MAX_REPORT_ERROR)
`endif
$display("OVL_ERROR : %s : %s : %0s : severity %0d : time %0t :
%m",
assert_name, msg, err_msg, severity_level, $time);
if (severity_level == 0) ovl_finish;
end
endtask
//-------------------------------------

Three files have been packeted
(assert_always.vlib,ovl_header.h,ovl_task.h).

Any suggestions will be appreciated!
Best regards,
Davy

 

[Chris F Clark]

To hoepfully make the point a little more clear, the two .h files
ovl_header.h and ovl_task.h were not meant to be converted into
stand-alone .v files. they were meant to be `included into other .v
files. In particular, ovl_task.h was meant to be included in the
assert_xxx.v (where xxx is the assertion name) files (i.e. the files
that were originally given the .vlib suffix) and ovl_header.h was
meant to be included into a user written .v file that uses assertions.

-Chris

 

[Avrum]

The body of a function is procedural code; it is restricted to the subset of
the language that can go between the begin and end statement in an always or
initial block. As a result, it is not possible to use constructs like wires
or module instantiation inside a function.

That being said, the function you want can be coded by replacing the wire
declaration of 'plus' as a reg, not a wire, and removing the "assign"
keywords from the two additions in the body of the function.

Avrum

"Davy" <zhushenli@gmail.com> wrote in message
news:1120461296.446205.157340@o13g2000cwo.googlegroups.com...

Hi all,

I want to use function to write small combinational logic.
But I found it seems I cannot declear wire in function,why?
Any suggestions will be appreciated!

The func_test have some compile error, why?
//--------func_test---------------
module func_test(
in_1,
in_2,
in_3,
out,
);

input [5:0] in_1;
input [5:0] in_2;
input [5:0] in_3;

output [5:0] out;

assign out = plus(in_1,in_2,in_3);

function [5:0] plus;
input [5:0]in_1;
input [5:0]in_2;
input [5:0]in_3;
wire [5:0] plus;
begin
assign plus = in_1+in_2;
assign out = plus + in_3;
end
endfunction

endmodule

Best regards,
Davy

 

[Rob Dekker]

Hi Ashish,

System Verilog does not allow function overloading,
which means that multiple constructors would not be allowed.

Rob

P.S. The Verific parser(s) issues an error (on the second declaration of "new") :

overloading.v(9): ERROR: new is already declared (VERI-1116)



"Ashish Dobhal" <ashish.dobhal@gmail.com> wrote in message news:1120165660.996083.141000@g47g2000cwa.googlegroups.com...

Can we have multiple constructors in a single class in System Verilog?
E.g.,

module test;

class A;
int i;
function new();
i=0;
endfunction

function new(input int a);
i=a;
endfunction

endclass

A a1;
initial
begin

a1=new(2);
$display("value is :%d",a1.i);
end

endmodule

 

[Rob Dekker]

Hi Chris,

According to the syntax rules (Annex A), each constraint block should end with a semi-colon.
Even if it is the one and only one in the list.

So "{x < y;}" is correct and "{b - a > length}" seems to be a typo in the example.

This is counter-intuitive, but so are many, many other syntax rules in System Verilog..

Rob


"Chris Briggs" <chris@engim.com> wrote in message news:1120252628.807903.141970@g47g2000cwa.googlegroups.com...

I just noticed that the constraint block examples in section 12 show a
semicolon inside the closing brace, except for the example in section
12.11.1 for 'std::randomize() with' which doesn't have that semicolon.

E.g., with semicolon:
success = p.randomize() with {x < y;}; // from section 12.6
^

E.g., without semicolon:
success = std::randomize(a, b) with {b - a > length}; // from 12.11.1

Is this an LRM typo or did they mean for constraints on scope variables
to not have that semicolon? And if so, why?

-cb