EDK : FSL macros defined by Xilinx are wrong

John Mashey wrote:

Of course, lots of ISAs have borrowed
from each other, and and ADD is an ADD .

Unless it's a TAD.

Or an A.

Although TAD (for Two's Complement Add) is hallowed by its appearance
on the PDP-8, that isn't really a major alternative.

But there are two basic schools of thought on assembler mnemonics.

One is the IBM 704 school of thought, where every mnemonic is exactly
three letters long.

The other is the IBM 360 school of thought, where the mnemonics are as
short as possible to be distinct.

Of course, today's assemblers tend to draw inspiration from another
computer, the PDP-11, and use various symbols preceding operands to
indicate addressing modes.

John Savard

 

[Symon]

Brijesh,
It is possible to de-glitch your clock in the FPGA. Like this.
Let's call your input clock, 'CLOCK'. OK, feed this into and back out of an
unbonded IOB with the input delay turned on. This gives you 'CLOCK_DELAYED'.
Add a SR latch. When CLOCK = '1' and CLOCK_DELAYED = '0', set the latch.
When CLOCK = '0' and CLOCK_DELAYED = '1', reset the latch. The output of the
latch is your new clock. The IOB-delay filters any glitches shorter than the
delay. Cascade more unbonded IOBs for more delay.
Horrible or what? Make sure you use MAXDELAY constraints in the UCF file,
especially for 'CLOCK' to the latch. Manually place the latch next to the
'CLOCK''s input IOB.
Cheers, Syms.

 

[Eric Smith]

I wrote:

What MIPS invented and patented was the idea that instead of having the
hardware deal with unaligned bus accesses, they require software to
issue *two* instructions to do an unaligned access. One does the
"left part" and one does the "right part" of the word.

Everett M. Greene writes:

This must be a misstatement or it's a ridiculous patent.
How can a patent be issued for NOT doing something?

Of course you can patent something new that eliminates the need
for something old!

The patent is on the two instructions, and their use in eliminating
the need for the usual hardware that would support unaligned access.

There's also the "obvious to anyone experienced with
the technology" thing.

The use of the two instructions in question seemed like something
that wasn't obvious when I first saw them. I think it passes the
obviousness test.

However, the patent office has a much lower bar for obviousness than
you or I would have. Even though I think this patent was reasonable,
they certainly grant many others that I don't think they should.

Eric

 

[Eric Smith]

jon@beniston.com (Jon Beniston) writes:

Embedded FLASH in 90nm is years off,

Why can't one use 130nm (or even 180nm) embedded flash in a chip design
that uses 90nm for everything else? (Yes, I'm largely ignorant of chip
design issues at that level. I usually only do HDL design.)

Eric

 

[Nicholas Weaver]

In article <qhaco912bi.fsf@ruckus.brouhaha.com>,
Eric Smith <eric@brouhaha.com> wrote:

jon@beniston.com (Jon Beniston) writes:
Embedded FLASH in 90nm is years off,

Why can't one use 130nm (or even 180nm) embedded flash in a chip design
that uses 90nm for everything else? (Yes, I'm largely ignorant of chip
design issues at that level. I usually only do HDL design.)

Requires significant additional process steps, which may be
incompatable with the 90nm process.



--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu

 

[Sebastian Weiser]

Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message news:<d33k4c$sjr$1@solaris.cc.vt.edu>...

We have a board with multiple IDE interfaces implemented in Virtex2
device. We are using UDMA 3 protocol.
One of the boards is giving a CRC error at random times, erros occurs
once in 12 hrs of continous read operations. Error occurs on the same
IDE channel.

According to the ATA/ATAPI spec, you need input buffers with at least
320 mV of hysteresis. The appendix notes that double clocking of the
CRC calculator while capturing the correct data or calculating the
correct CRC while capturing wrong data had been observed, thus the
requirement. Maybe that's your problem?
BTW: The spec also notes that your inputs must be 5 V tolerant, which
AFAICS can't be achieved on a pure Virtex-II while keeping the correct
dimensions of the series resistors. The FPGA must even widthstand 6 V
ringing voltages. I don't know if a Virtex-II can do this.

All inputs are LVTTL 3.3V, no IBUF delays used on strobe or data. On
Strobe pins I have enabled DCI with 50 Ohm resistor. But now my
understanding is that for LVTTL 3.3V input pins, DCI does no good.

I don't know much about these issues (I design circuits for FPGA/ASICs
and do no "real" hardware), but don't you need to take LVCMOS33 for
outputs?

A separate question I was trying to look up the source impeadance/input
impeadance of V2 outputs/inputs, couldn't find the number anywhere. Are
they specified?

The ATA/ATAPI specs dictate that the series termination plus input
impedance is between 50 and 85 Ohms. How have you taken the values for
your board without knowing those of the FPGA?


Sebastian Weiser

 

[Bret Wade]

Rudolf Usselmann wrote:

Just a short note of caution ....

After installing sp1 for ise 7.1 (linux) mapper is crashing:

map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o
usb_top_map.ncd usb_top.ngd usb_top.pcf
Release 7.1.01i - Map H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Using target part "4vlx25sf363-10".
Mapping design into LUTs...
Writing file usb_top_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs

SNIP

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs

Invoking physical synthesis ...
Abort (core dumped)

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

This problem can be avoided if you turn off that new
"-register_duplication" feature.

Bret

 

[Antti Lukats]

"Bret Wade" <bret.wade@xilinx.com> schrieb im Newsbeitrag
news:d38nu7$6qk6@xco-news.xilinx.com...

Rudolf Usselmann wrote:

Just a short note of caution ....

After installing sp1 for ise 7.1 (linux) mapper is crashing:

map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o
SNIP

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs

Invoking physical synthesis ...
Abort (core dumped)

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis



This problem can be avoided if you turn off that new
"-register_duplication" feature.

Bret

a nice "feature" !!
you should call thise feature "force core dump" then people would know to
avoid it, and not spend hours of frustration!

antti

 

[Peter Alfke]

There is an old slide presentation of mine on the web, where slides 100
and 101 describe a simple way to cope with double-pulsing clocks

..http://www.google.com/search?client=safari&rls=en-us&q=%22peter+alfke%22&ie=UTF-8&oe=UTF-8

Peter Alfke
============================
Sebastian Weiser wrote:

Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message
news:<d33k4c$sjr$1@solaris.cc.vt.edu>...
We have a board with multiple IDE interfaces implemented in Virtex2

device. We are using UDMA 3 protocol.
One of the boards is giving a CRC error at random times, erros
occurs
once in 12 hrs of continous read operations. Error occurs on the
same
IDE channel.

According to the ATA/ATAPI spec, you need input buffers with at least
320 mV of hysteresis. The appendix notes that double clocking of the
CRC calculator while capturing the correct data or calculating the
correct CRC while capturing wrong data had been observed, thus the
requirement. Maybe that's your problem?
BTW: The spec also notes that your inputs must be 5 V tolerant, which
AFAICS can't be achieved on a pure Virtex-II while keeping the
correct
dimensions of the series resistors. The FPGA must even widthstand 6 V
ringing voltages. I don't know if a Virtex-II can do this.

All inputs are LVTTL 3.3V, no IBUF delays used on strobe or data.
On
Strobe pins I have enabled DCI with 50 Ohm resistor. But now my
understanding is that for LVTTL 3.3V input pins, DCI does no good.

I don't know much about these issues (I design circuits for
FPGA/ASICs
and do no "real" hardware), but don't you need to take LVCMOS33 for
outputs?

A separate question I was trying to look up the source
impeadance/input
impeadance of V2 outputs/inputs, couldn't find the number anywhere.
Are
they specified?

The ATA/ATAPI specs dictate that the series termination plus input
impedance is between 50 and 85 Ohms. How have you taken the values
for
your board without knowing those of the FPGA?


Sebastian Weiser

 

Eric Smith wrote:

I wrote:
What MIPS invented and patented was the idea that instead of having
the
hardware deal with unaligned bus accesses, they require software to
issue *two* instructions to do an unaligned access. One does the
"left part" and one does the "right part" of the word.

Everett M. Greene writes:
This must be a misstatement or it's a ridiculous patent.
How can a patent be issued for NOT doing something?

Of course you can patent something new that eliminates the need
for something old!

The patent is on the two instructions, and their use in eliminating
the need for the usual hardware that would support unaligned access.

This certainly does make sense. There definitely is prior art for
computers that do not support unaligned access to memory; the
System/360 comes to mind.

And they can handle unaligned operands, but it takes at least four
instructions:

A 5,ALIGNED

becomes, say

LH 6,UALIGNED
SLL 6,16
IH 6,UALIGNED+2
A 5,6

or even

LC 6,UALIGNED
SLL 6,24
L 7,UALIGNED+1
SR 7,8
N 7,#X'00FFFFFF'
O 6,7
A 5,6

so if the MIPS speeds things up by having a "fetch left half of n
bytes" followed by "fetch right half of N-n bytes, then perform the
operation" instructions (as a RISC chip, it might not have the 'perform
the operation' part) it has indeed done something new.

John Savard

 

[Anne & Lynn Wheeler]

jsavard@ecn.ab.ca writes:

And they can handle unaligned operands, but it takes at least four
instructions:

A 5,ALIGNED

becomes, say

LH 6,UALIGNED
SLL 6,16
IH 6,UALIGNED+2
A 5,6

or even

LC 6,UALIGNED
SLL 6,24
L 7,UALIGNED+1
SR 7,8
N 7,#X'00FFFFFF'
O 6,7
A 5,6

ICM was introduced with 370 ... insert character under mask
ICM 6,B'1111',UNALIGNED
ar 5,6

problem with LH was that it was arithmetic (not logical) and
propogated the sign bit (and it required half-word alignment).

--
Anne & Lynn Wheeler | http://www.garlic.com/~lynn/

 

[Peter Alfke]

Seems like I gave you a bad URL.
Try this one:

http://www.te.rl.ac.uk/esdg/atlas-flt/talks/StockholmXilinx.pdf.

Peter Alfke

 

[Rudolf Usselmann]

Bret Wade wrote:

Rudolf Usselmann wrote:

Just a short note of caution ....

After installing sp1 for ise 7.1 (linux) mapper is crashing:

map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o
usb_top_map.ncd usb_top.ngd usb_top.pcf
Release 7.1.01i - Map H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Using target part "4vlx25sf363-10".
Mapping design into LUTs...
Writing file usb_top_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs

SNIP

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs

Invoking physical synthesis ...
Abort (core dumped)

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis



This problem can be avoided if you turn off that new
"-register_duplication" feature.

Bret

Bret,

Before sp1, "-register_duplication" helped me meet timing when
IO buffer registers needed to be duplicated.
Do you know of another work around ?

Thanks,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

 

[Antti Lukats]

"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
news:115ikci5cm72pe8@corp.supernews.com...

I am fairly new to the FPGA world. I've been using Actel parts
(Axcelerator
family) at work but I would like to migrate to the Xilinx family for the
next generation design for an existing project. I would like to take
advantage of the in-cricuit reprogrammablility and the high speed parts
(either Virtex II or Virtex 4). I've downloaded the free WebPack from
Xilinx and have purchased the Spartan 3 Starter kit. I've done a little
checking into the costs of development tools for home use for embedded
processors.

According to the Xilinx home page advertising the EDK, the package cost is
about $495. This is for a one-year license. Does this mean I would have
to
pay $495 every year I wanted to use this package? Is this the only way to
get support for embedded processors like Microblaze and PowerPC? Are
there
any alternatives (less expensive) for home use? I would like to develop
code for FPGAs (fairly high speed devices... > 300MHz) at home then employ
the designs at work (where a separate license with annual renewal) would
be
established.

Is the EDK to only way to get generation support for Macro models?

Is there a better route to development that anyone could suggest?

Thanks.

Dave

well first of all you dont have to use EDK if you are looking for
alternatives
www.gaisler.com there is free open-source GRLIB SoC and toolchain including
uclinux support for LEON3 (SPARC) softcore, thats completly free, inlcuded
free PCI
and wrapper around ethernet and can from the opencores

the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based system
a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
FPGA the LEON3 SoC is an alternative

of course if at work there is EDK then you must use EDK
Antti

 

[Ziggy]

Antti Lukats wrote:

"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
news:115ikci5cm72pe8@corp.supernews.com...

I am fairly new to the FPGA world. I've been using Actel parts

(Axcelerator

family) at work but I would like to migrate to the Xilinx family for the
next generation design for an existing project. I would like to take
advantage of the in-cricuit reprogrammablility and the high speed parts
(either Virtex II or Virtex 4). I've downloaded the free WebPack from
Xilinx and have purchased the Spartan 3 Starter kit. I've done a little
checking into the costs of development tools for home use for embedded
processors.

According to the Xilinx home page advertising the EDK, the package cost is
about $495. This is for a one-year license. Does this mean I would have

to

pay $495 every year I wanted to use this package? Is this the only way to
get support for embedded processors like Microblaze and PowerPC? Are

there

any alternatives (less expensive) for home use? I would like to develop
code for FPGAs (fairly high speed devices... > 300MHz) at home then employ
the designs at work (where a separate license with annual renewal) would

be

established.

Is the EDK to only way to get generation support for Macro models?

Is there a better route to development that anyone could suggest?

Thanks.

Dave



well first of all you dont have to use EDK if you are looking for
alternatives
www.gaisler.com there is free open-source GRLIB SoC and toolchain including
uclinux support for LEON3 (SPARC) softcore, thats completly free, inlcuded
free PCI
and wrapper around ethernet and can from the opencores

the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based system
a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
FPGA the LEON3 SoC is an alternative

of course if at work there is EDK then you must use EDK
Antti

Not disagreeing with the Leon3 being really cool, but if he doesnt get
the EDK how would one actually load the FPGA? Would there be free tools
to do that?

I also think he wants to really do his own development as well.. Not
just grab a pre-done core.

I know for some of us, $500/year would be steep for a hobby.. ( yes i
realize that the hobby business isnt what supports these companies, so
they really dont care much about us. So free tools are nice. )

 

[Antti Lukats]

"Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag
news:eTc6e.3688$GJ.1717@attbi_s71...

Antti Lukats wrote:
"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
news:115ikci5cm72pe8@corp.supernews.com...

I am fairly new to the FPGA world. I've been using Actel parts

(Axcelerator

family) at work but I would like to migrate to the Xilinx family for the
next generation design for an existing project. I would like to take
advantage of the in-cricuit reprogrammablility and the high speed parts
(either Virtex II or Virtex 4). I've downloaded the free WebPack from
Xilinx and have purchased the Spartan 3 Starter kit. I've done a little
checking into the costs of development tools for home use for embedded
processors.

According to the Xilinx home page advertising the EDK, the package cost
is
about $495. This is for a one-year license. Does this mean I would
have

to

pay $495 every year I wanted to use this package? Is this the only way
to
get support for embedded processors like Microblaze and PowerPC? Are

there

any alternatives (less expensive) for home use? I would like to develop
code for FPGAs (fairly high speed devices... > 300MHz) at home then
employ
the designs at work (where a separate license with annual renewal) would

be

established.

Is the EDK to only way to get generation support for Macro models?

Is there a better route to development that anyone could suggest?

Thanks.

Dave



well first of all you dont have to use EDK if you are looking for
alternatives
www.gaisler.com there is free open-source GRLIB SoC and toolchain
including
uclinux support for LEON3 (SPARC) softcore, thats completly free,
inlcuded
free PCI
and wrapper around ethernet and can from the opencores

the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based
system
a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
FPGA the LEON3 SoC is an alternative

of course if at work there is EDK then you must use EDK
Antti



Not disagreeing with the Leon3 being really cool, but if he doesnt get
the EDK how would one actually load the FPGA? Would there be free tools
to do that?

I also think he wants to really do his own development as well.. Not
just grab a pre-done core.

I know for some of us, $500/year would be steep for a hobby.. ( yes i
realize that the hobby business isnt what supports these companies, so
they really dont care much about us. So free tools are nice. )

I dont get you, all you need is some FPGA S3-400 is enough
then grab GRLIB build your SoC use 5 wires to LPT port cable
to configure the then Sparc SoC already is working in the FPGA
nothing else required.

there is lots todo with GRLIB too

antti

 

[Ziggy]

Antti Lukats wrote:

"Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag
news:eTc6e.3688$GJ.1717@attbi_s71...

Antti Lukats wrote:

"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
news:115ikci5cm72pe8@corp.supernews.com...


I am fairly new to the FPGA world. I've been using Actel parts

(Axcelerator


family) at work but I would like to migrate to the Xilinx family for the
next generation design for an existing project. I would like to take
advantage of the in-cricuit reprogrammablility and the high speed parts
(either Virtex II or Virtex 4). I've downloaded the free WebPack from
Xilinx and have purchased the Spartan 3 Starter kit. I've done a little
checking into the costs of development tools for home use for embedded
processors.

According to the Xilinx home page advertising the EDK, the package cost

is

about $495. This is for a one-year license. Does this mean I would

have

to


pay $495 every year I wanted to use this package? Is this the only way

to

get support for embedded processors like Microblaze and PowerPC? Are

there


any alternatives (less expensive) for home use? I would like to develop
code for FPGAs (fairly high speed devices... > 300MHz) at home then

employ

the designs at work (where a separate license with annual renewal) would

be


established.

Is the EDK to only way to get generation support for Macro models?

Is there a better route to development that anyone could suggest?

Thanks.

Dave



well first of all you dont have to use EDK if you are looking for
alternatives
www.gaisler.com there is free open-source GRLIB SoC and toolchain

including

uclinux support for LEON3 (SPARC) softcore, thats completly free,

inlcuded

free PCI
and wrapper around ethernet and can from the opencores

the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based

system

a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
FPGA the LEON3 SoC is an alternative

of course if at work there is EDK then you must use EDK
Antti



Not disagreeing with the Leon3 being really cool, but if he doesnt get
the EDK how would one actually load the FPGA? Would there be free tools
to do that?

I also think he wants to really do his own development as well.. Not
just grab a pre-done core.

I know for some of us, $500/year would be steep for a hobby.. ( yes i
realize that the hobby business isnt what supports these companies, so
they really dont care much about us. So free tools are nice. )


I dont get you, all you need is some FPGA S3-400 is enough
then grab GRLIB build your SoC use 5 wires to LPT port cable
to configure the then Sparc SoC already is working in the FPGA
nothing else required.

there is lots todo with GRLIB too

antti

Perhaps beacuse some of us want to do our OWN designs too?

 

[Duane Clark]

starfire wrote:

...
According to the Xilinx home page advertising the EDK, the package cost is
about $495. This is for a one-year license. Does this mean I would have to
pay $495 every year I wanted to use this package?

Yes, there is an annual fee, which at least if paid directly through
Xilinx, is $495 (having just paid it a few days ago).

Is this the only way to
get support for embedded processors like Microblaze and PowerPC?

Not strictly. What EDK provides is two main things that I find useful.
First is a fairly painless, complete environment for developing the
hardware and software. More significant, EDK includes (included for the
$495 paid for EDK) a bunch of cores for performing lots of common
functions. For example, cores for all kinds of different memories, both
internal memory and a wide variety of external memory types. That alone
is well worth the price to me. Almost all these cores include VHDL
source too.

Are there
any alternatives (less expensive) for home use? I would like to develop
code for FPGAs (fairly high speed devices... > 300MHz) at home then employ
the designs at work (where a separate license with annual renewal) would be
established.

Well, you might want to read the license carefully. While of course few
will admit it here, I think it is fairly common for people to have
copies of the software at home for this purpose, and frankly I think it
is in the interest of Xilinx to ignore such uses. There is no hardware
license enforcement (via flexlm or whatever) on EDK. Probably the bigger
factor is whether your company allows such use; it is not worth getting
fired over.

Since this apparently would benefit you at work, probably a good way to
obtain EDK and also get familiar with it is to look into some of the
"evaluation" boards offered by the various chip vendors and Xilinx.
Several of these include EDK as part of the purchase price, and some
also include more elaborate tool such as a complete Linux environment
(not included with EDK). I consider that the learning hump on these
tools is quite large, and having a complete working board and
environment to start from was invaluable to me. Without that, it is
clear to me after the fact that I would have spent substantially more
time trying to figure out all the pieces.

 

[Bret Wade]

Rudolf Usselmann wrote:

Bret Wade wrote:


Rudolf Usselmann wrote:

Just a short note of caution ....

After installing sp1 for ise 7.1 (linux) mapper is crashing:

map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o
usb_top_map.ncd usb_top.ngd usb_top.pcf
Release 7.1.01i - Map H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Using target part "4vlx25sf363-10".
Mapping design into LUTs...
Writing file usb_top_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs

SNIP

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs

Invoking physical synthesis ...
Abort (core dumped)

Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis



This problem can be avoided if you turn off that new
"-register_duplication" feature.

Bret


Bret,

Before sp1, "-register_duplication" helped me meet timing when
IO buffer registers needed to be duplicated.
Do you know of another work around ?

Thanks,
rudi

Hi Rudi,

We've seen one similar case and that was a Windows only failure. If you
have access to a Linux or Solaris machine, that might work. On the other
hand, that case wasn't an SP1 regression like yours is, so they may be
different problems. If that doesn't work, a webcase would be the next
suggestion.

Regards,
Bret

 

[Brijesh]

Peter Alfke wrote:

Thanks for the link.
It has some helpful tips and tricks.

Seems like I gave you a bad URL.
Try this one:

http://www.te.rl.ac.uk/esdg/atlas-flt/talks/StockholmXilinx.pdf.

Peter Alfke