EDK : FSL macros defined by Xilinx are wrong

[Mohammed A Khader]

Hi Bert,

You sure you define your address as SIGNED ???
I have also synthezied with unsigned but the same error persist.

It's also asynchronous. Maybe a clocked process ?
did you simulate ?

Its a part of a design , so I have to add some more logic after the
Rom Output. I have used a different architecture for simulation which
does the initialization of ROM from a file but rest is same. Yes, I
have simulated and it worked. But after learning the APEX20KE ESBs I
am thinking to add a register at Rom Output(to make it synchronus) and
make some changes to compensate for extra cycle.

I cannot initialize the ROM in a case statement with 1024 of
words(tooooooo Laborious).Is there any other way to do it . I thought
attribute syn_romstyle(From synplicity ) would help me in recognizing
so that I could initialize the ROM Later while programming the FPGA.
How do you do for such cases.

Thanks a lot.
-- Mohammed A Khader.

 

[Mohammed A Khader]

Hi ken,

Rom is having 1k of 16bit words. Hence I could'nt initialize it in a
case statement. I thought attirbute syn_romstyle would help me in this
..
Is there any other way to do it .

Thanks .

-- Mohammed A Khader.

 

[Ray Andraka]

Mohammed A Khader wrote:

Hi ken,

Rom is having 1k of 16bit words. Hence I could'nt initialize it in a
case statement. I thought attirbute syn_romstyle would help me in this
.
Is there any other way to do it .

Thanks .

-- Mohammed A Khader.



You can define a constant array of integers (even put it in a separate

package) for the rom contents. You'll need to also have functions to
convert the array of integers into the init generics and attributes for
the BRAMs. The advantage of doing it this way is that it is relatively
easy to handle data that is bit sliced over several BRAMs (the init
value function can take care of this) using plain text data. The
integer array constant can be easily copied from Excel or Matlab and
pasted into the constant declaration.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ray Andraka]

Moti Cohen wrote:

Hi all,
I would like to get into a CAM design for FPGA.
Does any of you know about where can I find material on this subject? I
will appreciate stuff like tutorials and reference designs (examples in
any HDL)..

Thanks in advance, Moti.



How big a memory do you need? How sparse is it?

For small CAMs, you can use the Xilinx SRL16 capability to essentially
make custom LUTs that are dependent on the stored words. These take 16
clocks to write, but provide an address look-up in a single cycle once
they are programmed. I believe Xilinx has an app-note on this
technique. I think you can extend the idea to use a BRAM as well,
although the write time starts getting unreasonably large.

As your allowed time for access increases, so do your options. Let us
know what your requirements are, and perhaps one of us can steer you to
a solution that works for your case.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Mike Harrison]

On Wed, 27 Apr 2005 11:43:00 GMT, Rene Tschaggelar <none@none.net> wrote:

The whole is solved by a notebook being the work machine at
the expense of reduced performance.

But yes, the whole is a bit silly.

...and of course entirely unenforceable in practice, unless they insist you have a GPS receiver on
the machine....
How is anyone ever going to know where you physically are when you use it ?

 

[Ziggy]

David wrote:

On Wed, 27 Apr 2005 11:42:58 +0000, Uwe Bonnes wrote:


In comp.arch.fpga license_rant_master <none@nowhere.net> wrote:
: I am an ASIC engineer who frequently 'takes work home' with me.
: Recently, I began using ssh to remotely login to our company's
: servers to run some Verilog/VHDL simulations. Launching
: sims (from the UNIX command line) is fairly easy and painless,
: but any kind of interactive (GUI) operations are pitifully
: slow over an WAN/internet connection. In the past, I
: haven't needed to do much more than check on running jobs,
: restart them, then logout. Now, I find the need to do some
: interactive debugging work (waveform viewing, code editing,
: etc.)

Look at NX. It what LBX (Low Bandwidth X ) promised, but NX
delivers. Probably not to easy to set yet, but worth a try.



It's easy enough to set up the server (either look at the commercial
version from www.nomachine.com, or google for "freenx" or "nxserver") on
linux, and clients are even easier (download free from nomachine). It is
said to be usable over a modem connection - I have certainly found it
works well over ADSL for most work. It's definitely faster than tightVnc
(which is also okay for many things - and works well for pretending you
are sitting at your office windows desktop).



Bye




Too bad its not easy to setup a server in FreeBSD ( i know, totaly OT )

Like others will most likely point out, something like TightVNC would
support compression, and is even easier to setup then NX..

 

[Alex Gibson]

"Ziggy" <Ziggy@TheCentre.com> wrote in message
news:wZwbe.22752$r53.15336@attbi_s21...

Paolo wrote:
Hi,
This board:
http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html
has similar characteristics, besides is available a Software Dev Kit to
immediately develop your program in C++.
My company, buy this board to develop gambling machine. Our company
doesn't have an inside structure to develop hardware, but only software.
Before we developed our software on PC platform. But the PC platform
it's not good for an embedded use. Now with this board we succeed in
realizing excellent products.
On the web page of Seventech, you can also see a sample C++ code to
realize a graphic animation with this board.
With this board it is possible to realize graphic animations with very
good performance and the cost, also for the companies, it is <300$, for
an only piece.

Paolo




That does look interesting, too bad the FPGA doesnt have the dual PowerPC
cores included..

What sort of free tools are available for the altera chips and are they
any good?

Altera Quartus
http://www.altera.com/products/software/products/quartus2web/sof-quarwebmain.html
http://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp
annoyance is having to re-request a license every so often.
Usually happens when you don't have net access
and sometimes can take a few days to get a new one.

Tools quite good.
If you started with xilinx can take bit to get used to.
Maybe a bit less buggy than xilinx tools in my experiance.
(don't crash as often on my machine or ones I have to help support)

Altera have a fpga with an arm core.
http://www.altera.com/products/devices/arm/arm-index.html

Alex

 

[Alex Gibson]

"Ziggy" <Ziggy@TheCentre.com> wrote in message
news:qwxbe.23136$NU4.3286@attbi_s22...

Alex Gibson wrote:
Has any one tried running 7.1 for linux on OS X or darwin or freebsd ?

Even just commandline tools ?

Trying to avoid having yet another computer(or dual boot)

Alex

Not sure how it could work if the linux they support is ix86.. OSX is PPC
remember...

darwin the base of OS X has both ppc and x86 versions
and can be downloaded from

http://developer.apple.com/darwin/

http://www.opendarwin.org/

http://www.gnu-darwin.org/

It doesn't have any of the apple libraries that run on top of darwin
from OS X but can run X11 , kde , gnome etc all the usuall bsd / linux
programs.

Guess I need to get another x86 box then and vmware to run windows and
linux.
need something for ise + edk and for building uclinux for microblaze

Alex

 

[Petter Gustad]

Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com> writes:

Petter Gustad wrote:

Is there an easy way to convert a plain ascii file of hex numbers etc.
into a SOF format or similar in order to program the UFM of the MAX
II?
Petter


I think plain hex-ascii to MIF format is so obvious that you
don't need anything more that a few seconds of your text editor...

Thank you for your reply. I've used MIF files for simulation
previously, but I would like to program the UFM seperately. It seems
like the Quartus II programmer accepts SOF files only. How can I load
the MIF file into the UFM?

Further is there a way I can generate a SVF file to program the UFM?
I would like to program serial numbers etc. into the UFM during
production and testing of some boards containing a MAX II among other
devices.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Antti Lukats]

Hi Petter,

my first attempt to look into the problem caused following exception in
quartus

Internal Error: Sub-system: PGME, File: pgme_tsunami_algorithm.cpp, Line:
1640
data_ptr != NULL
Quartus II Version 4.2 Build 156 11/29/2004 SJ Web Edition

and Quartus self closed itself silently...
hm...next attempt:

Error: JEDEC STAPL Format Files, Jam STAPL Byte Code 2.0 Files, Serial
Vector Format Files, and In System Configuration Files do not support
EPM1270 device


ok your choices

1) to reverse engineer the JTAG commands to program the UFM and write your
own JAM or SVF and play that using JAM or SVF player
2) fight with Altera to provide some solution
3) if you can live that you need to program the UFM before the main then you
can use simple JTAG-BSCAN indirect approuch
4) if you can allocate some 10 to 12 LE you can add the ability to reprogram
the UFM while the MAX2 is programmed (and possible operation)
5) you can hire me todo [1]
6) you can hire me todo [3] or [4]

http://gforge.openchip.org/frs/shownotes.php?release_id=47

there is simple boilerplate that connect the JTAG BSCAN to the UFM for
read/write - its only an starter boilerplate need to add some flip flops and
muxes to get it useable, but it shows a little how the idea would work

Antti










"Petter Gustad" <newsmailcomp6@gustad.com> schrieb im Newsbeitrag
news:87fyxc6vm0.fsf@filestore.home.gustad.com...

Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com> writes:

Petter Gustad wrote:

Is there an easy way to convert a plain ascii file of hex numbers etc.
into a SOF format or similar in order to program the UFM of the MAX
II?
Petter


I think plain hex-ascii to MIF format is so obvious that you
don't need anything more that a few seconds of your text editor...

Thank you for your reply. I've used MIF files for simulation
previously, but I would like to program the UFM seperately. It seems
like the Quartus II programmer accepts SOF files only. How can I load
the MIF file into the UFM?

Further is there a way I can generate a SVF file to program the UFM?
I would like to program serial numbers etc. into the UFM during
production and testing of some boards containing a MAX II among other
devices.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Antti Lukats]

"Bert Cuzeau" <_no_spa_m_info_no_underscore_@alse-fr___.com> schrieb im
Newsbeitrag news:426f3007$0$20473$626a14ce@news.free.fr...

austin wrote:
http://www.xilinx.com/bvdocs/notifications/pdn2004-21.pdf

Is the discontinue notice for somw parts that had extremely low volumes.


Thanks Austin.
The "port" won't be too difficult anyway

Bert

BTW, Atmel AT40K are claimed to be pin-compatible to xilinx XC4K,
but if you can redesign to recent lowcost FPGA then thats possible
preferable.

antti

 

[mb]

Hi thanks a lot guys )

i think ur response was indeed helpful

cheers

 

[Petter Gustad]

"Antti Lukats" <antti@openchip.org> writes:

Hi Petter,

my first attempt to look into the problem caused following exception in
quartus

Internal Error: Sub-system: PGME, File: pgme_tsunami_algorithm.cpp, Line:
1640
data_ptr != NULL
Quartus II Version 4.2 Build 156 11/29/2004 SJ Web Edition

Urg!

You can generate SVF in 4.2SP1:

Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version

I have
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name GENERATE_JAM_FILE ON

in my Tcl script. But I would like to generate SVF files for the UFM
part only. I don't want to run full synthesis, place and route, etc
for each production device.

1) to reverse engineer the JTAG commands to program the UFM and
write your own JAM or SVF and play that using JAM or SVF player

My plan was to write some code to merge in my own data in order to
program the UFM from serial numbers read from a barcode reader.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Subroto Datta]

Hi Petter,

Chapter 9 of the MAX II handbook explains how to use the ALTUFM
megafunction to add UFM data with mif or hex file. The user has to
recompile if they want to change the hex file data, as this is how you
convert it to POF.

This can be found at
http://www.altera.com/literature/hb/max2/max2_mii51010.pdf
(page 9-34 thru 9-38.)

Hope this helps.
Subroto Datta
Altera Corp.



Petter Gustad wrote:

Is there an easy way to convert a plain ascii file of hex numbers
etc.
into a SOF format or similar in order to program the UFM of the MAX
II?

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Antti Lukats]

read what the OP asked!

he wants to program the UFM from MIF or HEX __without__ recompiling!
thats the all problem. dont suggest the obvious things. we all know that an
MIF can be assigned to the UFM and it is merged to POF during compile.

antti
PS what you said certainly does not help the OP !

what would help is when Altera would document the JTAG commands
to program the MAX2 and UFM !

even the BSCAN USER command seems to be big secret if looking at Altera web!
well thats no big deal the instruction is 0x0E but ASFAIK that info is not
to be
found in any public documents from Altera!
cyclone JTAG download is pretty simple (but also not documented)
this no-docu-from-altera is the problem why our FPGA FrequencyMeter
application doesnt support fully Cyclone, we simple have not fully
mastered the JTAG download, yes I looked at the SVF files, etc..
but this type of JTAG command reverse engineering is stupid!!!
would be better to document the obvious things.



"Subroto Datta" <sdatta@altera.com> schrieb im Newsbeitrag
news:1114636655.106746.211620@f14g2000cwb.googlegroups.com...

Hi Petter,

Chapter 9 of the MAX II handbook explains how to use the ALTUFM
megafunction to add UFM data with mif or hex file. The user has to
recompile if they want to change the hex file data, as this is how you
convert it to POF.

This can be found at
http://www.altera.com/literature/hb/max2/max2_mii51010.pdf
(page 9-34 thru 9-38.)

Hope this helps.
Subroto Datta
Altera Corp.



Petter Gustad wrote:
Is there an easy way to convert a plain ascii file of hex numbers
etc.
into a SOF format or similar in order to program the UFM of the MAX
II?

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Ray Andraka]

Antti Lukats wrote:

BTW, Atmel AT40K are claimed to be pin-compatible to xilinx XC4K,
but if you can redesign to recent lowcost FPGA then thats possible
preferable.

antti




Pin compatible only in that the pin definitions matched so that you

could concievably put an equivalent design (different bit stream) in the
Atmel part and use it in a xilinx socket. That is where the
similarities ended. The AT40K has a completely different internal
architecture, and most notably does not have any fast carry logic, and
instead of using LUTs for memory have small 32 bit memories for every
couple of logic cells. If you compare architectures, you'll find that
many Xilinx designs will not fit in the resources supplied in the
"equivalent" Atmel part.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Antti Lukats]

Hi Ray,

yes sure I forgot to mention those details.. its totally different thing
internally.
I was just looking at AT94 and AT40 in order to see if I could maybe have
an application for them, the AT94S10 is $19, its true single chip, has
onchip
25 MIPS RISC and can do dynamic reconfiguration. could be used as
replacement (way more flexible) for SystemACE, that where my interest was.
I still have the very secret document about all the bitstream cell bit info
of
the AT40K so still having ideas doing something that really benefits from
dynamic reconfiguration.

Antti


"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
newsoTbe.50$c83.49@lakeread07...

Antti Lukats wrote:

BTW, Atmel AT40K are claimed to be pin-compatible to xilinx XC4K,
but if you can redesign to recent lowcost FPGA then thats possible
preferable.

antti




Pin compatible only in that the pin definitions matched so that you
could concievably put an equivalent design (different bit stream) in the
Atmel part and use it in a xilinx socket. That is where the
similarities ended. The AT40K has a completely different internal
architecture, and most notably does not have any fast carry logic, and
instead of using LUTs for memory have small 32 bit memories for every
couple of logic cells. If you compare architectures, you'll find that
many Xilinx designs will not fit in the resources supplied in the
"equivalent" Atmel part.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Antony]

Duane Clark ha scritto:

By the way, I should mention one more subtle gotcha. The addresses to
the DIMM need to be reversed, because this determines the DDR/DIMM
commands.

Modified the core, but it didn't work... Unfortunately I discovered that
I hadn't the Service Pack installed, so I had to modify manually the
cores (two of them were older than the ones you used for the diff
files...) and had to do some fine tuning... Tomorrow I'll ask to install
the SP 2 on the lab's machine and check with it installed what I can do.

Anyway, thanks for the help!!!

 

[info_]

Thanks for the follow-up.

One of the "valid" reasons I didn't give details about was that these
chips are running at an ambient temperature of 175 degrees Celsius
This customer won't qualify a new family every now and then
as you can surely guess ;-)

Any semi wiling to qualify the latest chips at this temp ?

 

[Ljubisa Bajic]

Hi Austin,

I also tried using the power estimation tool on Xilinx' web site and
ran into pretty much the same results as Paul described earlier in the
thread.
Specifically, I tried >10 different configurations with a V4 LX80
part; varying the following parameters (all "utilization" parameters
were between low and medium values, Vccint was varied between 1.1V and
1.3V):

Vccint
CLB Usage
FIFO Usage
RAM usage
DSP block usage
Amount of air flow

What I found is that for every "configuration" I tried the ratio of
Vccint_new/Vccint_old was almost exactly equal (equal at least to the
precision of a mW) to the ratio of Power_new/Power_old (where the
Vccint
values are between 1.1 and 1.3 and Power_{new,old} refers to only the
power
reported as dissipated on the Vccint rail.

Could you please shed some light on the behaviour described above? Are
Paul and I simply doing something completely wrong with the power
estimator?

In order to avoid coming off as simple minded, I will refrain from any
speculation on my side.

Thanks,
Ljubisa Bajic
ATI Technologies


Austin Lesea <austin@xilinx.com> wrote in message news:<d4mfgm$7d53@cliff.xsj.xilinx.com>...

Paul,

It does change (with V), as is shown by the predictor.

And yes, we do use Vccint. We also use Vccaux.

Nothing is ever as simple as it first seems.

The devil is in the details, and telling you how it works would just
allow you to copy it, and improve your own estimator.

Austin

Paul Leventis wrote:

Hi Austin,


Since we power the pass gates from Vccaux through a band gap

referenced

supply for the entire interconnect, many simple minded formulas that

you

may come up with will not apply.


Excuse my simple-mindedness, but I am having trouble understanding.
You have no circuitry powered off the actual VccInt rail? Your routing
buffers, LUTs, DSPs, RAMs and other hard-IP blocks do not use VccInt
but rather run off the regulated VccAux-driven supply?

Yes, I will concur that simple rules-of-thumb are never quite true in
practice, and depend on exact circuits used. But are you suggesting
that your supply current doesn't change with voltage? At all?

Paul Leventis
Altera Corp.