EDK : FSL macros defined by Xilinx are wrong

[info_]

Synplify projects are in fact Tcl scripts.
So you might write a MIF parser in Tcl (easy) and write down a
synthesizable vhdl Rom table (entity). I did this in C for a DDFS.
Probably free on my website.

Bert Cuzeau

 

[Jim George]

v wrote:

What if you route an IBUFG input pin to a regular BUF?...will the tools
still treat it as global clock?

No, this net will be routed on local resources. The IBUFGs feed a
routing box near the top center and bottom center of the chip, these
have connections to the local resources (HEX lines, etc) and these get
used. I accidentally ended up doing this once, saw the problem in FPGA
editor, then fixed it. If you want to get a clock out of the FPGA,
configure the output buffer as a DDR Flip Flop, tie D0 high, D1 low,
give your clock to C0 and an inverted version to C1.

See XAPP462 for details, it's a very good document on the capabilities
of the DCM.

-Jim

 

[Brendan Cullen]

Hi,

Marc makes some excellent points about the provision of information.

If you're targeting V4 then you are targeting one of our SX or LX devices
and you are using 7.1.01i.

If you provide accurate switching information (and an important element of
that is simulation information from a VCD or XAD file) then your
estimation for V4 devices should be within 50% of the actual measurement.
If you run a series of designs you can expect your average design error to
be within 25%.

Feel free to send any other queries my way,

Brendan
Xilinx Power Tools



parity wrote:

Hello,

i'm from germany and just registered to this forum. Hello to everybody
out there.

I'm working on very small FPGA Designs which are size-comparable
(about 4-40 Look-up-Tables on a VIRTEX FPGA) to 4 Bit-adders and 4
Bit-multipliers. I use them just for testing some things. The problem
is that I use XPower to calculate the power consumption of the designs
and the power values are not what i expected.

I have a testbench, an input stimuli and the placed and routed design.
Whenever i put stimulis to the design it delivers (like expected) the
"mW" values. But if i change the stimuli to other ones, which are
nearly the same, the power consumption raises to the double or stays
the same. (after subtracting the quiescent part). There's (in most
cases) nothing between them.

Does anybody know this problem? Have I reached the smallest possible
XPower value, or what is it?

Oh, and does anybody know, how accurate XPower should be. Is there a
chance to get some information about it?

Thanks for all answers,

parity

 

[Rob Warnock]

Ulf Samuelsson <ulf@NOSPAMatmel.com> wrote:
+---------------
| I happen to think that the ARM Thumb patent is a load of rubbish.
+---------------

Yup. See my previous posting about the LINC/LINC-8/PDP-12 machines...


-Rob

-----
Rob Warnock <rpw3@rpw3.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607

 

[digi]

At first you imlement your Core to IPIF User Logic, then you must
reimport you Core with Creat/Import Wizard. And by reimporting you
must take no PAO file but a PRJ File from your IPIF Topdesign!

 

[Joe Pfeiffer]

nmm1@cus.cam.ac.uk (Nick Maclaren) writes:

In article <1bhdikbazp.fsf@cs.nmsu.edu>,
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
|> "Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes:
|
|> > The basis of the patent is the "ARM Ltd discovery" that less code is better
|> > than more code.
|> > Code compression for RISC is mentioned already in the original RISC paper by
|> > Katevenis.
|
|> Original RISC paper by Katevenis? While I was able to find a 1983
|> paper by him, near as I can tell the original RISC paper is still the
|> one by Patterson amd Ditzel in 1980.

There were papers containing much of the technical content in the
1960s.

Of course. But the one that tied it all together in a single,
coherent bundle was Patterson and Ditzel.
--
Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605
Department of Computer Science FAX -- (505) 646-1002
New Mexico State University http://www.cs.nmsu.edu/~pfeiffer

 

[Dave Hansen]

On Wed, 06 Apr 2005 06:21:44 GMT, Tauno Voipio
<tauno.voipio@iki.fi.NOSPAM.invalid> wrote:

[...]

There is a case of this years ago: The Zilog Z80
used the Intel 8080/8085 instruction set and extended
it, but used different mnemonics for nearly all
instructions.

Similar case with the NEC V20/Intel 8088

Regards,

-=Dave
--
Change is inevitable, progress is not.

 

[Ray Andraka]

Brendan Cullen wrote:

Hi,


If you're targeting V4 then you are targeting one of our SX or LX devices
and you are using 7.1.01i.



not necessarily. I'm targeting an SX55 and using 6.3sp3.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

Ulf Samuelsson wrote:

You protect an ISA by patenting some special thing which is required
to
implement the ISA.
I happen to think that the ARM Thumb patent is a load of rubbish.

The basis of the patent is the "ARM Ltd discovery" that less code is
better
than more code.
Code compression for RISC is mentioned already in the original RISC
paper by
Katevenis.

I note that the Itanium ISA is covered by a patent on its unique method
of explicitly indicating parallelism. The more conventional way of
indicating parallelism, by a 'parallel' bit on each instruction, was
used on TI signal processing chips.

I'm sad to hear that there is a patent on the ARM Thumb instruction set
that extends to the general principle, because something like it is
what the PowerPC architecture desperately needs - so that people can
use it the way IBM wants, without compromising the architecture.

John Savard

 

Tauno Voipio wrote:

There is a case of this years ago: The Zilog Z80
used the Intel 8080/8085 instruction set and extended
it, but used different mnemonics for nearly all
instructions.

Note that this was because Intel *copyrighted* the mnemonics, rather
than trademarking them, however.

John Savard

 

[Tauno Voipio]

Dave Hansen wrote:

On Wed, 06 Apr 2005 06:21:44 GMT, Tauno Voipio
tauno.voipio@iki.fi.NOSPAM.invalid> wrote:

[...]

There is a case of this years ago: The Zilog Z80
used the Intel 8080/8085 instruction set and extended
it, but used different mnemonics for nearly all
instructions.


Similar case with the NEC V20/Intel 8088

Yep - the V20 contained the 8080 instruction set as well.

I wrote a CP/M handler running on a PC/XT with V20.

--

Tauno Voipio
tauno voipio (at) iki fi

 

[Sander Vesik]

Tobias Weingartner <weingart@cs.ualberta.ca> wrote:

In article <qhpsxanzti.fsf@ruckus.brouhaha.com>, Eric Smith wrote:

But if there isn't a patent on an architecture, you don't need a license
to implement it. The purpose of the license is to grant you a right that
was taken away from the patent. If there's no patent, you haven't been
denied the right.

No, you are wrong. I do not need a patent on my IP in order for me to
license it to you. It's called copyright.

so precicely what do you claim is copyrightable in an ISA? instruction
names? thats not even handled by the implementation.

--
Sander

+++ Out of cheese error +++

 

[Eric Smith]

"JJ" <johnjakson@yahoo.com> writes:

If some processor that is not any way MIPs like can otherwise perform a
register ld/st for a word on any byte boundary is that a problem, or
only if the rest of it is MIPs like too.

It's not the unaligned load/store per se that is patented; many processors
have done that.

What MIPS invented and patented was the idea that instead of having the
hardware deal with unaligned bus accesses, they require software to
issue *two* instructions to do an unaligned access. One does the
"left part" and one does the "right part" of the word.

The normal MIPS load and store instructions require alignment just as
on most other RISC processors.

 

[Eric Smith]

Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:

Of course. But the one that tied it all together in a single,
coherent bundle was Patterson and Ditzel.

Are you asserting that the IBM 801 papers didn't tie it all together
in a single coherent bundle?

 

[Eric Smith]

mojaveg@mojaveg.iwvisp.com (Everett M. Greene) writes:

It always puzzled me as to how Intel could get a copyright
on instruction mnemonics. This struck me as being akin to
someone copyrighting the Latin alphabet. An AND, is an
AND, is an AND,...

AFAIK the validity of the copyright on the mnemonics was never tested in
court. It seems unlikely that it would be upheld.

 

[Everett M. Greene]

Tauno Voipio <tauno.voipio@iki.fi.NOSPAM.invalid> writes:

Dan Koren wrote:
"Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote

Are ISA covered by patents or trademarks? Is it allowed to develop a
processor core for a popular ISA as long as no reference is made to any of
the original company trademarks? Many thanks for your comments.

Trademarks cover only product *names*.

ISA names can indeed be trademarked,
hower that would not prevent anyone
from copying/using the architecture.

It would only prevent them from
selling/promoting/advertising it
under the same name as the original.

There is a case of this years ago: The Zilog Z80
used the Intel 8080/8085 instruction set and extended
it, but used different mnemonics for nearly all
instructions.

It always puzzled me as to how Intel could get a copyright
on instruction mnemonics. This struck me as being akin to
someone copyrighting the Latin alphabet. An AND, is an
AND, is an AND,...

 

[Joe Pfeiffer]

Eric Smith <eric@brouhaha.com> writes:

Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
Of course. But the one that tied it all together in a single,
coherent bundle was Patterson and Ditzel.

Are you asserting that the IBM 801 papers didn't tie it all together
in a single coherent bundle?

The earliest 801 paper I'm familiar with was published in 1982. While
the project certainly tied things together in a coherent RISC bundle
before the RISC and MIPS projects (as both Hennessy and Patterson
acknowledge), Patterson and Ditzel is the first publication I'm aware
of that does.
--
Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605
Department of Computer Science FAX -- (505) 646-1002
New Mexico State University http://www.cs.nmsu.edu/~pfeiffer

 

[JJ]

Thanks for clarification, thats okay then!

Perhaps it worth inventing/patenting same idea for exactly 3 & 4 & 5
instructions too

johnjakson at usa dot com
transputer2 at yahoo dot com

 

[David]

On Wed, 06 Apr 2005 09:23:30 -0700, jsavard wrote:

I'm sad to hear that there is a patent on the ARM Thumb instruction set
that extends to the general principle, because something like it is
what the PowerPC architecture desperately needs - so that people can
use it the way IBM wants, without compromising the architecture.

John Savard

There are Freescale (formerly Motorola) PowerPC microcontrollers with code
compression (look for the MPC562 on the Freescale website, for example).
The do not use an alternative instruction set like the Thumb - instead, it
is a more dynamic compression. Software utilities compress your
executable and generate tables which you must load into the decompressor's
lookup table ram on startup. The decompressor is part of the instruction
pre-fetch burst controller, which passes fully decompressed instructions
on to the main cpu core. This makes it more flexibile than the Thumb
technique, and you get the full power of the core rather than a subset,
but it's more of a hassle to configure (and probably awkward for debugging).

 

[Jon Beniston]

Quiet Desperation <nospam@nospam.com> wrote in message news:<060420051752320025%nospam@nospam.com>...

Any chance of there ever being an FPGA where one or more of the
SelectRAM blocks is nonvolatile?

I design a lot of stuff that is programmable and reconfigurable beyond
the FPGAs. I commonly need to store the setting of digital delay chips
and switch settings and other control lines so that a unit powers up
with everything in the state desired by the end user.

Currently I use little automotive serial EEPROMs, but, dang but it'd be
nice to have a little EEPROM inside an FPGA. Just one 18Kbit block
would do wonders.

NvM in a 90nm std CMOS process is not easy to do. There's only one
solution I know of (Virage's NOVeA), but 18Kbit would be a large chunk
of silicon. Embedded FLASH in 90nm is years off, and by then, FPGAs
will be 65 / 45nm. An MCP would be nice, but this isn't really a huge
advantage over having an external memory as FPGAs have so many I/Os.

Can't you write your configuration data into your FPGAs configuration
PROM?

Cheers,
Jon