EDK : FSL macros defined by Xilinx are wrong

given a complete lack of eveidence for this "capacity-induced failure",
it seems more probable that the failures were due to ESD,
contamination, miswiring, etc.
 
On 22 May 2006 17:25:33 -0700, the renowned "Nigel"
<neilchamberlain@hotmail.com> wrote:

good point. we havent measured the continuity in both directions.

the short is real (at least in one direction - from Vcc to ground, less
than an ohm)

the cause is, as yet, TBD.
Click to expand...
How much fault current is the supply capable of?


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
 
the supply is capable of approx 3A fault current. however, the limit
was set to a little over 1A when the fault was first detected.
 
Nigel wrote:
the supply is capable of approx 3A fault current. however, the limit
was set to a little over 1A when the fault was first detected.
Click to expand...
Was the chip hot after the failure? If not, latchup can be ruled out.
The 1 A it may have had may or may not suffice to fry it if
latchup has occured (for whatever reason). Some large peak
current discharging the power filtering capacitors can have helped,
do you have an idea about that (how much capacitance there, that is)?

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
 
Falk Salewski wrote:

If I implement a function in an FPGA twice and do all these measures to make
sure that there are no functional interactions between theese two
implementations: What makes this implementation worse comparing to an
implementation based on two separate devices? The single power supply? If
this single piece of silizium is "faulty"? anything else?

Regards
Falk S.
Click to expand...
Yes,
both circuits share the same configuration circuitry. A fault in the
configuration logic will render the whole device unprogrammable.
 
Hello

I just finished the test with the UC-II gigabit ethernet design for the ML403 board. Unfortunately, the design is very slow for high speed transmission. The main problem is the little quantity of memory for the code of the TCP/IP stack, so you need to optimize in space, and the instruction speed is decreased.

But for slow applications this is a great solution, because it's simply and easy to learn.

The next step? Hardware processing...

Regards
 
Antti a écrit :

the USB chip on the Xilinx s3e starterboard is the same as on the
opalkelly board I think,
Thanks for that. It would have to be the USB interface on the censored
page. Is the usb eeprom reprogrammable on-board?
the usb micro is cypress fx2
Click to expand...
Are you 100% sure of that (the only FX2 they mention in the datasheet
is an extension connector) ?
If yes, how is the FIFO port of the FX2 connected to the FPGA ?

Goodbye,
Stéphane.
 
"Stéphane Goujet" <stephane.goujet@pp.invalid> schrieb im Newsbeitrag
news:5RQgg.38$VW4.19@read3.inet.fi...
Antti a écrit :

the USB chip on the Xilinx s3e starterboard is the same as on the
opalkelly board I think,
Thanks for that. It would have to be the USB interface on the censored
page. Is the usb eeprom reprogrammable on-board?
the usb micro is cypress fx2

Are you 100% sure of that (the only FX2 they mention in the datasheet is
an extension connector) ?
If yes, how is the FIFO port of the FX2 connected to the FPGA ?

Goodbye,
Stéphane.
Click to expand...
pretty sure, yes the datasheet refers to FX2 (as extension connector)

but the board has on on-board embedded usb platfrom cable, and that includes
the cypress FX2 usb micro
this pages are left out from schematics and are covered up with ink on PCB
prints

Antti
 
Antti Lukats a écrit :

the usb micro is cypress fx2
Are you 100% sure of that (the only FX2 they mention in the datasheet is
an extension connector) ?
If yes, how is the FIFO port of the FX2 connected to the FPGA ?
pretty sure, yes the datasheet refers to FX2 (as extension connector)
but the board has on on-board embedded usb platfrom cable, and that includes
the cypress FX2 usb micro
Click to expand...
But perhaps just the pins to program the FPGA and the flash memory
are connected, and the USB port cannot be used to transfer personal data
through the FIFO of the FX2 microcontroller. It seems to be so, because
else they would probably mention that this board has a USB port that can
transfer high-speed USB data, and they do not. They just say that the
board can be programmed through USB.

this pages are left out from schematics and are covered up with ink on PCB
prints
Click to expand...
Yes, I saw that... :-(

Goodbye,
Stéphane.
 
Stéphane Goujet schrieb:

Antti Lukats a écrit :

the usb micro is cypress fx2
Are you 100% sure of that (the only FX2 they mention in the datasheet is
an extension connector) ?
If yes, how is the FIFO port of the FX2 connected to the FPGA ?
pretty sure, yes the datasheet refers to FX2 (as extension connector)
but the board has on on-board embedded usb platfrom cable, and that includes
the cypress FX2 usb micro

But perhaps just the pins to program the FPGA and the flash memory
are connected, and the USB port cannot be used to transfer personal data
through the FIFO of the FX2 microcontroller. It seems to be so, because
else they would probably mention that this board has a USB port that can
transfer high-speed USB data, and they do not. They just say that the
board can be programmed through USB.

this pages are left out from schematics and are covered up with ink on PCB
prints

Yes, I saw that... :-(

Goodbye,
Stéphane.
Click to expand...
well they dont provide and user communication over the USB controller,
but sure it
would be possible, maybe not with the max transfer rate, but still
possible

Antti
 
Stéphane Goujet schrieb:

Antti a écrit :

the USB chip on the Xilinx s3e starterboard is the same as on the
opalkelly board I think,
Thanks for that. It would have to be the USB interface on the censored
page. Is the usb eeprom reprogrammable on-board?
the usb micro is cypress fx2

Are you 100% sure of that (the only FX2 they mention in the datasheet
is an extension connector) ?
If yes, how is the FIFO port of the FX2 connected to the FPGA ?

Goodbye,
Stéphane.
I did not say the FIFO port is connected - I said that the USB
Click to expand...
controller
can be used for user defined protocols, also transferring user data

Antti
 
Forgot the message :)

Anyone know of a decent FPGA/Prom Jtag programmer for Xilinx FPGAs?

Thanks,

Colin

"Colin Hankins" <colinhankins@cox.net> wrote in message
news:id4hg.93001$TK1.16745@fed1read06...
 
Antti a écrit :

the usb micro is cypress fx2
I did not say the FIFO port is connected - I said that the USB
controller can be used for user defined protocols, also
transferring user data
well they dont provide and user communication over the USB
controller, but sure it would be possible, maybe not with the max
transfer rate, but still possible
Click to expand...
OK, well, it is a pity (for me, I suppose those pins are more useful
somewhere else for other people).
I guess I have to look towards boards like Orange Tree Tech.'s
ZestSC1, Opal Kelly's XEM3001 or Cesys' USB3FPGA. Only problem is that
they are 2 or 3 or 4 times the price as Xilinx' S3E starter kit without
all the functions this starter kit includes.

Goodbye,
Stéphane.
 
I deffinatelly recommend Platform Cable USB if you willing to give
150$.
Otherwise build or buy Parallel cable III (very low cost).

Cheers, Guru
 
Where can one find a schematic of a parellel port jtag programmer?

"Guru" <ales.gorkic@email.si> skrev i meddelandet
news:1149591274.181317.159500@j55g2000cwa.googlegroups.com...
I deffinatelly recommend Platform Cable USB if you willing to give
150$.
Otherwise build or buy Parallel cable III (very low cost).

Cheers, Guru
Click to expand...
 
Chris Sorenson wrote:
installable package in a shell script? Binary here documents?


Nvidia does the same thing with their binary-only drivers, the binary
is included as part of one giant shell script. Perhaps you could
even modify it if you used an 8-bit clean editor...
Click to expand...
It's a tried and true technique.
See gzexe for another example.

I don't believe there's anything special about RH that caused Xilinx to pick
it other than being "the enterprise Linux".

Heck the "script written for RH" runs just fine under ABI emulation on
FreeBSD.

--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
 
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

GaLaKtIkUs™ wrote:

I wanted to use Icarus but I was confronted to a big problem (as a user
of Xilinx): in the simlation libraries there are specify blocs and
Icarus verilog doesn't support them and there are no shoft term plans
to support them. Great was my deception (as open source enthusiast) but
now I'm obliged to use a commercial simulator.
Click to expand...
It doesn't matter. The specify blocks are ignored and simulation
works just fine. You will not be able to do back-annotated post-
par timing simulations, but functional simulations work just fine.

I (and my day job co-workers) use Icarus Verilog for Xilinx work
all the time.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Stephen Williams wrote:
GaLaKtIkUs™ wrote:
I wanted to use Icarus but I was confronted to a big problem (as a user
of Xilinx): in the simlation libraries there are specify blocs and
Icarus verilog doesn't support them and there are no shoft term plans
to support them. Great was my deception (as open source enthusiast) but
now I'm obliged to use a commercial simulator.


It doesn't matter. The specify blocks are ignored and simulation
works just fine. You will not be able to do back-annotated post-
par timing simulations, but functional simulations work just fine.

I (and my day job co-workers) use Icarus Verilog for Xilinx work
all the time.
Click to expand...
Interesting - can you give some comments on the relative speed /
reliability /size of the present Icarus release ?

-jg
 
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Hash: SHA1

Jim Granville wrote:
Stephen Williams wrote:
GaLaKtIkUs™ wrote:
I wanted to use Icarus but I was confronted to a big problem (as a user
of Xilinx): in the simlation libraries there are specify blocs and
Icarus verilog doesn't support them and there are no shoft term plans
to support them. Great was my deception (as open source enthusiast) but
now I'm obliged to use a commercial simulator.


It doesn't matter. The specify blocks are ignored and simulation
works just fine. You will not be able to do back-annotated post-
par timing simulations, but functional simulations work just fine.

I (and my day job co-workers) use Icarus Verilog for Xilinx work
all the time.

Interesting - can you give some comments on the relative speed /
reliability /size of the present Icarus release ?
Click to expand...
I can say with certainty that a licensed Modelsim simulator is
faster. Others will be able to say how much faster. I do image
processing in a 1/3 full XC2V3000 w/ SDRAMS, and I can simulate
plausible jobs. Sometimes I even do simulations on my 1.3GHz
Powerbook G4:)

Now when you say "present Icarus release", there are the current
snapshots and there is the v0.8 stable branch. The stable branch
is a little faster in some cases, but is not as complete in others.
The stable release is "stable", but the snapshots are getting the
bug fixes and new features.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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