EDK : FSL macros defined by Xilinx are wrong

That, for me, is the primary factor. If a complete failure can be
tolerated, it's generally acceptable to use a single part and replicate
the design - but with safety critical, it's another story. I worked for
a while at a nuclear power plant, and every critical system has at
least one backup, and in some cases, two backups. Clearly, not a
situation where you can tolerate a complete failure gracefully.
Click to expand...
If I implement a function in an FPGA twice and do all these measures to make
sure that there are no functional interactions between theese two
implementations: What makes this implementation worse comparing to an
implementation based on two separate devices? The single power supply? If
this single piece of silizium is "faulty"? anything else?

Regards
Falk S.
 
Didi wrote:
Jim,


Sounds a strange idea - how does one macrocell, know that it's
neighbours are used ?


strange things like that can indeed happen. On the oldest
coolrunner, for which I have written my logic compiler, there
was a possibility to use some more multiplexor paths than
the manufacturers software was using (IIRC it was 40 vs. 36).
I tried it only to discover that when it came to that, the
chip was becoming unstable... so I lowered my limit as well.
Click to expand...
That's rather a different case, even unique :)

Perhaps it is about power distribution, who knows.
Click to expand...
Coolrunners are low power devices - All I could think of was
possibly longer programming times, for more device usage, but
that is also a stretch...

That's why the TIME-LINE of failures is important.

Also, Vcc shorts do not sound like any device-mapping failures, but
do sound like ESD/latchup ....

-jg
Nigel,
the fpga newsgroup should be better for this thread,
Austin or Peter (both highly knowledgeable Xilinx employees)
might be able to give some more info.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

Jim Granville wrote:

Nigel wrote:

has anyone experienced problems when operating Cool Runner (XPLA3)
CPLDs near the capacity of their macrocells? specifically, i have two
devices that have failed independently with hard short circuits to
ground on the 3.3V power supplies. i have heard some anecdotal evidence
that this can happen when too many of the macrocells are used. has
anyone heard of this or seen it documented or reported elsewhere?

Sounds a strange idea - how does one macrocell, know that it's
neighbours are used ?
Check things like ESD ratings, and latchUp ratings.
When did the failures occur ?

-jg
Click to expand...
 
On Sat, 20 May 2006 07:48:18 +1200, in article
<446e20cb@clear.net.nz> no.spam@designtools.co.nz
"Jim Granville" wrote:
Didi wrote:
Jim,
Click to expand...
....

Perhaps it is about power distribution, who knows.

Coolrunners are low power devices - All I could think of was
possibly longer programming times, for more device usage, but
that is also a stretch...

That's why the TIME-LINE of failures is important.

Also, Vcc shorts do not sound like any device-mapping failures, but
do sound like ESD/latchup ....
Click to expand...
Don't rule out manufacturing problems, I remember a short on a CPLD
(which just happened to be a Philips Coolrunner), but our clue was
the short was not permanent. turned out to be a tiny ball of solder
under a PLCC package, careful 'nudging' and heating a few pins in turn
made it melt onto an existing pad only.

Some conductive muck may have got on one batch of boards, that went to one
site as well.


--
Paul Carpenter | paul@pcserviceselectronics.co.uk
<http://www.pcserviceselectronics.co.uk/> PC Services
<http://www.gnuh8.org.uk/> GNU H8 & mailing list info
<http://www.badweb.org.uk/> For those web sites you hate
 
Paul Carpenter wrote:

Coolrunners are low power devices - All I could think of was
possibly longer programming times, for more device usage, but
that is also a stretch...

That's why the TIME-LINE of failures is important.

Also, Vcc shorts do not sound like any device-mapping failures, but
do sound like ESD/latchup ....


Don't rule out manufacturing problems, I remember a short on a CPLD
(which just happened to be a Philips Coolrunner), but our clue was
the short was not permanent. turned out to be a tiny ball of solder
under a PLCC package, careful 'nudging' and heating a few pins in turn
made it melt onto an existing pad only.

Some conductive muck may have got on one batch of boards, that went to one
site as well.
Click to expand...
Good point. Replacement=works, does not always mean the removed device
is faulty, the OP should verify that failure on the removed devices.
I was assuming his description was precise, but you could be right...

-jg
 
the failure has manifested on the removed device. we have delidded the
device and verified the short on the die. however, we have not ruled
out that contamination external to the package may have caused the
failure in the first place.

the vendor claims shorting can happen in devices near capacity. i have
heard of no other examples of this. other modules that have the same
CPLD with the same program have not failed.

bottom line: we suspect ESD damage due to mishandling.

thanks for the responses.
N.
 
Nigel wrote:
the vendor claims shorting can happen in devices near capacity.
Click to expand...
"Vendor" would have to be Xilinx, but I cannot believe that statement.
Filling a low-power CPLD to capacity does not create a Vcc-to-GND short
circuit.
That is not even an urban legend, it's just silly.
Peter Alfke, Xilinx Applications
 
Nigel wrote:

the failure has manifested on the removed device. we have delidded the
device and verified the short on the die. however, we have not ruled
out that contamination external to the package may have caused the
failure in the first place.

the vendor claims shorting can happen in devices near capacity. i have
heard of no other examples of this. other modules that have the same
CPLD with the same program have not failed.

bottom line: we suspect ESD damage due to mishandling.
Click to expand...
Who is the 'vendor' you refer to ?
-jg
 
On 20 May 2006 18:59:40 -0700, the renowned "Peter Alfke"
<alfke@sbcglobal.net> wrote:

Nigel wrote:

the vendor claims shorting can happen in devices near capacity.

"Vendor" would have to be Xilinx, but I cannot believe that statement.
Filling a low-power CPLD to capacity does not create a Vcc-to-GND short
circuit.
That is not even an urban legend, it's just silly.
Peter Alfke, Xilinx Applications
Click to expand...
It could conceivably cause some kind of ground bounce leading to
latchup of the parasitic SCR and thence to death by overheating of the
die if the supply is capable of delivering the amps.

Is the ground and bypass situation on the chip close to ideal? (at
least 4-layer board with gnd and Vdd planes and lots of bypass
capacitance)?

I have a different kind of part (micro) from a different vendor that
manages to tell the difference between what should be a simple CMOS
input (no pullups or anything like that) grounded and the same input
grounded through a 1.2K resistor.


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
 
Spehro Pefhany wrote:
On 20 May 2006 18:59:40 -0700, the renowned "Peter Alfke"
alfke@sbcglobal.net> wrote:


Nigel wrote:

the vendor claims shorting can happen in devices near capacity.

"Vendor" would have to be Xilinx, but I cannot believe that statement.
Filling a low-power CPLD to capacity does not create a Vcc-to-GND short
circuit.
That is not even an urban legend, it's just silly.
Peter Alfke, Xilinx Applications


It could conceivably cause some kind of ground bounce leading to
latchup of the parasitic SCR and thence to death by overheating of the
die if the supply is capable of delivering the amps.

Is the ground and bypass situation on the chip close to ideal? (at
least 4-layer board with gnd and Vdd planes and lots of bypass
capacitance)?
Click to expand...
Latch-up is mainly a current injection effect, and can be reduced if
the lead-connections to the outside world have series impedance, or
series impedance + external clamps, in severe cases.
In devices with internal Vcc-IO clamp diodes, you do need to watch
lifting Vcc effects, from long duration/significant values clamp
currents, and power supplies that do not sink (most do not).
Low power CPLDs need attention in this, because their own load
currents are very low.

On the PLDs we've tried to create LatchUp on, -ve pulse latchup was
easier than +ve ( but still >> 100mA) and +ve latchup needed quite
massive over-voltages to get enough current (higher clamp impedences)
- so in that direction, pin failures are likely to happen at the same
time, or first.

-jg
 
Spehro Pefhany schrieb:

It could conceivably cause some kind of ground bounce leading to
latchup of the parasitic SCR and thence to death by overheating of the
die if the supply is capable of delivering the amps.
Click to expand...
Could also be a power-up sequence issue. When different voltages are
onboard and another IC connected to the CPLD is power up much ealier and
drives the (still unpowered) IOs of the CPLD, latchup can happen too.

Is the ground and bypass situation on the chip close to ideal? (at
least 4-layer board with gnd and Vdd planes and lots of bypass
capacitance)?
Click to expand...
Naaaaa, I wouldnt like to develop paranoia on this. I think a double
layer for this CPLD is just fine, with some 100nF placed close to the CPLD.

Regards
Falk
 
On Sun, 21 May 2006 10:53:41 +0200, the renowned Falk Brunner
<Falk.Brunner@gmx.de> wrote:

Spehro Pefhany schrieb:

It could conceivably cause some kind of ground bounce leading to
latchup of the parasitic SCR and thence to death by overheating of the
die if the supply is capable of delivering the amps.
Click to expand...
The reasoning here is that a more fully utilized CPLD has more nodes
switching very quickly and virtually the same instant, which in turn
means more volts across fixed stray layout, package and die
inductance.

Could also be a power-up sequence issue. When different voltages are
onboard and another IC connected to the CPLD is power up much ealier and
drives the (still unpowered) IOs of the CPLD, latchup can happen too.
Click to expand...
Sure, however I fail to see how power sequencing issues would lead to
different results depending on the percentage of the CPLD which is
used.

Is the ground and bypass situation on the chip close to ideal? (at
least 4-layer board with gnd and Vdd planes and lots of bypass
capacitance)?

Naaaaa, I wouldnt like to develop paranoia on this. I think a double
layer for this CPLD is just fine, with some 100nF placed close to the CPLD.

Regards
Falk
Click to expand...
Maybe, but it's hard to make a marginal layout when full power planes
are employed, even with an dumb-as-a-post autorouter. Single and
double-sided boards offer far richer opportunities in this department.


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
 
Spehro Pefhany schrieb:

The reasoning here is that a more fully utilized CPLD has more nodes
switching very quickly and virtually the same instant, which in turn
means more volts across fixed stray layout, package and die
inductance.
Click to expand...
Right, but this is only a qualitative statement. What matters is
quantity. So how big is the overall inductance? How much does voltage
drop increase between a almost empty and a almost full device?
Answering these question (which is not so easy) may yield the answer,
that there is plenty of margin left. Ind I guess Xilinx did quite alot
of testing with fully utilized devices.

Sure, however I fail to see how power sequencing issues would lead to
different results depending on the percentage of the CPLD which is
used.
Click to expand...
Ask Mr. Murphy ;-) Maybe its just one critical IO that is used or not.

Regrds
Falk
 
On Sunday, in article <4db0j4F19lkfkU1@individual.net>
Falk.Brunner@gmx.de "Falk Brunner" wrote:
Spehro Pefhany schrieb:
Sure, however I fail to see how power sequencing issues would lead to
different results depending on the percentage of the CPLD which is
used.

Ask Mr. Murphy ;-) Maybe its just one critical IO that is used or not.
Click to expand...
If it is true that only boards to one site with same program as other boards
fails, my money is on environmental or manufacturing.


I.E. something on the site is different to screw things up - ESD, other
damage to boards, miswiring, latchup or other screw ups because
of sequencing of external events.

Manufacturing caused those boards to have something wrong with that
batch.

All of which could still be a marginal issue in the design, that site
ensures happens.

--
Paul Carpenter | paul@pcserviceselectronics.co.uk
<http://www.pcserviceselectronics.co.uk/> PC Services
<http://www.gnuh8.org.uk/> GNU H8 & mailing list info
<http://www.badweb.org.uk/> For those web sites you hate
 
the vendor (i cant reveal who that is) is using the CoolRunner in a
design.
it is not Xilinx.
N.
 
When you say short,: how short is short?
Measure the I/V characteristic for both polarities.
That might give youa hint whether it is "ohmic" or whether a diode is
involves.
I still maintain that your mystery vendor is imagining things.( I meant
ro write something not fit for this newsgroup...)
Peter Alfke
 
Nigel wrote:
cannot say.
vendor is not Xilinx.
Click to expand...
Can you clarify 'vendor'
are you :

a) buying devices from this company [= distributor]
b) buying completed PCBs from this company
c) do you really mean customer - they buy boards from you, to sell/install ?

-jg
 
b) sort of - we are buying a box from the vendor that has a PCB in it
that has the cool runner on it.
 
good point. we havent measured the continuity in both directions.

the short is real (at least in one direction - from Vcc to ground, less
than an ohm)

the cause is, as yet, TBD.
 
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