EDK : FSL macros defined by Xilinx are wrong

[freechip]

"freechip" <freechip@hotmail.fr> wrote in message
news:VqSdnSn0Kpv2YtXZRVn_vA@giganews.com...

Hi,
I am working on a 10 Gb Ethernet project (deep packet inspection) and
need
to implement CAM in my FPGA. I am using a Stratix GX and I don't think
I
can use CAM (internal or external) in the stratix GX Dev Board.

Let me know your thoughts about that.

Thanks a lot.

How big a (Ternary?)CAM do you need?

Hi,
I don't yet.
Do you think it is possible with Altera products?
Have a good day.

 

[ALuPin@web.de]

Hi freechip,

yes I think it is possible to build a CAM
around Altera RAM blocks.

How big is the CAM ? After how many clock cycles
do you need a hit ?

Rgds
André

 

[freechip]

Hi freechip,

yes I think it is possible to build a CAM
around Altera RAM blocks.

How big is the CAM ? After how many clock cycles
do you need a hit ?

Rgds
Andr=E9

Hi Andr,
Actually, I am in the research phase and I really don't know how big is
the cam. I just wanted to know, to compare to Xilinx Family, if it was
poosible to use cam with Altera product. For my project (deep packet
inspection), the use of the cam is necessary.
If you can tell me how can a build a cam around Altera RAM block (and the
max. of the cam without my answers to your questions), I will be very
pleased.

Thanks.

 

[John_H]

How big a (Ternary?)CAM do you need?


freechip wrote:

Hi,
I don't yet.
Do you think it is possible with Altera products?
Have a good day.

It's possible to build teeny, tiny CAMs. The information Austin pointed
out gives you an idea of what you can accomplish with FPGA resources
that can apply to all FPGAs, not just Xilinx.

If you need a few entries, you might be okay. If you need small
entries, you may be able to do many more.

Read that documentation and you'll get a feel for the limits you're
faced with.

Personally, I'd love a 4kx20 CAM but I know there's no way to do it in
an FPGA>

 

[radarman]

Trust me, it is more complicated than that, but there are plenty of
both legit and questionable reasons for going with external buffers.

For one, we are typically driving very long cable harnesses or large
backplanes with lots of fan-out. While an FPGA pin might be able to do
it, we are guaranteed performance with the external parts. There is
also the fact that a technician can reasonably replace, or probe, a
buffer chip - while a BGA repair requires a trip back to the factory.
Then, there is debug and integration. Our integration and test cycles
are already too short to allow for a two-week trip back to the factory
for rework.

Also, even at just 5%, the buffers are cheaper.

 

[Andy]

If I'm not mistaken, you have the option of determining whether the
"calibration" works once at configuration, or continuously during/after
configuration. Continuous calibration compensates for
temperature/voltage variances during operation, but other than that, it
has no real advantages, and if the board is quieter at configuration,
it might be helpful to select calibration at config only. IIRC,
one-time calibration uses less power too.

If the calibration process is reasonably slow, is it possible to use a
cap in parallel with the DCI resistor to help lower the AC impedance,
and therefore reduce noise? (assuming noise was an issue in the first
place)

In any case, I would not place DCI resistors close to the FPGA at the
expense of bypass cap placement near the FPGA.

Andy

 

[Austin Lesea]

Andy,

Do not place a cap in parallel with the DCI resistor.

If you do not need continuous calibration, then by setting it to
calibrate once, you would need not be concerned about any noise.

Austin


Andy wrote:

If I'm not mistaken, you have the option of determining whether the
"calibration" works once at configuration, or continuously during/after
configuration. Continuous calibration compensates for
temperature/voltage variances during operation, but other than that, it
has no real advantages, and if the board is quieter at configuration,
it might be helpful to select calibration at config only. IIRC,
one-time calibration uses less power too.

If the calibration process is reasonably slow, is it possible to use a
cap in parallel with the DCI resistor to help lower the AC impedance,
and therefore reduce noise? (assuming noise was an issue in the first
place)

In any case, I would not place DCI resistors close to the FPGA at the
expense of bypass cap placement near the FPGA.

Andy

 

[Mike Treseler]

John_H wrote:

It's possible to build teeny, tiny CAMs. The information Austin pointed
out gives you an idea of what you can accomplish with FPGA resources
that can apply to all FPGAs, not just Xilinx.

If you need a few entries, you might be okay. If you need small
entries, you may be able to do many more.

However, if you plan decode 32 bit or 128 bit IP addresses,
an FPGA solution will likely cost just as much and not
work quite as well as a real CAM.

-- Mike Treseler

 

[John_H]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:4b4hneFvg226U1@individual.net...

However, if you plan decode 32 bit or 128 bit IP addresses,
an FPGA solution will likely cost just as much and not
work quite as well as a real CAM.

-- Mike Treseler

But if each 128-bit IP address only needs 4 slices and the number of IP
addresses is rather limited, the cost can be much better than a real CAM.

 

lecroy7200@chek.com wrote:

It appears that the Stratix II is not going to be fast enough for the
first stage. The primary problem is the lack of being able to support
a synchronous parallel bus. Looking in the October 2005 Stratix II GX
handbook, the fastest reference clock appears to be 622MHz, far below
where I want to run at. I could run a slower clock, use the SERDES to
multiply it up and resync the data and expand it out as you suggest,
but this really does not make a lot of sense. The clock already has
phase noise under 5pS rms (from testing) and the data would be matched
going to the device. I tried the SERDES approach you mentioned with
the Quartus tools using the Stratix II as a target device (even though
we have a full license for Quartus the tool requires TalkBack spyware
when targeting a GX device) and it seems to work. I tried to set the
clock to the frequency I am interested in and the tool barks back with
an error. I then tried a very simple approach of just using clocked
register but no luck.

I have seen a few Virtex 4 designs now that directly run a parallel bus
at the speeds I am interested in. I am a bit gun shy after all the
problems we have seen with Xilinx over the years, but they seem to be a
better fit for this application.

If you have any other ideas, I would be interested in hearing them.

You might want to take a look at the Lattice SC device its PURESPEED IO
has 2 Gbps throughput per differential I/O pair.
http://www.latticesemi.com/products/fpga/sc/index.cfm

 

[Cristian CIRESSAN]

Hello,

I was looking at a similar issue recently.

The problem is that bluetooth dongles are SLAVE devices -- or in the USB
terminology, simply USB devices.
They are supposed to work under the control of a USB host (controller),
which is
ussualy a PC. The USB host has to perform USB bus enumeration and probably
other complex tasks.
This means your FPGA has to perform the tasks of a USB host ...
(see USB Complete 3rd edition, Jan Axelson)
Also note that the bluetooth dongle is supposed to be powered-up by the
power lines (5V)
available on the USB interface ...

Finally, the bluetooth protocol is quite complex and implementing the
bluetooth stack is not
trivial. You may want to take a look at http://www.bluez.org/ to get an
idea.

There are USB controllers that implement the OTG (On The Go) supplement to
USB. They allow
devices to comunicate with other devices -- that is, allow devices to work
as hosts.
(see http://www.usb.org/developers/onthego/)
Check the datasheets for Philips ISP1362, TransDimension TD242LP, Cypress
CY7C67200EZ-OTG

My advice to you is to use a eb100-SER (http://www.a7eng.com) module. It has
the full bluetooth stack
implemented in firmware with a serial profile available on power-up and they
say 230kb/s bandwidth.
You connect to this module over a serial UART (easy to implement in an
FPGA).
It's simple to use and it worked for me ...

According to me you face a nice project but a huge one most probably...

Good luck and hope this helps.
Cristian

 

[Guru]

Yes it is true, FIFOs can be expanded. The only problem is that the
UCII is not XPS conmpatible design. Modifcations should be done
manually in ISE with no guarantee that the modified design will work.

Regards, Guru

 

[freechip]

Thanks a lot for your answers.
Actually, I can not tell you more about the size of the CAM.
You are talking about the size but did you implement cam in Altera
(Stratix?) because I didn't see it was possible to put cam in Stratix in
Altera's website.
Have a nice day.

Freechip

 

[John_H]

freechip wrote:

Thanks a lot for your answers.
Actually, I can not tell you more about the size of the CAM.
You are talking about the size but did you implement cam in Altera
(Stratix?) because I didn't see it was possible to put cam in Stratix in
Altera's website.
Have a nice day.

Freechip

Right, right. My apologies. I'm just so used to having embedded
LUT-style memories available that I have trouble making the mindset
switch to Altera. In Altera, CAMs suck (except maybe for way back in
the 20K days).

You can still use the embedded memories to build up a CAM in segments
for a small number of entries. Using the 4k memories arranged as
256x16, you could build 16 CAMs in 8-bit segments. 16 CAM entries of
128 bits would take 16 4k RAM blocks and qty 16, 16-wide cascades to
indicate a byte match for all 16 memories for one CAM entry.

So it can be done but with significantly more resources than the 64
slices needed in an SRL or single-port LUT-RAM device.

 

[Brian Drummond]

On 15 Apr 2006 18:39:28 -0700, "Peter Alfke" <alfke@sbcglobal.net>
wrote:

Well, I'll try another attack on our demonstrated stupidity.
I have screamed and hollered for almost a year, and sent e-mails up the
ladder, up to one step below the very top.
Maybe I have to go one stop higher.
Steve Knapp and I are very frustrated about this situation.
Obviously, our company could do much better...
Peter Alfke, from home

I'm glad you see it this way.

Further ammunition, should you need it...

Perhaps those who made the decisions based them on the quality of
distributor service visible to themselves, i.e. in the USA. Which is
fine if Xilinx don't want to be a global company.

Worldwide, things may not be quite so good; a multi-national distributor
like Avnet insists you (i.e. the customer) deal with their national
division, who operate to nationally accepted standards. Which, in the
case of the UK, means a quality of service somewhere between Fawlty
Towers and the Dead Parrot sketch.

Now I don't want to attack the idea of local distribution, and happily
use it where I can. But (for just one real example) having been quoted a
seven week lead time for a critical component, is it better to wait
patiently with a stalled project, or order it online (ex-stock!) and
continue working?

- Brian

 

[Gabor]

Allan wrote:

Nope, that didn't do it either. I've tried some iterations of this
theme with no success. Where would I find the libraries you mentioned
to take a look at?

%Xilinx%\verilog\src\unisims\RAMB16_S36_S36.v

 

[vssumesh]

One main doubt,
why
assign out = in[ind];
is possible but
assign out[ind] = in; is not possible
Because of this i think demuxing can only be done with FFs or latches
created in a behavioural code. Or is there any other method ????
but
always @(*)
out[ind] = in;
is creating all the logic needed for the demuxing only the storage is
to be avoided How can we extract the combinatorial logic part?

 

[Aurelian Lazarut]

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Aurash

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[Ron]

simon.stockton@baesystems.com wrote:

... I want to clock data into an entity on the falling edge of a
clock and clock data out of an entity on the rising edge of the same
clock.

I don't know about VHDL, butt something like this in Verilog would
probably do the trick:

module xyz(in, out)
input in;
output out;
reg temp;

always @(negedge clock)
temp<= in; // could be combinatorial logic here also

always @(posedge clock)
out<= temp; // could be combinatorial logic here also

endmodule