EDK : FSL macros defined by Xilinx are wrong

[Nico Coesel]

lm317t <lm317t@gmail.com> wrote:

For behavioral sim you could go with a brand agnostic tool like ghdl
and iverilog are both free, and I've used them sucessfully for simple
to quite large designs. I find the Xilinx and Altera tools to be too
slow and cumbersome, but I haven't compared those sim tools to ghdl or
iverilog.

Interesting. Would it be possible to do a functional simulation based
on the post-place & route VHDL file generated by ISE with ghdl?

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[Nico Coesel]

lm317t <lm317t@gmail.com> wrote:

For behavioral sim you could go with a brand agnostic tool like ghdl
and iverilog are both free, and I've used them sucessfully for simple
to quite large designs. I find the Xilinx and Altera tools to be too
slow and cumbersome, but I haven't compared those sim tools to ghdl or
iverilog.

Interesting. Would it be possible to do a functional simulation based
on the post-place & route VHDL file generated by ISE with ghdl?

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

 

[Symon]

Hi Michael,
This might help you...
Cheers, Syms.
http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

 

[HT-Lab]

<chrisdekoh@gmail.com> wrote in message
news:6ee86d42-4111-4a7c-8a85-30011b78a244@q27g2000prf.googlegroups.com...

Hi,
I am wondering if anyone of you have experienced this before. Here
goes the reset problem I am facing now. asynchronous reset in FPGAs
are usually a big NO-NO. from the articles I am reading, the async
reset, normally results in more logic being used to stitch up LUTs
together.
However, the design I am currently working on requires only one of
the blocks to run at 1/4 that of the original clock speed. I am using
a DCM to clock divide the master clock, and the output goes into this
block. The problem happens when

- the reset signal which resets the DCM, is the same reset which goes
into this same block.
- This will result in a problem, as the clock-divide-by-4 as I call
it, will not emit a clock pulse in reset state, as the DCM has not
locked yet. the synchronous reset will thus not work for this block.

1) Any ideas of how to circumvent this problem? I would like to use
synchronous resets, but also use the divide by 4 clock for the block.
2) Are my concepts of synchronous resets correct? that synchronous
resets on FPGA are better than asynchronous resets?

I believe this only applies to Xilinx FPGA's and not to any other vendors.

From http://www.xilinx.com/support/documentation/white_papers/wp248.pdf :

Use of Synchronous Sets/Resets
If a set or reset is necessary for the proper operation of the circuit, a
synchronous reset
should always be coded. Synchronous sets/resets not only have improved
timing
characteristics and stability but can also result in smaller, better
utilization within the
FPGA. Synchronous sets/resets can result in less logic (fewer LUTs), fewer
restrictions on packing, and, often, faster circuits.

Hans
www.ht-lab.com

thanks

Chris

 

[Göran Bilski]

Hi,

SFSL0 and MFSL0 has the same ID which is 0.

What version of EDK are you using?

Göran

<chrisdekoh@gmail.com> wrote in message
news:2a8aade4-dfe3-4ddc-846c-fb6900ef3c6f@a23g2000hsc.googlegroups.com...

Hi,
does anyone know how to use a 2nd FSL peripheral attached to
microblaze? This is what I did. I have attached 2 peripherals, let's
say we call it peripheral1 and peripheral2 to the microblaze's FSL
bus.

now here comes the problem. Using the commands
putfsl(val,0) and getfsl(val,1), I am able to write and read from
peripheral 1 respectively.

However, when I do
putfsl(val,2) and getfsl(val,3), nothing happens from peripheral2; I
thought i was supposed to write and read from peripheral 2
respectively by these commands.

I have been struggling with this for a while...any of your inputs
would really be great.



--- excerpt from system.mhs file


BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_FSL_LINKS = 2
PARAMETER C_USE_FPU = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE SFSL0 = peripheral1_to_microblaze_0 ## IS THE ID 1?
BUS_INTERFACE MFSL0 = microblaze_0_to_peripheral1 ## IS THE ID 0?
BUS_INTERFACE SFSL1 = peripheral2_0_to_microblaze_0 ## IS THE ID 3?
BUS_INTERFACE MFSL1 = microblaze_0_to_peripheral2 ## IS THE ID 2?
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END


otherwise, how to determine the corresponding ID of the FSL
peripherals? I have looked through fsl_v20.pdf but dun see anything
useful.

thanks a million!
Chris

 

[HT-Lab]

"Tim Pope" <timpope.programmer@gmail.com> wrote in message
news:601826a6-2169-4008-bcf6-cdd1e0afb9ee@s33g2000pri.googlegroups.com...

Hi All

i am new to FPGA's and have picked up a celoxica rc1000pp (virtex
2000e) cheap, the downside...no manuals or software.
i expected that (being an old bit of kit) the drivers and manuals
would be easy to get hold of....oh how i was wrong

does anyone on this mailing list have any details on the board... i
know there is an old windows driver, source-code for an old linux
driver available.

Celoxica was recently bought by Catalytic Inc (now renamed to AgilityDS). I
would send them an email (support@..) to see if they can send you the
drivers and perhaps the source code for it.

Hans
www.ht-lab.com

i'm not really interested in handel-c but i've been told it was
possible to use vhdl and load it on there (source provided
apparently)...if someone has that source

also any and all documentation would be great (pdf's etc preferred)

i jumped in at the deep end but the more docs and code i can get the
better (i will probably update the linux pci driver for latest kernel
and go from there...though i'll need the old source first ;-)

if you can help then thanks very much in advance

Tim

 

[RCIngham]

On Apr 21, 4:34 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com
wrote:
Hello, I have a question about instantiating a module in a verilog
testbench. Sometimes the instantiation may have lots of inputs and
output that you may not want to appear in the ModelSim simulation, is
there a way to stimulate particular signals in a module so the
simulation won't include (display) all of the i/o in your design.

This is probably not the most appropriate forum for this question. Try
http://forums.mugweb.org/ instead.

 

[RCIngham]

On Apr 21, 4:34 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com
wrote:
Hello, I have a question about instantiating a module in a verilog
testbench. Sometimes the instantiation may have lots of inputs and
output that you may not want to appear in the ModelSim simulation, is
there a way to stimulate particular signals in a module so the
simulation won't include (display) all of the i/o in your design.

This is probably not the most appropriate forum for this question. Try
http://forums.mugweb.org/ instead.

 

[HT-Lab]

<jjlindula@hotmail.com> wrote in message
news:7c110d97-7eaa-440e-a661-225a0fd05de2@f36g2000hsa.googlegroups.com...

...snip

);
Here only a few signals would be stimulated and few signals would
appear in the ModelSim simulation window. Is there a way to do this?

I probably don't understand you question but you can simply drag and drop
the signals of interest from the Objects window onto the Waveform window. If
you want to do this from a script than look up the "add wave" command in the
reference manual.

Hans.
www.ht-lab.com

thanks,
joe

 

[HT-Lab]

<jjlindula@hotmail.com> wrote in message
news:7c110d97-7eaa-440e-a661-225a0fd05de2@f36g2000hsa.googlegroups.com...

...snip

);
Here only a few signals would be stimulated and few signals would
appear in the ModelSim simulation window. Is there a way to do this?

I probably don't understand you question but you can simply drag and drop
the signals of interest from the Objects window onto the Waveform window. If
you want to do this from a script than look up the "add wave" command in the
reference manual.

Hans.
www.ht-lab.com

thanks,
joe

 

[HT-Lab]

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:4039fc88-3cab-46eb-b778-3d20001f14d6@d45g2000hsc.googlegroups.com...
On Apr 21, 1:11 pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:

Yes, my son--you are quickly learning the lameness of VHDL. A number
isn't a number--sometimes it must be in single quotes, sometimes in
double quotes, and most often expressed in binary, just as the ancients
used to write. And almost never can you use a number directly, but must
convert it from one arcane type to another. -Kevin- Hide quoted text -


On the first day, the VHDL gods created 'integer', 'natural', etc. and
created ways to easily specify such numbers in any base, and saw that
it was good...and the VHDL gods said, go forth and use these types for
they are of my creation and they are good....but the unbelievers who
think every number will potentially be bigger than 32 bits on each and
every design that they create and the scallywags that created
std_logic_arith refused to use 'integer' and instead used
std_logic_vectors to perform arithmetic and then cursed the VHDL
language for the numerous type conversions that they themselves
brought down upon themselves....

KJ

very good

Hans
www.ht-lab.com

 

[HT-Lab]

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:4039fc88-3cab-46eb-b778-3d20001f14d6@d45g2000hsc.googlegroups.com...
On Apr 21, 1:11 pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:

Yes, my son--you are quickly learning the lameness of VHDL. A number
isn't a number--sometimes it must be in single quotes, sometimes in
double quotes, and most often expressed in binary, just as the ancients
used to write. And almost never can you use a number directly, but must
convert it from one arcane type to another. -Kevin- Hide quoted text -


On the first day, the VHDL gods created 'integer', 'natural', etc. and
created ways to easily specify such numbers in any base, and saw that
it was good...and the VHDL gods said, go forth and use these types for
they are of my creation and they are good....but the unbelievers who
think every number will potentially be bigger than 32 bits on each and
every design that they create and the scallywags that created
std_logic_arith refused to use 'integer' and instead used
std_logic_vectors to perform arithmetic and then cursed the VHDL
language for the numerous type conversions that they themselves
brought down upon themselves....

KJ

very good

Hans
www.ht-lab.com

 

[Nial Stewart]

"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:6864a277-1433-452a-9918-c60c6b2c9463@u36g2000prf.googlegroups.com...
On Apr 20, 7:01 pm, chrisde...@gmail.com wrote:
Hi Peter,
I do not have this luxury. The core which is running at f/4 clock
is a core originally written in Handel C and given to me as a ngc file
and not in VHDL. The maximum synthesizable speed of this core is only
at f/4 MHz. The core thus has to run at an f/4 clock.
With this set of restrictions in mind, could there still be a
solution to the reset problem?
Chris

There must be a limited number of flip-flops in that part of the
design. Just clock each of them with the fast clock, and drive CE with
the slower clock.

Peter, from what Chris has said I don't think there are CE's into the
core he's using.




Nial

 

[Nial Stewart]

Hello, thanks for responding to my post. Sorry for me confusing
everyone. Let's say I have a large design that has lots of inputs and
outputs and let's say I'm only interested in a simulation consisting
of only a few inputs and outputs. When I run ModelSim it will add in
all the inputs/output of the module I am simulating, thus adding in
all of the inputs and outputs of my design into the waveform window. I
was hoping I could configure something so when the simulation finishes
it would display the signals I'm interested in. Is that possible? I'll
also try the other newsgroup and see if anyone has a solution.

How are you running Modelsim?

When I run it up, load a project/simulation then open the wave window there
are no signals in it.

I've got a 'standard' naming convention so I can easily find and load the
*.do file that loads the signals associated with a particular testbench.
These are then saved in the /Modesim sub directory of the project in
question.



Nial.

 

[Stef]

In comp.arch.fpga,
jjlindula@hotmail.com <jjlindula@hotmail.com> wrote:

On Apr 22, 2:13 am, "HT-Lab" <han...@ht-lab.com> wrote:
jjlind...@hotmail.com> wrote in message

news:7c110d97-7eaa-440e-a661-225a0fd05de2@f36g2000hsa.googlegroups.com...

..snip

);
Here only a few signals would be stimulated and few signals would
appear in the ModelSim simulation window. Is there a way to do this?

I probably don't understand you question but you can simply drag and drop
the signals of interest from the Objects window onto the Waveform window. If
you want to do this from a script than look up the "add wave" command in the
reference manual.


Hello, thanks for responding to my post. Sorry for me confusing
everyone. Let's say I have a large design that has lots of inputs and
outputs and let's say I'm only interested in a simulation consisting
of only a few inputs and outputs. When I run ModelSim it will add in
all the inputs/output of the module I am simulating, thus adding in
all of the inputs and outputs of my design into the waveform window. I
was hoping I could configure something so when the simulation finishes
it would display the signals I'm interested in. Is that possible? I'll
also try the other newsgroup and see if anyone has a solution.

I don't believe modelsim automatically adds signals to the wave window,
it also does not automatically run a simulation.
How do you start modelsim? Your environment may start modelsim with a
scriptfile (.do) and it may have generated a default for this script
that adds all your IO to the wave window and runs the simulation to
completion.

If you can find that script, you can probably modify it to suit your
needs.

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

Out of sig error

 

[MM]

<mspiegels@gmail.com> wrote in message
news:ba79fdd6-bd77-4b2c-a1a8-b2253055a564@x19g2000prg.googlegroups.com...

The only problem is that i have no idee which pins belong to the
DCM...and don't know how to connect the DCM's clock outputs to the
DIFF CLK output-pins in order to measure them.
So if anybody could tell me which bank and pin-number belongs to the
DCM(s) i would be very happy

There are no pins belonging to DCMs. There are pins dedicated as clock
inputs though. Usually pin assignments are handled in the project's UCF
file. For your differential output you need to instantiate a differential
driver in your HDL code and assign the pins in the UCF.. Driving clock out
of the chip is better done with a DDR register in IOB, but this is another
issue, probably not important for you at this point.


/Mikhail

 

[Andreas Ehliar]

On 2008-04-23, ee_ether <xjjzdv402@sneakemail.com> wrote:

Hi,

A colleague and I are having a friendly debate on coding state
machines in Verilog, targeting synthesis for FPGAs. Comments are very
appreciated. I am NOT trying to start a holy war here regarding
syntax style (one process vs. two process, etc).

Crux of the matter: Do you need to define values for outputs of your
state machine in EVERY state, or do you only need to define values for
outputs in states where you want the output to update/change?

In a process activated by a clock edge it is not necessary to specify
the output value in every branch. It is possible to create synchronous
logic anyway. The following example will show a flip-flop with a load
enable for example.

always @(posedge clk) begin
if (ce) q <= d; // Flip flop with enable signal
//else q <= q; // This is automatically implied
end

However, if you have a combinational circuit I guess you could see
the construction like this:

always @* begin
if (ce) q = d;
// else q = q; // This is also automatically implied
end

The problem is that q = q would build a combinational loop and the
synthesizer will probably implement this as a latch.



(In reality I guess there might be some simulation issues. I guess
that a simulator is not even going to update q with the value of q
if the else case is not present. Actually, I'm not sure that it will
update q anyway, even if the else case is present as it is just going
to be updated with the same value. A quick experiment indicates that
at least ModelSim doesn't update the variable in this case at least.)

/Andreas

 

[Symon]

http://toolbox.xilinx.com/docsan/xilinx92/books/docs/cgd/cgd.pdf

 

[Symon]

http://toolbox.xilinx.com/docsan/xilinx92/books/docs/cgd/cgd.pdf

 

[Symon]

Alan Nishioka wrote:

Xilinx is canceling the Virtex-E XCV1000E-FG860.

We are currently shipping a product that uses 13 of these chips on 4
different boards.

Does anyone have any ideas on how to deal with this?

One possibility is to rev the boards to use the XCV1000E-FG900, making
minimal changes to the boards around the fpga.

Complete re-design of the boards for this old system is out of the
question. Stockpiling a bunch of parts won't work because we don't
know what future quantities will be and the parts are very expensive.

Alan Nishioka
alan@nishioka.com

Hi Alan,
Maybe an interposer would work? Mount the FG900 on that, mount the
interposer on your board? Somethign like this...
http://advanced.com/pdf/AIC_BGA_Interposer_DataSheet_revJun07.pdf
HTH., Syms.