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already knows the encryption key?Alvin Andries wrote:
But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there
are
more than 100 of these in the larger V5 SX(T) devices (too lasy to look
up
the exact number), you will end up with quite a bit less than 1000 FPGAs.
Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
Perhaps use the money it costs for all those FPGAs to pay off someone who
already knows the encryption key?Alvin Andries wrote:
But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there
are
more than 100 of these in the larger V5 SX(T) devices (too lasy to look
up
the exact number), you will end up with quite a bit less than 1000 FPGAs.
Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
Perhaps use the money it costs for all those FPGAs to pay off someone who
B.t.w two questions:Antti wrote:
snip
quit simple
if you want to deliver a BITFILE only and allow the client to
change the software but not the FPGA bit file itself.
this is VERY simple with Xilinx tools
and IMPOSSIBLE with Altera tools
Sounds like simple common sense - what is it that prevents
Altera from offering this ? - and why did they miss
this obvious flow ?
Aren't you supposed to shoot everybody you tell about the project?Tim (one of many) wrote:
Alvin Andries wrote:
But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since
there are
more than 100 of these in the larger V5 SX(T) devices (too lasy to
look up
the exact number), you will end up with quite a bit less than 1000 FPGAs.
Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
But not totally outrageous. I've recently completed a beamforming
antenna design for installation in an aircraft that uses one Virtex
4SX55 for each antenna element. There are 240 antenna elements, thus
240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the
FPGA is a 10 channel tuner, downconverter, and beam steering.
What "voltage p-p" is 128.2 mV? Is this something you observe at an output?Hello,
I have a project where i have to implement a ring oscillator (3 not
gates) using an altera DE2.
But i am confronted to several problems.
The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
quartus has optmised 'a little too much' since i want to see the
delay.
Is there any way to disable the optimisation ? I have read and show on
option 'wire keep_wire', but i did not manage to make it work ... Or
maybe it is another problem.
You probably drive the gates in the linear region, where a lot of current isI do not understand the "Don't the gate in the chain short chain get
overloaded?"
....
You probably drive the gates in the linear region, where a lot of current isI do not understand the "Don't the gate in the chain short chain get
overloaded?"
....
I have one example of this in my PPC405 design atB.t.w two questions:
- can anybody give an example commandline for a real world DATA2MEM
example?
I have one example of this in my PPC405 design atB.t.w two questions:
- can anybody give an example commandline for a real world DATA2MEM
example?
Use impact withLe Wed, 09 Apr 2008 12:49:43 -0400, DJ Delorie a écrit:
Habib Bouaziz-Viallet <habib@rigel.systems> writes:
I'm wondering if a basic tool already exist to program Xilinx CPLD
(XC95144 and so) under Linux (preferably with the old Parralle cable III)
Hi !
It's always a pleasure to speak with you M. Delorie
Doesn't ISE itself have such a tool?
I'm working with WebPack ISE and i guess that the programming tools
(ImpACT) is a native MS-Windows tool and did not work under GNU/Linux.
I'm building a parallel cable for my own so i did not already test it.
I don't have direct experience with the Xilinx simulation, but a coupleI've noticed that the Xilinx FFT bit-accurate c simulation calls are
very very slow. Anyone else notice this?
snip
The program is single-threaded right now, and I intend to write a
multi-threaded version soon. But first, I decided to use a profiler
on my single-threaded code to see what kind of speedup I should
expect. I wasn't very surprised to find that 99% of my execution time
was taking place inside the xilinx_ip_xfft_v5_0_bitacc_simulate()
function. I WAS surprised to find that 55.6% of that function's
execution time is being spent in malloc() and free() calls. I have
some nice call graphs and an excel spreadsheet I'd be willing to share
if someone from Xilinx would like to take a look.
Petersen Curt
If you like to go the SVF way, urjtag (look on sourceforge) can play SVF onPS :
Although the DJ Delorie solution (xapp058) requires more work, I would go
more deeply later.
Your book is talking about simulation. You can't synthesise that code,Hi,
in my book it's written that the clock
has to instactiated like this :
Hi Thorsten,
Your book is talking about simulation. You can't synthesise that code,Hi,
in my book it's written that the clock
has to instactiated like this :
Hi Thorsten,
beginOK,
I found the pin, now another question. This is also for simulation only:
reset <= '1', '0' after T/2;
I tried to convert that like that :
process
begin
reset <= '1';
wait until falling_edge(clk);
reset <= '0';
end process;
But that would run forever, right ?
Is it possible to abort a process after 1 execution ?
--TK
generate_reset : process
Hi Lars,What happend to the tech Xclusive articles that used to be on the
Xilinx home page? I was trying to find one of Austins excellent
articles on synchronous digital design but where unable to locate it...
....along with 593 emails offering pills to give him a 13 inch penis, and 264On Apr 11, 4:02 pm, Jim Granville <no.s...@designtools.maps.co.nz
wrote:
Lars wrote:
Thanks anyway, and Austin and Peter; if you read this, please use
your influence to correct some of the obvious mistakes made by the
web- people at Xilinx!
Amazing - how hard can it be to get that right ?
-jg
We try to please.
If Lars had only given his real and usable e-mail address, he would
have had the properly formatted information in minutes...
Peter Alfke
Good that you found it on your own.Thorsten Kiefer wrote:
Hi,
I wrote a simple stop watch for the Spartan 3 StarterKit.
Unfortunately it seems to be unstable, i.e. sometimes
when I release the button, the counter doesn't stop as
it should. During synthesis I get a warning - about
timing I think. Can you have a look at the program
and advice me how to avoid this instability ??
http://tokisworld.org/spartan3/stopwatch.tbz
Best regards
Thorsten
OK, I found the bug......