EDK : FSL macros defined by Xilinx are wrong

[KJ]

"Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message
news:4800baf9$0$580$6e1ede2f@read.cnntp.org...

Thorsten Kiefer wrote:

Hi,
I wrote a simple stop watch for the Spartan 3 StarterKit.
Unfortunately it seems to be unstable, i.e. sometimes
when I release the button, the counter doesn't stop as
it should. During synthesis I get a warning - about
timing I think. Can you have a look at the program
and advice me how to avoid this instability ??

http://tokisworld.org/spartan3/stopwatch.tbz

Best regards
Thorsten

OK, I found the bug......

Good that you found it on your own.

In the future, if you do expect to get any help from any newsgroup you
should put a bit more thought into your posting. Statements like "During
synthesis I get a warning - about timing I think" are completely useless,
I'm 100% confident that the synthesis tool did not report that text. Not
posting any code doesn't give anyone anything to go on either.

Basically, if you would like help, don't make it difficult on the potential
helpers.

KJ

 

kislo <kislo02@student.sdu.dk> wrote:

On 12 Apr., 21:00, kislo <kisl...@student.sdu.dk> wrote:
i got a problem with the Spartan 3E starter kit from Xilinx, no matter
what Mode pins are set for, the DONE LED is always turned on when i
power on the board. I cannot connect to the board via JTAG pin headers
either. All the voltages are correct. What could be the problem ? any
thing i can do to debug it ? i have another Spartan 3E board and it
works fine.

the LED is on even though i hold PROG_B low

Check shorts.
Check power voltages.
Check the schematics.

 

[Symon]

Michael wrote:

I wasn't sure about the speedgrade - but I googled around and found
some other people had used -4 for that option on similar boards. Is
that the correct choice? How would I figure that out? Also, what
exactly does the speedgrade mean? The help file wasn't very verbose
about it.

Thanks!

-Michael

Hi Michael,
It's written on the chip. You'll see 4C somewhere, I expect. This is
speedgrade 4, commercial temperature range. The speedgrade is used to
guarantee the speed of the innards of the device. Read the datasheet, and
look for the 'switching characteristics' section.
HTH., Syms.

 

[Symon]

Michael wrote:

I wasn't sure about the speedgrade - but I googled around and found
some other people had used -4 for that option on similar boards. Is
that the correct choice? How would I figure that out? Also, what
exactly does the speedgrade mean? The help file wasn't very verbose
about it.

Thanks!

-Michael

Hi Michael,
It's written on the chip. You'll see 4C somewhere, I expect. This is
speedgrade 4, commercial temperature range. The speedgrade is used to
guarantee the speed of the innards of the device. Read the datasheet, and
look for the 'switching characteristics' section.
HTH., Syms.

 

[Alvin Andries]

"NRClark" <nicholas.clark@gmail.com> wrote in message
news:5b377f74-9395-46de-b771-dccba3d994d1@k1g2000prb.googlegroups.com...

Hi everybody,

I'm working on a hobbyist board I'm designing to do some audio DSP.
I'm a little new to Verilog,
although not to programming in general. So far the FPGA design work
has been going smoothly
enough, but I'm having some trouble with synthesizing the code I wrote
for my DAC. I tried to avoid
all of the 'common' mistakes and design for synthesizability, but
there's some I must have missed.

My design simulates just fine, but when I go to synthesize it I get
these weird "Multi-source" errors:

ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
shift_counter<4
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
shift_counter<2
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
shift_counter<1
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
Msub__COND_2_Madd
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
Mcount_shift_counter>.

I can't find the bug in my design, which means it must be some bug in
my own understanding.

Any words of insight? My Verilog code follows.

Thanks,
Nick

//------------------------------------
code----------------------------------------
module dac_cs4345(CLK, RST_N, SCLK,
LRCLK, L_DATA, R_DATA,
DATAOUT);

// In this design, CLK = 49.152MHz, MCLK = 24.576MHz,
// SCLK = 6.144MHz, LRCLK = 96KHz. They are all in-phase
// each other, with the various clocks being generated from
// a 49.152MHz crystal and another Veriog module containing
// counters.

// Module port declarations

input CLK, RST_N;
input SCLK, LRCLK;
input [23:0] L_DATA, R_DATA;

output reg DATAOUT;

// Internal declarations

reg r1, r2;
wire SCLK_DELAYED;

// Counter used as an index to access data serially.
reg [4:0] shift_counter;

// L_Data and R_Data are both registered to protect against
// spurious transitions during conversion.
reg [23:0] L_DATA_STORAGE;
reg [23:0] R_DATA_STORAGE;

// Begin Program

// Since our data is set up on the LRCLK edge, we have to allow
// some delay before accessing it. Since SCLK is the clock used
// pull data, a slightly delayed SCLK will be generated and used.
// SCLK_DELAYED arrives one CLK period after SCLK.

always @(posedge CLK) begin
r2 <= r1;
r1 <= SCLK;
end
assign SCLK_DELAYED = r2;

// Both the L and R data are assumed to arrive at this module
// at the same time, and to be available at the rising
// edge of the provided LRCLK. Since LRCLK is the output
// waveform used for synching data, this is a valid assumption.
// L_data and R_data _must_ be set up some time before the
// positive edge of LRCLK.

always @(posedge LRCLK) begin
L_DATA_STORAGE <= L_DATA;
R_DATA_STORAGE <= R_DATA;
shift_counter <= 31; // Reset count-down counter
end

always @(negedge LRCLK)
shift_counter <= 31; // Reset count-down counter

// Output data is assigned here. DATAOUT is assigned the value of
// 0 if our counter has gone past the data's LSB. The DAC's
// left-channel data is supplied when LRCLK is high, and its
// right-channel data is spplied when LRCLK is low.

always @(posedge SCLK_DELAYED) begin
if(shift_counter < 8)
DATAOUT = 0;
else if(LRCLK == 1)
DATAOUT = L_DATA_STORAGE[shift_counter-8];
else
DATAOUT = R_DATA_STORAGE[shift_counter-8];
end

// The timing of this is such that shift_counter counts down
// from 32 to 0 twice in each LRCLK - once per 'side'. This is
// decremented after the output has already been assigned a value.
// shift_counter could also be decremented on the falling edge of
// SCLK_DELAYED without changing the result.

always @(negedge SCLK) begin
shift_counter <= shift_counter-1;
end

endmodule

You adjust shift_counter in multiple processes (always @), which won't do.
You should only have 1 clocked process modifying shift_counter.
With all clocks being synchronously divided versions of CLK = 49.152MHz, you
should substitute the other clocks by "enable"/edge detect signals clocked
on CLK. The low frequency clocks can still be made available/imported from
the external world.

Regards,
Alvin.

 

[Alvin Andries]

"NRClark" <nicholas.clark@gmail.com> wrote in message
news:5b377f74-9395-46de-b771-dccba3d994d1@k1g2000prb.googlegroups.com...

Hi everybody,

I'm working on a hobbyist board I'm designing to do some audio DSP.
I'm a little new to Verilog,
although not to programming in general. So far the FPGA design work
has been going smoothly
enough, but I'm having some trouble with synthesizing the code I wrote
for my DAC. I tried to avoid
all of the 'common' mistakes and design for synthesizability, but
there's some I must have missed.

My design simulates just fine, but when I go to synthesize it I get
these weird "Multi-source" errors:

ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
shift_counter<4
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
shift_counter<2
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
shift_counter<1
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
Msub__COND_2_Madd
ERROR:Xst:528 - Multi-source in Unit <dac_cs4345> on signal
Mcount_shift_counter>.

I can't find the bug in my design, which means it must be some bug in
my own understanding.

Any words of insight? My Verilog code follows.

Thanks,
Nick

//------------------------------------
code----------------------------------------
module dac_cs4345(CLK, RST_N, SCLK,
LRCLK, L_DATA, R_DATA,
DATAOUT);

// In this design, CLK = 49.152MHz, MCLK = 24.576MHz,
// SCLK = 6.144MHz, LRCLK = 96KHz. They are all in-phase
// each other, with the various clocks being generated from
// a 49.152MHz crystal and another Veriog module containing
// counters.

// Module port declarations

input CLK, RST_N;
input SCLK, LRCLK;
input [23:0] L_DATA, R_DATA;

output reg DATAOUT;

// Internal declarations

reg r1, r2;
wire SCLK_DELAYED;

// Counter used as an index to access data serially.
reg [4:0] shift_counter;

// L_Data and R_Data are both registered to protect against
// spurious transitions during conversion.
reg [23:0] L_DATA_STORAGE;
reg [23:0] R_DATA_STORAGE;

// Begin Program

// Since our data is set up on the LRCLK edge, we have to allow
// some delay before accessing it. Since SCLK is the clock used
// pull data, a slightly delayed SCLK will be generated and used.
// SCLK_DELAYED arrives one CLK period after SCLK.

always @(posedge CLK) begin
r2 <= r1;
r1 <= SCLK;
end
assign SCLK_DELAYED = r2;

// Both the L and R data are assumed to arrive at this module
// at the same time, and to be available at the rising
// edge of the provided LRCLK. Since LRCLK is the output
// waveform used for synching data, this is a valid assumption.
// L_data and R_data _must_ be set up some time before the
// positive edge of LRCLK.

always @(posedge LRCLK) begin
L_DATA_STORAGE <= L_DATA;
R_DATA_STORAGE <= R_DATA;
shift_counter <= 31; // Reset count-down counter
end

always @(negedge LRCLK)
shift_counter <= 31; // Reset count-down counter

// Output data is assigned here. DATAOUT is assigned the value of
// 0 if our counter has gone past the data's LSB. The DAC's
// left-channel data is supplied when LRCLK is high, and its
// right-channel data is spplied when LRCLK is low.

always @(posedge SCLK_DELAYED) begin
if(shift_counter < 8)
DATAOUT = 0;
else if(LRCLK == 1)
DATAOUT = L_DATA_STORAGE[shift_counter-8];
else
DATAOUT = R_DATA_STORAGE[shift_counter-8];
end

// The timing of this is such that shift_counter counts down
// from 32 to 0 twice in each LRCLK - once per 'side'. This is
// decremented after the output has already been assigned a value.
// shift_counter could also be decremented on the falling edge of
// SCLK_DELAYED without changing the result.

always @(negedge SCLK) begin
shift_counter <= shift_counter-1;
end

endmodule

You adjust shift_counter in multiple processes (always @), which won't do.
You should only have 1 clocked process modifying shift_counter.
With all clocks being synchronously divided versions of CLK = 49.152MHz, you
should substitute the other clocks by "enable"/edge detect signals clocked
on CLK. The low frequency clocks can still be made available/imported from
the external world.

Regards,
Alvin.

 

ISE on 64 bit Windows runs quite a bit slower and uses more memory than the
32 bit executables. That's why we now install the 32bit executables together
with the 64bit executables on a 64bit system.

However, 64bit Linux runs slightly faster than 32bit Linux.

Steve

"David Brown" <david@westcontrol.removethisbit.com> wrote in message
news:4803021c$0$14994$8404b019@news.wineasy.se...

Eric Smith wrote:
Roger wrote:
Will there be a 64 bit WebPack version of ISE in the near future?

Is it really necessary? WebPack doesn't support parts large enough
to exhaust the memory avialable in the 32-bit world.

Processors using the amd64 ISA have a number of advantages other than just
access to larger amounts of memory. They've got more general purpose
registers, 64-bit arithmetic, and slightly less legacy baggage. So for
some tasks, a program compiled for 64-bit windows/*nix will run noticeably
faster than one compiled for 32-bit mode - even if it does not use much
memory. I have no idea if that applies to ISE, however.

 

[HT-Lab]

"Sue" <sudhangi@gmail.com> wrote in message
news:a6b7da33-81c8-4780-bbfd-822ceade089e@s39g2000prd.googlegroups.com...

Does anyone know how can I get started on making a DOS script file to
synthesize a VHDL design. I tried understanding something from:
http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/xst/xst.pdf

But I still need more help.
Can someone please tell me the sequence which I should follow.

Thanks

This is how Mentor's HDL Designer does it (auto generated)

syn.bat:

"C:/Xilinx/bin/nt/xst.exe" -intstyle xflow -ifn cpu86.xst -ofn cpu86.syr

cpu86.syr: output log file

cpu86.xst: contains the project as shown below (note not all synthesis
settings shown):

set -xsthdpdir ./xst
run
-ifn cpu86.prj
-ofn cpu86
-top cpu86
-p xc3s500e-cp132-4
-uc cpu86.xcf

cpu86.prj: contains the file list

vhdl cpu86 proc_rtl.vhd
vhdl cpu86 cpu86_struct.vhd

cpu86.xcf: contains the UCF settings:

NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 0.025 us;

Good luck,

Hans
www.ht-lab.com

 

[HT-Lab]

"Sue" <sudhangi@gmail.com> wrote in message
news:a6b7da33-81c8-4780-bbfd-822ceade089e@s39g2000prd.googlegroups.com...

Does anyone know how can I get started on making a DOS script file to
synthesize a VHDL design. I tried understanding something from:
http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/xst/xst.pdf

But I still need more help.
Can someone please tell me the sequence which I should follow.

Thanks

This is how Mentor's HDL Designer does it (auto generated)

syn.bat:

"C:/Xilinx/bin/nt/xst.exe" -intstyle xflow -ifn cpu86.xst -ofn cpu86.syr

cpu86.syr: output log file

cpu86.xst: contains the project as shown below (note not all synthesis
settings shown):

set -xsthdpdir ./xst
run
-ifn cpu86.prj
-ofn cpu86
-top cpu86
-p xc3s500e-cp132-4
-uc cpu86.xcf

cpu86.prj: contains the file list

vhdl cpu86 proc_rtl.vhd
vhdl cpu86 cpu86_struct.vhd

cpu86.xcf: contains the UCF settings:

NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 0.025 us;

Good luck,

Hans
www.ht-lab.com

 

[RCIngham]

which would be more useful to learn in the industrial world: Verilog
or VHDL?

In Europe (including UK) VHDL is more commonly used.

In USA Verilog is prevalent.

However, SystemVerilog is gradually gaining ground everywhere, and
Verilog-2001 is a subset of SV.

It is probably very difficult to learn both simultaneously...

 

[HT-Lab]

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:fu2ku0$aep3@cnn.xsj.xilinx.com...

Michael wrote:
Howdy - I'm just getting started with FPGAs. In college I remember we
used ModelSim with ISE for FPGA simulation. We were able to get a
license through our school for free. Like a fool I no longer have that
license, so what free options are out there? I saw that there is
something called ModelSim Xilinx Edition III Starter (http://
www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
limited feature package, or a time limited package. Is that what I
want? Or is there something else I should be looking at?

Thanks!

-Michael

The ModelSim starter is limited. I think the main limitation is that it
is programmed to get radically slower as the number of lines of HDL
increases. -Kevin

Starter edition slows down to 1% of PE (basically grinds to a halt) after
10000 lines (executable lines), below 10000 lines it operates at 30% of PE.

MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.

There is no swift, mixed language or SystemC support in either version.

Hans
www.ht-lab.com

 

[HT-Lab]

"Michael" <nleahcim@gmail.com> wrote in message
news:d46de822-ec69-411f-9c02-1d98727b9f46@d26g2000prg.googlegroups.com...
On Apr 15, 12:43 pm, "HT-Lab" <han...@ht-lab.com> wrote:

"Kevin Neilson" <kevin_neil...@removethiscomcast.net> wrote in message

news:fu2ku0$aep3@cnn.xsj.xilinx.com...





Michael wrote:
Howdy - I'm just getting started with FPGAs. In college I remember we
used ModelSim with ISE for FPGA simulation. We were able to get a
license through our school for free. Like a fool I no longer have that
license, so what free options are out there? I saw that there is
something called ModelSim Xilinx Edition III Starter (http://
www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
limited feature package, or a time limited package. Is that what I
want? Or is there something else I should be looking at?

Thanks!

-Michael

The ModelSim starter is limited. I think the main limitation is that it
is programmed to get radically slower as the number of lines of HDL
increases. -Kevin

Starter edition slows down to 1% of PE (basically grinds to a halt) after
10000 lines (executable lines), below 10000 lines it operates at 30% of
PE.

MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.

There is no swift, mixed language or SystemC support in either version.

Hanswww.ht-lab.com

Hi Hans - thanks for the information. I'm not terribly worried about
speed at the moment - I'm just trying to learn the basics for now. Do
you know how the student edition (http://www.model.com/resources/
student_edition/student_default.asp) compares to these?

I believe it is the same speed as PE but I am not 100% sure.

It can't handle mixed HDL designs which seems a bit of a handicap -

I agree, some companies (I don't want to mention any names
*cough*Micron*cough*) decided to only provide models in one language forcing
users to spend extra money on a dual language license, perhaps they are
sponsored by the EDA industry?

Hans
www.ht-lab.com

 

[HT-Lab]

"Michael" <nleahcim@gmail.com> wrote in message
news:d46de822-ec69-411f-9c02-1d98727b9f46@d26g2000prg.googlegroups.com...
On Apr 15, 12:43 pm, "HT-Lab" <han...@ht-lab.com> wrote:

"Kevin Neilson" <kevin_neil...@removethiscomcast.net> wrote in message

news:fu2ku0$aep3@cnn.xsj.xilinx.com...





Michael wrote:
Howdy - I'm just getting started with FPGAs. In college I remember we
used ModelSim with ISE for FPGA simulation. We were able to get a
license through our school for free. Like a fool I no longer have that
license, so what free options are out there? I saw that there is
something called ModelSim Xilinx Edition III Starter (http://
www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
limited feature package, or a time limited package. Is that what I
want? Or is there something else I should be looking at?

Thanks!

-Michael

The ModelSim starter is limited. I think the main limitation is that it
is programmed to get radically slower as the number of lines of HDL
increases. -Kevin

Starter edition slows down to 1% of PE (basically grinds to a halt) after
10000 lines (executable lines), below 10000 lines it operates at 30% of
PE.

MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.

There is no swift, mixed language or SystemC support in either version.

Hanswww.ht-lab.com

Hi Hans - thanks for the information. I'm not terribly worried about
speed at the moment - I'm just trying to learn the basics for now. Do
you know how the student edition (http://www.model.com/resources/
student_edition/student_default.asp) compares to these?

I believe it is the same speed as PE but I am not 100% sure.

It can't handle mixed HDL designs which seems a bit of a handicap -

I agree, some companies (I don't want to mention any names
*cough*Micron*cough*) decided to only provide models in one language forcing
users to spend extra money on a dual language license, perhaps they are
sponsored by the EDA industry?

Hans
www.ht-lab.com

 

[HT-Lab]

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:fu2k7i$aep1@cnn.xsj.xilinx.com...

Michael wrote:
Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
Kit with Xilinx ISE. I am an electrical engineer by training and did
some verilog in my collegiate days - but that was quite some time ago
and it is all very fuzzy now. I have decided that as an EE I should be
familiar with FPGAs - so I'm re-educating myself. With that said -
which would be more useful to learn in the industrial world: Verilog
or VHDL?

Thanks!

-Michael
Verilog is better, but VHDL is used more in FPGAs.

Statements like this are best described with the help of a bit of
multimedia:

http://www.youtube.com/watch?v=0PSMr_0qCak

Hans
www.ht-lab.com

SystemVerilog (a Verilog superset) is the future, but in the FPGA world,
the future is often further away than you'd think. (Verilog-2001 features
are still lacking in some tools.) The far future is sequential
C-to-gates. Teach that to your grandchildren. -Kevin

 

[HT-Lab]

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:fu2k7i$aep1@cnn.xsj.xilinx.com...

Michael wrote:
Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
Kit with Xilinx ISE. I am an electrical engineer by training and did
some verilog in my collegiate days - but that was quite some time ago
and it is all very fuzzy now. I have decided that as an EE I should be
familiar with FPGAs - so I'm re-educating myself. With that said -
which would be more useful to learn in the industrial world: Verilog
or VHDL?

Thanks!

-Michael
Verilog is better, but VHDL is used more in FPGAs.

Statements like this are best described with the help of a bit of
multimedia:

http://www.youtube.com/watch?v=0PSMr_0qCak

Hans
www.ht-lab.com

SystemVerilog (a Verilog superset) is the future, but in the FPGA world,
the future is often further away than you'd think. (Verilog-2001 features
are still lacking in some tools.) The far future is sequential
C-to-gates. Teach that to your grandchildren. -Kevin

 

[Gavin Scott]

Roger <rogerwilson@hotmail.com> wrote:

Thanks for the comments in response to my initial query. It sounds like
there won't be a 64 bit Webpack - which is a shame as the devices covered by
it are sufficient for my work and I've got a PC with Vista 64 bit on it!

It's unfortunate that so many people seem to have have this feeling
that 64-bit programs are better than 32-bit programs in all cases

Of course it's also unfortunate that Windows does not support an ILP32
memory model that would utilize the other AMD extensions to the x86
architecure such as the additional registers and register widths.

G.

 

[Symon]

Dave wrote:

Does anybody out there have a good methodology for determining your
optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean?
The brute force method is fairly maddening. I'd be curious to hear if
anybody has any 'tricks of the trade' here.

Also, just out of curiosity, how many of you do your own PCB layout,
versus farming it out? It would certainly save us a lot of money to
buy the tools and do it ourselves, but it seems like laying out a
board out well requires quite a bit of experience, especially a 6-8
layer board with high pin count FPGA's.

We're just setting up a hardware shop here, and although I've been
doing FPGA and board schematics design for a while, it's always been
at a larger company with resources to farm the layout out, and we
never did anything high-speed to really worry about the board layout
too much. Thanks in advance for your opinions.

Dave

Hi Dave,
I layout my own PCBs. Unlike Mike T., I don't let the FPGA tools pick the
pinout. That said, it is important to consider carefully consider nets which
might have tight timing, e.g. clocks. I reason that there is a lot more
flexibility in the FPGA routing than on my PCB, and it's cheaper, so I can
save most time and money by being flexible in the pinout. I set the banks
the nets are to go on, and firm up the detailed pinout by swapping pins on
the FPGAs banks during the PCB layout process. You need some experience in
what your HDL code is gonna look like to be able to do this, but there you
go.
If you are adept at FPGA work, you'll find learning a PCB layout tool is a
piece of cake. I also use laser drilled microvias from layer 1 to 2, which
make the layout of big BGAs easier and saves layers. SI is easier also. The
price is usually less this way; the layers outweigh the via expense. You
don't need buried vias, IME.
Some of my FPGA buddies and I have had bad experiences with contract PCB
people. Sometimes they are knowledgeable and talented, but sometimes they
are dogmatic idiots, and sometimes they are useless. If you go the contract
route, it's important to closely monitor what they get up to so you find out
early doors which type they are.
Like you and Mike say, it depends a lot on your experience. If you've worked
closely with your layout guys in the past, that'll be a big help to you.
For sure, there's more than one way to skin a cat, but I enjoy PCB layout.
YMMV, good luck with it.
Cheers, Syms.
p.s. One benefit to laying out the PCB yourself is that it can help you spot
stupid mistakes in the circuit as you go. It forces you to look very closely
at the layout.

 

[Symon]

Joerg wrote:

Yep, that's why I usually do not do my own layouts. Occassionally I
route a small portion of a circuit and send that to my layouter. No
DRC or anything, just to show him how I'd like it done.

Hi Joerg,

That's a excellent middle way.
Cheers, Syms.

 

[Symon]

Andy wrote:

assignments, but after that, we are often able to let the PWB tool
auto-swap the FPGA pins, and then clean that up in layout. Then we
feed that pin out back to the FPGA design tools, and make sure we can
place and route the design in the FPGA while meeting timing. This is
often with a preliminary version of the FPGA code, but with relevant
IO structures in place.

Andy

Hi Andy,
Do you use PADS I/O designer?

Also, have you ever found that the PWB tool swapped pins that prevented your
FPGA code meeting timing? I never bother testing, because it always does.
I'd be interested in any counter examples you have.
Thanks for your post, Syms.

 

[HT-Lab]

<robquigley@gmail.com> wrote in message
news:b111607f-eba0-4eba-85ef-1c14e1431c3b@a70g2000hsh.googlegroups.com...

Hey everybody,

Just started using Xilinx XST as my synthesis tool and I'm just
looking for the command line instruction (or GUI) to set the design
frequency, I was using precision where it was "setup_design -
frequency=66".

Anyone know the equivalent command for XST?

My eyes cant seem to find it in the documentation! :-(


Cheers,


Rob.

UCF file?

NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 0.025 us;

Hans
www.ht-lab.com