EDK : FSL macros defined by Xilinx are wrong

[whygee]

-jg wrote:

On Nov 26, 12:17 pm, whygee <y...@yg.yg> wrote:
So I think the jitter is not critical, but overall stability is desirable.
Commercial temperature range is OK.
But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars
would have been good : it could keep track of time/date AND provide real-time signals
If those last few ppm matter, you will pay for them...
sure... i'll go for the price first ;-)

I have searched a couple of well known stores and the best
(and cheapest) I could find is 3x5 at about $2/pc.
If I want 50pc, my "pocket money" won't be enough

1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768
ans = 2.56e-6
That's a complex computation, the PLL's dividers
are too small for division by 3051...
Not complex : You divide 100MHz by 3051 one out of 4 times, and 3 out
of 4 times, you divide by 3052. So that's just 12FF for the 3051/3052
counter, and 2FF for the 'which of 4? counter'
It seems that it's too demanding, the FF are not the whole story.

At 100MHz, I can only count on a depth of 5 or 6 gates with 3-inputs
(the target is A3P250), I would have liked a predivider at least...

A 12.288MHz main clock seems much easier, though software delays will be
impacted by the 1.7% decrease... What other trouble could occur when
the clock is slowed down a bit ? For the slow & precise measurements, I am fine
with the internal power-of-two timer, but what fast operations could go wrong
or simply be affected or impacted ? I/O timings are mostly specified with a
"minimum delay" so non-polled peripherals should be fine, communication
protocols are handshaked... No, I don't see what impact a reduction
from 100MHz to 98MHz could have on good software. Particularly if it
is meant for a CPU that could have an adjustable main clock.

The only effect is on ego (or marketing) because 100MHz is a "sweet spot"
and 98 looks more like a miss, even though static timing analysis
reports better than that. But who said that marketing was compatible
with engineering ?

-jg
jg != malcolm ?
My son grabs his gmail, and I don't always notice....
erf

-jg
yg

--
http://ygdes.com / http://yasep.org

 

[-jg]

On Nov 26, 12:17 pm, whygee <y...@yg.yg> wrote:

malcolm wrote:
If this is for motion control,
it's likely the 40ns jitter and 5ppm of
my earlier example is fine...

By "motion control" I mean something similar to
Microchip's AN964 : "Software PID Control of an Inverted Pendulum Using the PIC16F684 "http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeI...

So I think the jitter is not critical, but overall stability is desirable..
Commercial temperature range is OK.
But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars
would have been good : it could keep track of time/date AND provide real-time signals

If those last few ppm matter, you will pay for them...

1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768
ans = 2.56e-6

That's a complex computation, the PLL's dividers
are too small for division by 3051...

Not complex : You divide 100MHz by 3051 one out of 4 times, and 3 out
of 4 times, you divide by 3052. So that's just 12FF for the 3051/3052
counter, and 2FF for the
'which of 4? counter'

-jg

jg != malcolm ?

My son grabs his gmail, and I don't always notice....

-jg

 

[-jg]

On Dec 11, 6:41 am, rickman <arius....@gmail.com> wrote:

On Dec 4, 6:39 am, "Nial Stewart"

nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
FPGA design using a PCB layout tool is a recipe for disaster.

Indeed, I think they're wasting their time down this path.

What is good is the ability to pin/netlist swap when routing and pass
that back to the FPGA constraints. They should concentrate on this and making it
as flexible as possible but forget the FPGA development side of things.

Yes, it should be relatively easy to verify a pin mapping match.
That needs little intelligence, or groundwork, on the PCB side.

Is the tool FPGA pin type aware?  I have found some layout people
don't like to swap pins on FPGAs because it can be very complex due to
the many constraints on pin capability.  If the tool is aware of these
limitations, it could help with intelligent swapping.

There are degrees of awareness, and effort :

Pinswap is the simplest, and that requires a symbol definition that
groups pins as swapable.
Here, the bus stays on a Pin-group, but the bit-destinations swap to
reduce vias.

Hopefully, this should have minimal risk of not
rerouting in the FPGA post-swap.

Next step is possible bank/Pin swap, which is more work, and more risk
(so is less commonly done)

Here, you must define both pin swap and bank swap symbols (which may
include VccIO caveats)

Most companies would avoid this, by first looking at
what banks 'make most sense' to choose, using that venerable tool :
The MK-I eyeball

Note that Actual FPGA place and route, is usually done by the Chip
Vendors tools, so calling a PCB package a 'FPGA Development System',
has much more to do with marketing, than engineering reality.

-jg

 

[laserbeak43]

interesting. I'll try a chipscope demo...

Thanks

On Dec 9, 6:48 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

Andy Peters <goo...@latke.net> writes:
On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shownSignaltap, A feature inQuartusWebpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is theXilinxequivalent - it's not in webpack (personally, I
think that's a mistake onXilinx'spart)

But comparing it toSignaltapmay (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? Whatversionof ChipScope are you using?

10.1.3



Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious

As I recall my experience withSignalTap(which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html

 

[laserbeak43]

I can't even get this simple code to work in the inserter

module two_input_xor (
input wire in1,
input wire in2,
output wire out
);
assign out = in1 ^ in2;
endmodule


On Dec 9, 6:48 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

Andy Peters <goo...@latke.net> writes:
On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

10.1.3



Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html

 

[Ed McGettigan]

On Dec 13, 3:20 pm, laserbeak43 <laserbea...@gmail.com> wrote:

I can't even get this simple code to work in the inserter

module two_input_xor (
        input wire in1,
        input wire in2,
        output wire out
        );
        assign out = in1 ^ in2;
endmodule

On Dec 9, 6:48 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:



Andy Peters <goo...@latke.net> writes:
On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

10.1.3

Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html- Hide quoted text -

- Show quoted text -

You didn't say what failed, but let me guess what they were.

1) Your simple code above doesn't have a clock so either nothing was
captured or it failed to insert because you didn't define a clock.

2) You tried to use the nets in1, in2 and out as the TRIGGER and DATA
sources and this failed. These net names become the PADs in the
design and can not be probed. You need to use the net attached to the
IBUF output for "in1" and "in2" and the net attached to the OBUF input
for "out".

This code would be a better simple design, using clock, in1_reg,
in2_reg and xor_reg.

odule two_input_xor (
input wire in1,
input wire in2,
input wire clock,
output reg out
);

reg in1_reg, in2_reg, xor_reg;

// Input Registers
always @ (posedge clock) begin
in1_reg <= in1;
in2_reg <= in2;
end

// Internal Registers
always @ (posedge clock) begin
xor_reg <= in1_reg ^ in2_reg;
end

// Output Registers
always @ (posedge clock) begin
out <= xor_reg;
end

endmodule

 

[Gabor]

Domain Name : honest-trade06.com
PunnyCode : honest-trade06.com
Creation Date : 2009-12-10 13:13:49
Updated Date : 2009-12-10 13:13:49
Expiration Date : 2010-12-10 13:13:45

Registrant:
Organization : huangbin chen
Name : huangbin chen
Address : Fujian, Putian City Licheng District, 361 Academy
Road
City : putianshi
Province/State : fujiansheng
Country : china
Postal Code : 351100

Administrative Contact:
Name : huangbin chen
Organization : huangbin chen
Address : Fujian, Putian City Licheng District, 361 Academy
Road
City : putianshi
Province/State : fujiansheng
Country : china
Postal Code : 351100
Phone Number : 86-0594-2235212
Fax : 86-0594-2235212
Email : chb422@vip.qq.com

Technical Contact:
Name : huangbin chen
Organization : huangbin chen
Address : Fujian, Putian City Licheng District, 361 Academy
Road
City : putianshi
Province/State : fujiansheng
Country : china
Postal Code : 351100
Phone Number : 86-0594-2235212
Fax : 86-0594-2235212
Email : chb422@vip.qq.com

Billing Contact:
Name : huangbin chen
Organization : huangbin chen
Address : Fujian, Putian City Licheng District, 361 Academy
Road
City : putianshi
Province/State : fujiansheng
Country : china
Postal Code : 351100
Phone Number : 86-0594-2235212
Fax : 86-0594-2235212
Email : chb422@vip.qq.com

 

[-jg]

On Feb 12, 9:05 am, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi,
I finally understand the reason when a flip-flops can be replaced by a
latch.
I saw the circuits before, but not realized what the basic reason was.
With the above paper, I now know that the technology is not a new, it
originated in 1980s.

Even earlier than that.

Just look at the relative sales volumes of the venerable 74373 vs
74374.
In all those cases, the latch is used to buy some extra setup time.

Anywhere you find an ALE pin, you find this principle, and that goes
back a LONG way.

-jg

 

[Weng Tianxiang]

On Feb 16, 12:36 pm, -jg <jim.granvi...@gmail.com> wrote:

On Feb 12, 9:05 am, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi,
I finally understand the reason when a flip-flops can be replaced by a
latch.
I saw the circuits before, but not realized what the basic reason was.
With the above paper, I now know that the technology is not a new, it
originated in 1980s.

Even earlier than that.

 Just look at the relative sales volumes of the venerable 74373 vs
74374.
 In all those cases, the latch is used to buy some extra setup time.

 Anywhere you find an ALE pin, you find this principle, and that goes
back a LONG way.

-jg

jg,
I checked SN74LV374 TI's manual and couldn't find what you said: ALE
pin.

For time borrowing through a pipelined stages, Intel uses Domino Logic
which was not available until 2000.

Weng

 

[glen herrmannsfeldt]

Weng Tianxiang <wtxwtx@gmail.com> wrote:

On Feb 16, 12:36?pm, -jg <jim.granvi...@gmail.com> wrote:

Even earlier than that.

?Just look at the relative sales volumes of the venerable 74373 vs
| 74374. In all those cases, the latch is used to buy some extra
| setup time.

?Anywhere you find an ALE pin, you find this principle, and that
| goes back a LONG way.

I checked SN74LV374 TI's manual and couldn't find what you
said: ALE pin.

ALE is an output on, for example, many Intel processors. Address
Latch Enable, such that the address can be latched while the pins
are used for other purposes.

The 8085 shares the data bus with part of the address bus, for example.
With a 74S373 the address is available for decoding long before ALE
goes low.

-- glen

 

[rickman]

On Feb 16, 7:07 pm, Weng Tianxiang <wtx...@gmail.com> wrote:

On Feb 16, 12:36 pm, -jg <jim.granvi...@gmail.com> wrote:



On Feb 12, 9:05 am, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi,
I finally understand the reason when a flip-flops can be replaced by a
latch.
I saw the circuits before, but not realized what the basic reason was..
With the above paper, I now know that the technology is not a new, it
originated in 1980s.

Even earlier than that.

 Just look at the relative sales volumes of the venerable 74373 vs
74374.
 In all those cases, the latch is used to buy some extra setup time.

 Anywhere you find an ALE pin, you find this principle, and that goes
back a LONG way.

-jg

jg,
I checked SN74LV374 TI's manual and couldn't find what you said: ALE
pin.

For time borrowing through a pipelined stages, Intel uses Domino Logic
which was not available until 2000.

The reason twofold. One is that the pin was not called ALE on the
latch, it was called C or G or LE or something similar. ALE is from
the Intel CPUs that require the latch to hold the address bits. The
other reason is that you are looking at the wrong part. The 373 part
is the latch and the 374 part is the register. I am pretty sure the
only difference is the function of the clock input.

The latch is used with these processors for the exact reason you are
looking at latches. It allows the output of the latch to output a
stable value from the input before the clock edge rather than after.
This was used to speed memory accesses.

Rick

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:
(snip)

The latch is used with these processors for the exact reason you are
looking at latches. It allows the output of the latch to output a
stable value from the input before the clock edge rather than after.
This was used to speed memory accesses.

I still remember latches from when I first started learning about
TTL from Popular Electronics. It was usual to connect a 7490 counter,
a 7475 latch and 7447 BCD to 7 segment decoder together. You run
the counter, the display counts (maybe too fast to see), and then
latches at the appropriate time. Sort of like a lap timer in
a race, which counts up, the latch holds the value while the
counter continues on. After a short time the count continues
on for the next lap. (I think they do this on olympics races.)

-- glen

 

[Weng Tianxiang]

On Feb 16, 5:38 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

rickman <gnu...@gmail.com> wrote:

(snip)

The latch is used with these processors for the exact reason you are
looking at latches.  It allows the output of the latch to output a
stable value from the input before the clock edge rather than after.
This was used to speed memory accesses.

I still remember latches from when I first started learning about
TTL from Popular Electronics.  It was usual to connect a 7490 counter,
a 7475 latch and 7447 BCD to 7 segment decoder together.  You run
the counter, the display counts (maybe too fast to see), and then
latches at the appropriate time.  Sort of like a lap timer in
a race, which counts up, the latch holds the value while the
counter continues on.  After a short time the count continues
on for the next lap.  (I think they do this on olympics races.)

-- glen

glen,
I found a very good example on how to use a latch.

See Xilinx's patent: 5933369 "RAM with synchronous write port using
dynamic latches".

It describes the method Xilinx uses for its distributed RAM.

Weng

 

[austin]

Weng,

Maybe we are using this patent, maybe not.

Just because it is a Xilinx patent does not automatically mean we
actually do this now, or ever.

Austin

 

[Weng Tianxiang]

On Feb 18, 9:28 am, austin <aus...@xilinx.com> wrote:

Weng,

Maybe we are using this patent, maybe not.

Just because it is a Xilinx patent does not automatically mean we
actually do this now, or ever.

Austin

Hi Austin,
Whether or not Xilinx uses the technique doesn't matter to me, I am
not working for Altera or any other FPGA companies, what matters to me
is the technique itself behind the patent.

Those are techniques you cannot learn from any textbooks.

Thank Xilinx, I learn a lot by reading Xilinx's patents.

Weng

 

[cfelton]

Any thoughts as to the relative merits of Modelsim PE and
Active-HDL (PE) for FPGA simulation?

Have had good luck with both. Active-HDL supports command line equivalen
of ModelSim. One issue, the "default" format for the Active-HDL waveform
is large and slow (??). I think it was an extra license (cost) for th
fast format. I don't recall which version of Active-HDL we had but i
might be worth checking before a purchase.

Another small note, Mentor had FAE locally (CO) that was useful. Didn'
have as good access to Aldec FAE. But maybe I never needed to ask, so i
was needed, can't remember?

We ran all simulations from scripts (command line) and both worked fro
that perspective.

.chris



---------------------------------------
Posted through http://www.FPGARelated.com

 

[cfelton]

What about Systemverilog support?

That might be true, does anyone know what the level of SystemVerilo
support is in Active-HDL. Back in 2005 was using Modelsim-PE wit
SystemVerilog fine, support all features I used then, class, interface
etc. BOMK it has been expanded since then.

You can get 30 day eval of both (pretty sure). Might be worth trying ou
unless there is a show stopper like SystemVerilog or multi-languag
support, Active-HDL supports Verilog/VHDL without an extra license (
think).

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Nick]

I've finally decided to buy a better simulator
(I've been making do with Modelsim XE so far).

Any thoughts as to the relative merits of Modelsim PE and
Active-HDL (PE) for FPGA simulation?

Thanks

Pete

I have been using both Modelsim PE and Active HDL since last six years
over the years , I have seen noticeable speed advantage of 2-3 times i
Active HDL-PE compared to Modelsim-PE. I also use lot of scripts t
simulate my designs and link files to AHDL without making local copies i
AHDL project.Well there is definite cost advantage with active HDL-PE.

-Nick



---------------------------------------
Posted through http://www.FPGARelated.com

 

[d_s_klein]

On Mar 4, 8:07 am, "cfelton" <cfelton@n_o_s_p_a_m.ieee.org> wrote:

 BOMK it has been expanded since then.

BOMK?

 

[Andy Peters]

On Mar 4, 10:05 am, d_s_klein <d_s_kl...@yahoo.com> wrote:

On Mar 4, 8:07 am, "cfelton" <cfelton@n_o_s_p_a_m.ieee.org> wrote:

 BOMK it has been expanded since then.

BOMK?

"best of my knowledge."

-a