EDK : FSL macros defined by Xilinx are wrong

fpga_toys@yahoo.com wrote:
Allan Herriman wrote:
How about inferring BRAM for the sboxes? That's what many
implementations do. (I'm assuming the point of the exercise is to
compare the results of an implementation written in C with one written
in a more conventional HDL.)

May seem strange, but the point wasn't to do a head to head comparison
with other HDL's. I've some interest in crypto algorithms and have been
on a search for "projects" which I can use as examples for the FpgaC
release. The changes for technology mapping F5/F6 muxes has been on my
list since last summer. AES and PCI examples just drove the point home
it should be now, not later.
Click to expand...
Well after a few hours of google I did find:
http://web.nps.navy.mil/~dcanrig/pub/sboxalg.c

Which after some serious hacking to reduce to define macros compiles
into just over a hundred luts or so, about a 15-20% savings over using
LUT rams and MUX's which would be a little over 128 LUT's per Sbox. I
suspect with some floorplanning that's faster than routing to use
BRAMs.

He has some HDL for the same algorithm, so when I'm done we can do a
head to head with XST.
 
laura_pretty05@yahoo.com.hk wrote:

My Altera FPGA boards is UP2 development kit-programmable logic for
education, with MAX EPM7128S &FLEX 10K EPF10K70 devices.
Click to expand...
Look at the board: there all pins of the FLEX_EXPAN_X pin rows are
numbered. (Only the numbers for pin 1,2 and 59,60 are printed. This is
the one row on the FLEX_EXPAN_X tables. The other row gives the internal
pin number of the FDGA. If you make pin assignments, this internal pin
number has to be used.

Ralf
 
MM wrote:
Since I upgraded Xilinx tools to ISE8.1SP2 I can start PCAD2004 while ISE is
running... This is all on XP...

Any ideas?
Click to expand...
You CAN start PCAD or you CAN'T start PCAD?

If you CAN'T start PCAD, perhaps you don't have enough memory?

-a
 
The schematic that you link points to is the Parallel Cable III and is used
as a basis of many 3rd party programming cables like ourselves. It will
usually program Coolrunner2 parts as well as XC9500 parts.

I am not quite sure what your CPLD question refers to but both Lattice and
Altera also have CPLD offerings. Even the biggest CPLDs are generally
smaller than smallest FPGAs in effective logic size.


John Adair
Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan-3 Development
Board.
http://www.enterpoint.co.uk


"Duccio" <picinotti.duccio@tin.it> wrote in message
news:1142497117.216446.269970@p10g2000cwp.googlegroups.com...
I want to know if the X2c family (coolrunner II) have a non-volatile
program memory inside its package: I would like a non-volatile memory
(eeprom...) that contains the "programs" also
when it's extinguished (and with a number of macrocells comparable with
a small/medium fpga).
However I would know the name of a low-power, non-volatile program
memory family (CPLD).
Another question: can I use the XC9500 programmer (seen
here: http://www.xilinx.com/support/programr/files/0380507.pdf) to
program the X2c family (or where I can find some programers for the
CPLD package)?

Thanks
Duccio
Click to expand...
 
Duccio wrote:

I want to know if the X2c family (coolrunner II) have a non-volatile
program memory inside its package: I would like a non-volatile memory
(eeprom...) that contains the "programs" also
when it's extinguished (and with a number of macrocells comparable with
a small/medium fpga).
However I would know the name of a low-power, non-volatile program
memory family (CPLD).
Click to expand...
There are a number of players in the On-Chip memory PLD devices

In the CPLD arena

Xilinx X2Cxx you mention
Lattice ispMACH4000z family
Atmel ATF15xASL/BE family,

In the FPGA fabric, but promoted as CPLD or Crossover devices
These make more sense as the macrocell count climbs.
These are not quite as low power as the 'Z' style CPLDs above,
but are less than the hungry FPGAs.

lattice ispMACH_XO
Altera MAX II


and NV FPGAs are also from
Actel - various families
Lattice

...but you will have already looked at the vendors web sites ?

Another question: can I use the XC9500 programmer (seen
here: http://www.xilinx.com/support/programr/files/0380507.pdf) to
program the X2c family (or where I can find some programers for the
CPLD package)?
Click to expand...
Check on the ISP software, for the cables supported.

-jg
 
Testing IS expensive, but so also is running a custom test - thus the
fairly high NRE prices on EasyPath - it also serves as a 'go away' flag
to those with insufficent volumes :)
Click to expand...
My guess is that Xilinx does not prepare custome tests. Instead they
select a handful from their pool of test vectors used to test the
whole device. So the issue is how to decide which test vectors to use
against a customer design: pretty simple really.....

One issue which I feel has been overlooked in the cost analysis is
that yields are higher for easypath than they would be for the
equivalent FPGA part.....

So I'd say that the cost savings come from both testing and yield
improvements....

No?
 
In general, you will find that this is a lot of trouble.

That said, it is done. See the AD12401 at www.analog.com for an example
of a module that interleaves two ADC.

If you want to interleave multiple ADCs there are three main parameters
that must be matched or corrected for on the ADCs. To the extent that
they are not matched, the quality will degrade.

1. DC offset. Easy to track and remove if it is not matched.
2. Gain. Needs to be matched or equalized across your frequency range
of interest.
3. Sampling phase offset. This is the one that will cause you big
problems. If the ADCs have any phase error in when they sample, it
will cause spurs in the data. The hight of the spurs depends on the
sampling phase error. The data sheet for the AD9481 gives an error
budget of < 2 ps for interleaving two 8 bit 250 MS/s ADCs with a 100MHz
analog input. That error budget will go down if your analog input is
higher frequency, or if you want more bits of resolution.

I think that there are some graphs of sampling phase error budgets vs
other parameters some where on the Analog web site, but I do not
remember where.



Regards,

John McCaskill
 
I mean you want to reach 500MS/s sampling?

It could be possible, you must be careful in designing PCB,

Jerzy Gbur
Click to expand...
Yes I would like to reach that sampling, but I guess there are a lot of
other things to take into consideration apart from the pcb like the ADC
errors etc.

Cheers

Jon
 
Yes,The fpga can't handle 5v , so I must use the 74lv245 to convert
the voltage.Now I have made the fpga work successfully,the problem is
that levels of the signals (low effective) are all recognized high
effective.I make the assert by high level,so the device don't work.
 
NickC wrote:
So I'd say that the cost savings come from both testing and yield
improvements....

No?
Click to expand...
With the very high margins as they as they are, and I suspect the
majority of the other direct and indirect costs for all purposes fixed,
I suspect that testing costs are a redherring as far as any significant
cost variable which would signficantly impact end user price. IE for
every dollar of revenue, testing costs are maybe a penny (or two). If
you asked for untested unpackaged die or full wafers prorated by
statistical yield, I suspect there isn't much of a savings to be
offered given that the real price setters are margins, other direct
costs, and indirect costs which remain unchanged.
 
fpga_toys@yahoo.com wrote:

IE for
every dollar of revenue, testing costs are maybe a penny (or two).
Click to expand...
I used to work for a semiconductor company. Test costs were sometimes
very significant, as the test equipment was expensive. Some complex
logic parts had long test times, and for one part I worked on the test
cost was roughly a quarter of the selling price, and roughly half of
the total cost.

Of course, this was an extreme example, and this was decades ago. I'm
sure the business has changed. Still, I'm not convinced that test
costs are quite as low as you assume.


--
Phil Hays
 
I want a board with a few of the largest Spartan3e chips, a little
SRAM, and a PCIExpress 8x slot and controller for under $300. Until
that happens, FPGAs are not in the consumer market in my opinion. All
the current consumer boards lack one necessary feature for general
purpose acceleration and coprocessing: datastream bandwidth. Tinkering
with gates (like one would do with current Digilent starter kits)
should not be considered a consumer product; that is in the hobbiest
arena.

I've worked with the FPGAs in the military some. They use it mostly for
image de/compression and de/encryption -- the obvious uses for them.
Bandwidth is a huge concern on every FPGA application I've ever worked
with, especially with the military. I just wish that thinking would
propagate down to the consumer level. Somehow the graphics card
companies seem to have a grip on it, while other general coprocessing
hardware seems to have been skipped over lightly.
 
Nick,

Yes, and no. That is not what we do.

We take the customer's bit pattern, and use proprietary software to
create a complete set of tests that test to a quality factor that is
much better than we can for a generic FPGA, and far better than any ASIC
test program can test for.

And yes, you figured it out: the yield for EasyPath(tm) is better.

Austin
 
John,

Not true. Test costs are not a red herring.

Look at the time spent in the socket of the tester, both at wafer sort,
and at packaged parts.

Look at the cost of the tester (which is in the millions of $).

We are not talking about a second of time here, we are talking about
running 'zillionz' (actual numbers are proprietary) of patterns at both
wafer sort and more at packaged parts to get the quality factor that our
generic FPGA customers demand.

Remember each test pattern is a configuration, which on a large part,
takes time. The actual running of the pattern is insignificant to the
time it takes to load.

Compare that with only a handful (again proprietary, but the image is
entirely appropriate and accurate) of tests, which actually test to a
better quality factor (coverage) for that application because the design
is known, and only those resources used are tested.

That, and yield are the two factors which contribute to the cost savings
to Xilinx that we can pass on to customers in the form of a lower price.

It is also the reason why we have no small parts in EasyPath(tm): small
parts have far less test time, and they also have extremely good yield
even for the generic versions.

Austin
 
See the First Quarter XCell article "Capturing Data from Gigasample
Analog-to-Digital Converters" for an excellent example by Ian King
showing how to read a pair of 1.5 Gsps ADCs into directly into an LX15.

maxascent wrote:
I am considering trying to interleave two 250MS/s ADCs. Would this be a
good idea? possible? or too much trouble?

Cheers

Jon
Click to expand...
 
Phil Hays wrote:
Of course, this was an extreme example, and this was decades ago. I'm
sure the business has changed. Still, I'm not convinced that test
costs are quite as low as you assume.

From the 2005 annual report 36.6% of revenues are cost of sales, of
about $576M. There are a few direct costs listed in that same report
Click to expand...
which probably are just under half of that which are fixed costs for
buildings, IP, and other payments, dropping the remaining direct costs
per dollar under $0.25. Not included are labor costs, or direct wafer
cost payments, etc to be taken out of that 25 cents. I strongly suspect
from that, testing isn't as much as a penny or two.

So, we know from the gross margins of the annual report, that testing
isn't 50% or even 25% as you may have experienced in the past. I
suspect the big changes over the last couple decades are investments
like BIST style testing to facilitate screening without expensive
testers driving full test coverage as we saw in the 1980's.

Two years ago, the marketing spin was "The Virtex-II EasyPath solution
offers a 25% to 80% cost reduction with production quantity deliveries
(thousands of units) in as little as 8-10 weeks". That level of
discount based on test costs alone doesn't play with the numbers
reported by the annual report. Most of that discount has to be single
piece to volume discounts, or other incentives - not testing costs.
 
Austin, you mentioned a patent on Easypath, I went to look for it, but
couldn't find anything.

Do you know if the patent has been approved and published yet? It
normally takes some time to get it out.....



On Thu, 16 Mar 2006 08:07:14 -0800, Austin Lesea <austin@xilinx.com>
wrote:

Nick,

Yes, and no. That is not what we do.

We take the customer's bit pattern, and use proprietary software to
create a complete set of tests that test to a quality factor that is
much better than we can for a generic FPGA, and far better than any ASIC
test program can test for.

And yes, you figured it out: the yield for EasyPath(tm) is better.

Austin
Click to expand...
 
pd....

-snip-

Automotive I guess is coming, as is aerospace. You could put the two
together, as control electronics.
Click to expand...
Both there now. Account for them as you will. We have a
Aerospace/Defense/Automotive Division today.

Aerospace posses issues with ionizing radiation.
Click to expand...
Which is why we offer the QPro series, and have onging research into
solving all the problems in these applications.

-snip again-

When there's an advantage of reconfiguration ability over static asic
massproduced at low price. A possible app could be builtin reciever for
television, modem etc.. that can be adapted fast to new codecs
post manufacture.
Click to expand...
Already in them. The sets are programmed just as they are leaving (for
country, etc.).



Austin
 
John,

The annual report includes CPLDs, FPGAs (all sizes), services, and storage.

Devil is in the details.

Austin
 
In message <ifmi1218qkjo36fnvf3mk21p6n2k4mv39m@4ax.com>
John C <brakepiston@yahoo.co.uk> wrote:

Reading the LSI Strucutred ASIC fiasco thread has made me think.
People are saying the FPGA revenues are going to grow, so....

Which markets are FPGA heading into?

I mean, at the moment there's Comms, Medical, Military, Consumer.

Where are they going next?

Automotive I guess is coming, as is aerospace. You could put the two
together, as control electronics.

How about seeing them in a PC?
Click to expand...
See http://www.microdigital.info

Altho the company seems to have ceased trading, there are a few of us who
have units.
It uses Spartan xc2s200's, one to implement a northbridge and one as a
memory controller and graphic engine. A xc95144 is used to boot them and
provide memory control.
NOTE this is not a windows machine, but is a RISCOS (http://www.riscos.com)
machine with an ARM based processor.


What are your views on the matter?
Click to expand...
--
webmaster@tankstage.co.uk
Iyonix PC
 
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