EDK : FSL macros defined by Xilinx are wrong

Paul Hartke wrote:
Eli Hughes wrote:

I have noticed though that the interrupt latency is quite high on the
Power PC (10uS! @ 100Mhz clock). Not sure where the weak link was in
the software chain. I was using the Xilinx provide functions for
hooking my own interrupt function. I had a project tha continuously
held the critical interrupt high. In the ISR, I toggled the LED. At a
100Mhz clock, the pulse with was 10uS!

-Eli


That means each ISR took ~1000 wallclock cycles. Were you executing out
of internal BRAM or external DRAM? Were the caches enabled?

Paul
Click to expand...


Everything was out of BRAM. Can't remember if caches were enable. I
have to check the project (Was about 6 months ago).

The only thing else I could figure was that my bit I was toggling was a
GPIO on the OPB. I know that OPB is very slow and may be hanging things
up. Either that or the Xilinx BSP interrupt functions are very bloated.

Never got that figured out. My resolution was to make my own DMA
controller on the PLB to transfer data over the bus. I never hooked
anything system critical to an interrupt, I always used hardware. Only
things like the serial port, etc. were tied to an interrupt.


-Eli
 
laura_pretty05@yahoo.com.hk wrote:

I want to know how can i connect this to PCB?
Click to expand...
I again do not understand you well. If you just write one unclear
sentence there are a lot of possible alternatives.

Do you mean pin assignments from the FPGA to the I/O pins at
FLEX_EXPAN_X? Use your synthesis tool. There must be an option, that is
called "pin assignments" (or similar).
MaxPlus+ generates an acf-file, where you may edit the pin assignments
with a text editor. Or otherwise search the menu. There is always a
manual for the synthesis tool.

Ralf
 
Metal,

Pessimists always claim they are just observing reality.

You must be working for one of those companies "circling the drain?"

Really hard to be positive about anything.


I see (our) business increasing (a lot), and I see margins that are
good, and getting better, and I see new opportunities popping up all
over the place. And I see the financials that support it.

You have told all of us how we will need food, shelter, and a few sticks
to burn here in the not so distant future.

Austin
 
John,

Stop playing the fool.

If one memory bit is bad, out of 20 million, then that FPGA can not be
used for the general public.

But if you don't use that one bit in your patern, then that chip is
perfect for you.

One bit.

That is all we are talking about here. That is EasyPath(tm).

One bit.

The majority of faults that prevent a FPGA from being perfectly good,
are just that, one fault, one bit.

One path missing (metal is open).

One bit that won't write.

One bit that won't read.

One LUT bit that can't be set.

One IO standard that isn't there.

Maybe you should go take a course on semiconductor manufacturing? Go
actually learn something?

Since we can't educate you, and you are unwilling to listen to us, maybe
you should go talk to someone you trust, and will listen to?

Austin
 
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
Aerospace posses issues with ionizing radiation.
Click to expand...
Xilinx has their QPRO line which is radiation tolerant for this market.
Aerospace was actually one of the earlier adopters of FPGAs for DSP
applications. I've built my business around this market and have
completed several designs specifically intended for low earth orbit
insertion. QPRO is not new, it has been around for close to a decade.
 
<fpga_toys@yahoo.com> wrote in message
news:1142618945.752008.15170@i40g2000cwc.googlegroups.com...
John_H wrote:
"dumping" is selling something below cost, not taking a lower margin than
premium, "perfect" products.

By their own statements, they do not screen the good parts first, so
depending on the wafer yield, a reasonable percentage of those are
parts ARE premium, "perfect" products being sold as low as 20% of the
normal price.
Click to expand...
Again, selling below MSRP is *not* dumping!

Dumping is selling parts below cost. We're talking negative margin here.

When xilinx writes a PO for 100k devices _from_the_fab_ at $N per device,
it's dumping if they sell that device for less than $N.
 
John_H wrote:

When xilinx writes a PO for 100k devices _from_the_fab_ at $N per device,
it's dumping if they sell that device for less than $N.
Click to expand...
if they were selling bare die, then $N would be correct.

They are however selling packaged and tested parts, so all standard
burdens, labor, buildings, IP, etc apply to the cost -- not just die
cost from the fab.
 
<fpga_toys@yahoo.com> wrote in message
news:1142619972.463368.89120@i40g2000cwc.googlegroups.com...
<snip>
We've heard a lot of whining about dropping non-profitable support ...
how long is a program going to last that ships as many perfect parts as
very slightly flawed parts?
Click to expand...
When the incremental sales are significant for a small percentage of Xilinx
customers, this program should have a long, happy existence.


Oh, and your flawless understanding of market dynamics has convinced me that
Xilinx is a bad investment. Yeah.
 
Without EasyPath any production device with any known defect (that is
not covered by an errata note) goes into the garbage can.
That has been and will remain our policy, and I assume the policy of
any reputable IC manufacturer.

EasyPath allows us to test only the relevant subset of the chip's
functionality (as needed by the specific user).
This increases yield for large devices significantly (hardly any gain
for small chips), and that higher yield means lower cost to us, and
supports a lower selling price. This should be understandable to
anybody with a high-school education.
Peter Alfke
 
Peter Alfke wrote:
Without EasyPath any production device with any known defect (that is
not covered by an errata note) goes into the garbage can.
That has been and will remain our policy, and I assume the policy of
any reputable IC manufacturer.
Click to expand...
Ahh ... an oldie moldie zero defect equals quality bigot. I thought all
those either retired or got laid off in hard times.

I can remember that same mantra in several industries, that all have
found that selling defect managment and a profitable seconds line is
the very key to improving sales and getting a better ROI for investors.
I remember the 1980's when the disk drive industry was going thru that
too. Just try and buy a half million zero defect drives today.

Maybe some stock holders aught to be asking your board why you are so
eager to crush into the can near perfect dies and packaged parts for a
single (or small number) of flaws that might easily bring another
10-50% in sales into users perfectly willing to purchase parts with
classified flaws they can design around.

I'm perfectly willing to design reconfigurable computers with a few
routing and LUT failures that we can map around with a defect list
keepaway table. I'd be even happy to get them as bare, but mountable
die.

Anybody else here that would be willing to purchase high end FPGA's for
reconfigurable computing with a few minor flaws? Since they are trash
to you, can I get several thousand XC4VLX200's at say a 90-95%
discount? hmm ... maybe that's to low an offer, and there is a bidding
war ready to errupt.
 
Subhasri krishnan wrote:

I am having problems debugging my memory controller. My initial idea is
to capture a frame and display the same frame continuously. But I see
problems in the pattern captured (some spots with colours that arent
expected to be there). When I simulate the controller it works as it is
expected. I understand that the timing has to be right and I modified
everything so that its alright.
Click to expand...
Verify that by running static timing at 100MHz.

I think that the problem lies with an asynchronous fifo used to buffer
data at 25Mhz.
Click to expand...
Consider syncing that interface to 100Mhz
and using a synch fifo.

Also
can i use 2 clocks in the same module?
Click to expand...
Not without working out synchronization at the boundaries.


-- Mike Treseler
 
John Williams' "Partial Reconfiguration on Xilinx Devices" email list is
another resource:
http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/

The archive is available here:
http://www.itee.uq.edu.au/~listarch/partial-reconfig/

scotto wrote:
Hello, Does anybody out there actually know how to set up HWICAP in EDK?
Has
anyone ever got this to work?

If you've ever looked into this, you know there's very little
documentation on how to setup and use HWICAP. Would someone please post a
C file instantiating, initializing, and perhaps even reading/writing a
frame through ICAP? That would be extremely helpful.

I am but a lowely univerisy student, and as such get zero support from
Xilinx
on these or any other matters.

Thanks much, --scott
Click to expand...
 
John,

Just wanted to be sure you were not on their pay roll.

I have been made a fool of once before thinking I was talking to a
potential customer when it was someone who was an actual competing
company employee...boy did I feel stupid.

Austin
 
fpga_toys@yahoo.com wrote:
If Ford decided to dump perfectly good Lincon's at 80% quoting they
were saving QC costs for the occasional scratch or miss alighed seat
frame, or what ever ... defectives ... we would laugh our heads off and
realize that it was a marketing ploy to dump product below market.
Click to expand...
That's not a good analogy for Easypath. Ford can repair manufacturing
defects at relatively low cost, compared to the total cost of the product.

Xilinx *might* be able to repair some bad dice by using FIB, but the
cost of doing so would significantly exceed the original cost of the
die, and although the result might be functional, it could not be
guaranteed to have comparable reliability to a normal part. Thus it
could not be sold except perhaps as an unqualified engineering sample.

Thus there is no motivation to do any sort of repair as part of the
production process, but rather to do everything possible to increase
the yield of fully functional parts. Still, for a large die, despite
their best efforts there will be some parts that are not fully
functional, but very nearly so (>99.999%). Unfortunately these cannot
be sold as normal FPGA product.

With Easypath the customer is not informed of the specific nature of the
defect(s) of the parts they receive; the parts might even be 100%
functional, but are not guaranteed as such. In fact Xilinx might not
even be aware of all of the defects; they have tested the part against
vectors that verify that it meets all relevant specifications with
regard only to the specific customer configuration bitstream.

Finally, they aren't "dumping", which would be selling below cost. They
are likely making quite a tidy profit on Easypath, since although the
price is lower than for a fully tested FPGA, the cost is also lower.
Time on a semiconductor tester is very expensive, thus anything that
reduced the test time significantly reduces the total part cost.
 
rickman wrote:
Now I realize that
Xilinx as a whole is not a lot different than the image you present and
it bothers me. It bothers me enough that I now have a strong
preference for any other FPGA manufacturer.

I think the fact that no one at Xilinx seems to have a problem with
your posts like this one says a lot about the company.
Click to expand...
Rickman, Austin is not alone in posting outspoken comments. You are no
slouch yourself !
Luckily, Xilinx is not a monolithic dictatorship, and the company
trusts its senior employees to post in this newsgroup without
censorship and without reprimands.

Austin and I give fast response, to the best of our knowledge (which is
quite extensive), but we are not always politically correct, and both
of us have a temper that can indeed be provoked by certain stupidities
repeatedly voiced on this newsgroup. We handle complex and sometimes
controversial subjects with engagement and also some humor.
We are not the official "Voice of Xilinx". You get that from Marketing
and in press releases.

I would be amazed if any smart engineer would base his component choice
on Austin's typing style. We would, however, appreciate if you base it
on the technical information you get in this newsgoup.
Peter Alfke, Xilinx Applications
 
Eric Smith wrote:
fpga_toys@yahoo.com wrote:
If Ford decided to dump perfectly good Lincon's at 80% quoting they
were saving QC costs for the occasional scratch or miss alighed seat
frame, or what ever ... defectives ... we would laugh our heads off and
realize that it was a marketing ploy to dump product below market.

That's not a good analogy for Easypath. Ford can repair manufacturing
defects at relatively low cost, compared to the total cost of the product.
Click to expand...
Actually the point was Ford not even checking, and shipping it AS-IS, a
little stronger point that Xilinx partially testing.

Xilinx *might* be able to repair some bad dice by using FIB, but the
cost of doing so would significantly exceed the original cost of the
die, and although the result might be functional, it could not be
guaranteed to have comparable reliability to a normal part. Thus it
could not be sold except perhaps as an unqualified engineering sample.
Click to expand...
Repair of defects is completely a different topic.

Finally, they aren't "dumping", which would be selling below cost. They
are likely making quite a tidy profit on Easypath, since although the
price is lower than for a fully tested FPGA, the cost is also lower.
Time on a semiconductor tester is very expensive, thus anything that
reduced the test time significantly reduces the total part cost.
Click to expand...
Tell the stock holders that when they put sellable "bad" dice in the
trash can, and ship good dice which were not fully tested for a heavy
discount, that CAN drop below the "cost" of a good die. There are two
lost profits in this business plan ... shipping good die at less than
cost, and trashing usable die that would qualify under an easypath
shipment. The sum of these two failures, is easily worth a significant
fraction of Xilinx's current revenue, and the management finders fee
(AKA bounus) for correcting this is probably more than most people will
retire with.

My finders fee is a lot less .... a briefcase full of discarded
XC4VLX200's which currently don't have any value and they probably have
to pay to get destroyed and hauled off.
 
Austin Lesea wrote:
Just wanted to be sure you were not on their pay roll.

I have been made a fool of once before thinking I was talking to a
potential customer when it was someone who was an actual competing
company employee...boy did I feel stupid.
Click to expand...
Ouch ... talk about getting baited :(

Nope ... I don't even know an Altera person. I do know or have met
several Xilinx people who have always been great people to deal with.
Every time I've been against the wall, there's been a Xilinx FAE to
help. Field staff always seem to have great customer skills.
 
In article <6a2e9f084e.tank@tankstage.co.uk>,
Tank <webmaster@tankstage.co.uk> wrote:

In message <ifmi1218qkjo36fnvf3mk21p6n2k4mv39m@4ax.com
John C <brakepiston@yahoo.co.uk> wrote:

Reading the LSI Strucutred ASIC fiasco thread has made me think.
People are saying the FPGA revenues are going to grow, so....

Which markets are FPGA heading into?

I mean, at the moment there's Comms, Medical, Military, Consumer.

Where are they going next?

Automotive I guess is coming, as is aerospace. You could put the two
together, as control electronics.

How about seeing them in a PC?

See http://www.microdigital.info

Altho the company seems to have ceased trading, there are a few of us who
have units.
It uses Spartan xc2s200's, one to implement a northbridge and one as a
memory controller and graphic engine. A xc95144 is used to boot them and
provide memory control.
NOTE this is not a windows machine, but is a RISCOS (http://www.riscos.com)
machine with an ARM based processor.



What are your views on the matter?
Click to expand...


Their web site is also non functional. Sounds interesting tho,
something like what i wanted to do. Multiple FPGA's on a 'pc' like
board. One for the cpu(s), one for video, another to handle all the
ports and drive communications.

Wont be any speed demon, but might be fun.
 
In article <bvtj129bi3tecrbann43si35dhcc35nt4a@4ax.com>,
metal <nospam@spaam.edu> wrote:

On Thu, 16 Mar 2006 12:33:27 +0000, John C <brakepiston@yahoo.co.uk
wrote:

Reading the LSI Strucutred ASIC fiasco thread has made me think.
People are saying the FPGA revenues are going to grow, so....

Which markets are FPGA heading into?

I mean, at the moment there's Comms, Medical, Military, Consumer.

Where are they going next?

Automotive I guess is coming, as is aerospace. You could put the two
together, as control electronics.

How about seeing them in a PC?

What are your views on the matter?

hmm....looking at the writing on the wall economically....

PC-mkt: no growth...expect a decline.

mil/aero: a new slaughter every year should keep this going; but
overall volume is questionable....

*snip*
Click to expand...

Lets hope you are a bit wrong, would hate to see FPGA companies start to
fold.. There really arent many to start with.

But i do agree with you, except for use in development of ASIC's is
there really a *true* market?

And is that market enough to keep things afloat for us hobbiests?
 
Do yourself and everybody on this newsgoup a favor and get rid of these
chips in an environmentally acceptable way.
Then overcome your frugality and spend a few dollars on a modern chip
evaluation board. Spartan3 or 3E comes to mind.
You will get ever so much more enjoyment out of that choice.
The XC3042 was introduced in 1988, 17 years ago. According to my 15:1
rule, that makes it the equivalent of a 255 year old senior citizen.
Would you ask that tottering poor guy to do your work?
The silicon would work perfectly, but is small and slow. The software
is no longer supported and is slow and clumsy and only runs on archaic
computers. Forget it.

Peter Alfke, Xilinx.
 
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