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middle, can't take either side but yet, his lines seem to break left orOn Fri, 19 Oct 2012 15:02:51 -0700 (PDT), Bill Sloman
bill.sloman@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
The real nuisance in a DDS is the damned lowpass filter.
VCOs can be a lot better, and VCXOs hugely better.
Slugman is like the yellow line on the road, he's always in the
That exchange was you, me, you. You tested it and according to the email itOn Fri, 19 Oct 2012 08:09:38 -0400, "Tom Del Rosso"
td_03@verizon.net.invalid> wrote:
Jim Thompson wrote:
Taking note that I'm not a logic designer, I'm not sure your
version covers all states.
It passed your sim with slightly different frequencies at each
input to create a walking phase shift.
You did need to match the gates. If they were simmed as discrete
7400's then you had to take the 4 on the left from one package.
It took Ron Treadway NINE gates back in the
mid-60's in the MC4044...
http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
I know. That's why I was surprised it worked with 8 as quoted:
==========quote==========
Newsgroups:
alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc
Sent: Monday, August 27, 2001 10:26 PM
Subject: Re: Help an Analog Guy with a Digital Problem
The internal feedback disabled the pulse too soon. The resulting
pulse width at the final latch was about 1/2 of what it is with
feedback from the output (~2.5nS vs 5nS).
Ok. So was your testing of the last circuit sucessful under full
load?
You bet...you're now in a product...E-Mail for details.
=========================
Thanks, Tom! I'll have to try that. Does it have deadband?
Someone who wants to do a lot of DDS PLLs in an FPGA, without goingOn Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
We don't use standard DDS chips very often. We do our own DDS logic inif your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html#Direct_Digital_Synthesis
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
The filter takes a lot more area, and does often cost more.DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
What an ass you are. I got my EE degree before DDS was invented, andThe real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
Obviously. but what sort of idiot would use one that way? Of course,On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Actually, as long as the DAC refresh time is shorter than your lowDAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
You should have paid closer attention during the relevant lecturesThe real nuisance in a DDS is the damned lowpass filter.
Only if you find low-pass filters intimidatingVCOs can be a lot better,
VCXO do - however - tend to be rather restricted in the frequenciesand VCXOs hugely better.
That's Jamie for you. John Larkin makes a fool of himself and JamieJohn Larkin wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
The real nuisance in a DDS is the damned lowpass filter.
VCOs can be a lot better, and VCXOs hugely better.
Slugman is like the yellow line on the road, he's always in the
middle, can't take either side but yet, his lines seem to break left or
right at every turning post.
He just can't maintain solid facts or lines.
I'm not designing much electronics a the moment, but I didn't need toOn Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
If you've built the logic part of the DDS chip into a corner of anDAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
Only if your low pass filter cuts off at too high a frequency. ThisAt low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus.
It's not the plateau that trips the comparator, but the noise on theThe plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter.
The DDS chips would be built with a logic process, while the filterAs I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
I never got an EE degree, and learned the stuff when I needed it - andThe real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
None. I've been out of work aka retired for the last ten years, as youHow many DDS synthesizers have you designed in the last 10 years?
Nothing that got built. I still managed to get my head around the ideaI've done a dozen or so. Hell, have you ever designed a DDS into something?
On Oct 20, 10:59 am, Jamie
jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
John Larkin wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
The real nuisance in a DDS is the damned lowpass filter.
VCOs can be a lot better, and VCXOs hugely better.
Slugman is like the yellow line on the road, he's always in the
middle, can't take either side but yet, his lines seem to break left or
right at every turning post.
He just can't maintain solid facts or lines.
That's Jamie for you. John Larkin makes a fool of himself and Jamie
chimes in to tell us that he too is intellectually limited - as if we
didn't already know.
--
Bill Sloman, Sydney
Actually, it's quite the opposite. Good show.
I can say one thing about slugman, it does not usually impersonate thatOn Fri, 19 Oct 2012 21:01:19 -0700 (PDT), Bill Sloman
bill.sloman@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html#Direct_Digital_Synthesis
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus. The
plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter. As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
"Ought to" means that you are following hearsay. We use filters whenOn Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.
Please design a suitable tunable, adaptive filter and post it here.DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
If you've built the logic part of the DDS chip into a corner of an
FPGA this could well be true. No DAc and no filter sounds like taking
economy a little too far.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus.
Only if your low pass filter cuts off at too high a frequency. This
does depend on the frequency range you want to cover, and if you were
going nuts you might look at ways of moving the 3dB point of the low
pass filter around to cover a really wide frequency range.
Or its residual slope.The plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter.
It's not the plateau that trips the comparator, but the noise on the
plateau.
Idiot. Hysteresis won't help the jitter at all.shouldn't have to point this out to someone with your extravagantly
practiced expertise.
Their full company name is Analog Devices.As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The DDS chips would be built with a logic process, while the filter
could be expected to be analog.
It escapes you because you don't actually design DDSs or theirup a FIR filter could be interesting, but it would use up a lot of
pins.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I never got an EE degree, and learned the stuff when I needed it - and
read up on it from time to time when I needed more.
Low pass filters aren't either complicated or difficult. Why you feel
the need to describe them as "damned" escapes me.
That seems to be your history, designing stuff that doesn't get built.How many DDS synthesizers have you designed in the last 10 years?
None. I've been out of work aka retired for the last ten years, as you
well know
I've done a dozen or so. Hell, have you ever designed a DDS into something?
Nothing that got built.
Jamie may be slow, but he's persistent. Pity about the direction.John Larkin wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds....
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus. The
plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter. As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I can say one thing about slugman, it does not usually impersonate that
often, he's doing very well at being himself, the ASS.
On Fri, 19 Oct 2012 22:54:37 -0700 (PDT), Bill Sloman
bill.sloman@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.
"Ought to" means that you are following hearsay. We use filters when
it makes sense.
It's bad enough that you make statements that are uninformed or wrong,
but you have to phrase them as personal insults.
Your story about applying for work at ASML summarizes the situation:
your are way to obnoxious for your own good.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
If you've built the logic part of the DDS chip into a corner of an
FPGA this could well be true. No DAc and no filter sounds like taking
economy a little too far.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus.
Only if your low pass filter cuts off at too high a frequency. This
does depend on the frequency range you want to cover, and if you were
going nuts you might look at ways of moving the 3dB point of the low
pass filter around to cover a really wide frequency range.
Please design a suitable tunable, adaptive filter and post it here.
Cutoff from, say, 45 KHz to 45 MHz, glitch-free tuning. 7 poles would
be adequate.
The plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter.
It's not the plateau that trips the comparator, but the noise on the
plateau.
Or its residual slope.
A little hysteresis around the comparator might help, but I
shouldn't have to point this out to someone with your extravagantly
practiced expertise.
Idiot. Hysteresis won't help the jitter at all.
What does help a bit is digital interpolation, between lookup table
entries, at the full clock rate. We do that in several of our
products. It is especually useful in products that have multiple DDSs
on chip and allow cross-synthesizer moddulations, like our V346. Any
DDS can AM/FM/PM any other, in compound paths. All the modulations are
on-chip, and only the final outputs have DACs and filters.
As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The DDS chips would be built with a logic process, while the filter
could be expected to be analog.
Their full company name is Analog Devices.
A delay line that could be used to set
up a FIR filter could be interesting, but it would use up a lot of
pins.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I never got an EE degree, and learned the stuff when I needed it - and
read up on it from time to time when I needed more.
Low pass filters aren't either complicated or difficult. Why you feel
the need to describe them as "damned" escapes me.
It escapes you because you don't actually design DDSs or their
filters.
How many DDS synthesizers have you designed in the last 10 years?
None. I've been out of work aka retired for the last ten years, as you
well know
I've done a dozen or so. Hell, have you ever designed a DDS into something?
Nothing that got built.
That seems to be your history, designing stuff that doesn't get built.
Get an ADI DDS eval board and learn something.
Seven dollars! It looks like it includes a 7-pole elliptic LC filter,John Larkin wrote:
On Fri, 19 Oct 2012 22:54:37 -0700 (PDT), Bill Sloman
bill.sloman@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.
"Ought to" means that you are following hearsay. We use filters when
it makes sense.
It's bad enough that you make statements that are uninformed or wrong,
but you have to phrase them as personal insults.
Your story about applying for work at ASML summarizes the situation:
your are way to obnoxious for your own good.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
If you've built the logic part of the DDS chip into a corner of an
FPGA this could well be true. No DAc and no filter sounds like taking
economy a little too far.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus.
Only if your low pass filter cuts off at too high a frequency. This
does depend on the frequency range you want to cover, and if you were
going nuts you might look at ways of moving the 3dB point of the low
pass filter around to cover a really wide frequency range.
Please design a suitable tunable, adaptive filter and post it here.
Cutoff from, say, 45 KHz to 45 MHz, glitch-free tuning. 7 poles would
be adequate.
The plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter.
It's not the plateau that trips the comparator, but the noise on the
plateau.
Or its residual slope.
A little hysteresis around the comparator might help, but I
shouldn't have to point this out to someone with your extravagantly
practiced expertise.
Idiot. Hysteresis won't help the jitter at all.
What does help a bit is digital interpolation, between lookup table
entries, at the full clock rate. We do that in several of our
products. It is especually useful in products that have multiple DDSs
on chip and allow cross-synthesizer moddulations, like our V346. Any
DDS can AM/FM/PM any other, in compound paths. All the modulations are
on-chip, and only the final outputs have DACs and filters.
As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The DDS chips would be built with a logic process, while the filter
could be expected to be analog.
Their full company name is Analog Devices.
A delay line that could be used to set
up a FIR filter could be interesting, but it would use up a lot of
pins.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I never got an EE degree, and learned the stuff when I needed it - and
read up on it from time to time when I needed more.
Low pass filters aren't either complicated or difficult. Why you feel
the need to describe them as "damned" escapes me.
It escapes you because you don't actually design DDSs or their
filters.
How many DDS synthesizers have you designed in the last 10 years?
None. I've been out of work aka retired for the last ten years, as you
well know
I've done a dozen or so. Hell, have you ever designed a DDS into something?
Nothing that got built.
That seems to be your history, designing stuff that doesn't get built.
Get an ADI DDS eval board and learn something.
http://www.ebay.com/itm/280840956721
"As is", that produces a linear ramp of current from 0 to 1 mA, inSuppose, in PSpice, I have a behavioral current source that "quits" unless
it has at least 0.5V across it...
GDC_I1 N_1 N_2 VALUE {(1+TANH(2.2/0.1*(V(N_1,N_2)-0.5)))/2*1mA}
Can LTspice understand that line "as is", or must it be changed?
If it must be changed, what is the proper syntax?
Thanks!
view of you using this place as a dumping ground.On Oct 20, 11:58 pm, Jamie
jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
John Larkin wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus. The
plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter. As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I can say one thing about slugman, it does not usually impersonate that
often, he's doing very well at being himself, the ASS.
Jamie may be slow, but he's persistent. Pity about the direction.
--
Bill Sloman, Sydney
There is no amount of bull shit you can spread here that would change my
On Sat, 20 Oct 2012 13:11:08 -0400, "Michael A. Terrell"
mike.terrell@earthlink.net> wrote:
John Larkin wrote:
On Fri, 19 Oct 2012 22:54:37 -0700 (PDT), Bill Sloman
bill.sloman@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.
"Ought to" means that you are following hearsay. We use filters when
it makes sense.
It's bad enough that you make statements that are uninformed or wrong,
but you have to phrase them as personal insults.
Your story about applying for work at ASML summarizes the situation:
your are way to obnoxious for your own good.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
If you've built the logic part of the DDS chip into a corner of an
FPGA this could well be true. No DAc and no filter sounds like taking
economy a little too far.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus.
Only if your low pass filter cuts off at too high a frequency. This
does depend on the frequency range you want to cover, and if you were
going nuts you might look at ways of moving the 3dB point of the low
pass filter around to cover a really wide frequency range.
Please design a suitable tunable, adaptive filter and post it here.
Cutoff from, say, 45 KHz to 45 MHz, glitch-free tuning. 7 poles would
be adequate.
The plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter.
It's not the plateau that trips the comparator, but the noise on the
plateau.
Or its residual slope.
A little hysteresis around the comparator might help, but I
shouldn't have to point this out to someone with your extravagantly
practiced expertise.
Idiot. Hysteresis won't help the jitter at all.
What does help a bit is digital interpolation, between lookup table
entries, at the full clock rate. We do that in several of our
products. It is especually useful in products that have multiple DDSs
on chip and allow cross-synthesizer moddulations, like our V346. Any
DDS can AM/FM/PM any other, in compound paths. All the modulations are
on-chip, and only the final outputs have DACs and filters.
As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The DDS chips would be built with a logic process, while the filter
could be expected to be analog.
Their full company name is Analog Devices.
A delay line that could be used to set
up a FIR filter could be interesting, but it would use up a lot of
pins.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I never got an EE degree, and learned the stuff when I needed it - and
read up on it from time to time when I needed more.
Low pass filters aren't either complicated or difficult. Why you feel
the need to describe them as "damned" escapes me.
It escapes you because you don't actually design DDSs or their
filters.
How many DDS synthesizers have you designed in the last 10 years?
None. I've been out of work aka retired for the last ten years, as you
well know
I've done a dozen or so. Hell, have you ever designed a DDS into something?
Nothing that got built.
That seems to be your history, designing stuff that doesn't get built.
Get an ADI DDS eval board and learn something.
http://www.ebay.com/itm/280840956721
Seven dollars! It looks like it includes a 7-pole elliptic LC filter,
too.
One can usually get an eval board for free, from an ADI rep. But you'd
have to sound competant and friendly, which would both be difficult
for Sloman.
Sounds to me that he did his job very well.On Oct 21, 2:53 am, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds...
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.
"Ought to" means that you are following hearsay. We use filters when
it makes sense.
"Hearsay" is this context, is body of electronic knowledge that
motivated the development of the DDS approach. An accumulator
generates a sequence of digital phase values for the sine wave being
synthesised, a look-up table turns this into a sequency of digital
amplitudes, and a DAC turns this into a sequence of analog voltages
(or currents), which ias a staircase approximation to the desired
waveform. The Fourier transform of this waveform includes the desired
fundamental and the undesired high frequency artifacts representing
the steps in the staircase, which you can filter out to any desired
degree with a suitable low pass filter.
All hearsay, until you build the hardware, but peculiarly reliable
hearsay.
It's bad enough that you make statements that are uninformed or wrong,
but you have to phrase them as personal insults.
You do find personal insults where most people would merely find
colourful language.
Your story about applying for work at ASML summarizes the situation:
your are way to obnoxious for your own good.
I upset the personal department by going behind their backs to talk to
an engineer that I'd been interviewed by earlier. Personnel
departments aren't good at evaluating engineers. Good ones know it and
don't get too upset about being by-passed. Bad ones know it too but
hate being reminded that they aren't as clever as they like to think.
At ASML it looks as if the guy in charge was more interested in
defending his right to act as a gatekeeper than in getting the right
people through the gate.
"Hearsay" is this context, is body of electronic knowledge thatOn Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz internal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds....
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
I'm not designing much electronics a the moment, but I didn't need to
be reminded that you ought to filter the output of a DDS chip.
"Ought to" means that you are following hearsay. We use filters when
it makes sense.
You do find personal insults where most people would merely findIt's bad enough that you make statements that are uninformed or wrong,
but you have to phrase them as personal insults.
I upset the personal department by going behind their backs to talk toYour story about applying for work at ASML summarizes the situation:
your are way to obnoxious for your own good.
What - precisely - is the application? The obvious solution would beDAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
If you've built the logic part of the DDS chip into a corner of an
FPGA this could well be true. No DAc and no filter sounds like taking
economy a little too far.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus.
Only if your low pass filter cuts off at too high a frequency. This
does depend on the frequency range you want to cover, and if you were
going nuts you might look at ways of moving the 3dB point of the low
pass filter around to cover a really wide frequency range.
Please design a suitable tunable, adaptive filter and post it here.
Cutoff from, say, 45 KHz to 45 MHz, glitch-free tuning. 7 poles would
be adequate.
Some devices do have a specified minimum slew rate for reliableThe plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter.
It's not the plateau that trips the comparator, but the noise on the
plateau.
Or its residual slope.
If the comparator flips repeatedly as the waveform goes through 0V (orA little hysteresis around the comparator might help, but I
shouldn't have to point this out to someone with your extravagantly
practiced expertise.
Idiot. Hysteresis won't help the jitter at all.
Digitally interpolating what, where? I presume you are using multipleWhat does help a bit is digital interpolation, between lookup table
entries, at the full clock rate. We do that in several of our
products. It is especually useful in products that have multiple DDSs
on chip and allow cross-synthesizer moddulations, like our V346. Any
DDS can AM/FM/PM any other, in compound paths. All the modulations are
on-chip, and only the final outputs have DACs and filters.
The term "process" refers to the sequence of operations used toAs I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The DDS chips would be built with a logic process, while the filter
could be expected to be analog.
Their full company name is Analog Devices.
I've designed quite enough filters to appreciate where it getsA delay line that could be used to set
up a FIR filter could be interesting, but it would use up a lot of
pins.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I never got an EE degree, and learned the stuff when I needed it - and
read up on it from time to time when I needed more.
Low pass filters aren't either complicated or difficult. Why you feel
the need to describe them as "damned" escapes me.
It escapes you because you don't actually design DDSs or their
filters.
It's not the whole of my history by any means. The electron beamHow many DDS synthesizers have you designed in the last 10 years?
None. I've been out of work aka retired for the last ten years, as you
well know
I've done a dozen or so. Hell, have you ever designed a DDS into something?
Nothing that got built.
That seems to be your history, designing stuff that doesn't get built.
If I had a potential customer for the knowledge that I might acquire,Get an ADI DDS eval board and learn something.
<snip>On Sat, 20 Oct 2012 13:11:08 -0400, "Michael A. Terrell"
mike.terr...@earthlink.net> wrote:
John Larkin wrote:
On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
They seemed friendly enough at the last Analog Devices seminar IGet an ADI DDS eval board and learn something.
http://www.ebay.com/itm/280840956721
Seven dollars! It looks like it includes a 7-pole elliptic LC filter,
too.
One can usually get an eval board for free, from an ADI rep. But you'd
have to sound competent and friendly, which would both be difficult
for Sloman.
<snip>John Larkin wrote:
On Sat, 20 Oct 2012 13:11:08 -0400, "Michael A. Terrell"
mike.terr...@earthlink.net> wrote:
John Larkin wrote:
On Fri, 19 Oct 2012 22:54:37 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 3:58 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
Mike Terrell's can't imagine that I've got more money than he has. IfGet an ADI DDS eval board and learn something.
http://www.ebay.com/itm/280840956721
Seven dollars! It looks like it includes a 7-pole elliptic LC filter,
too.
One can usually get an eval board for free, from an ADI rep. But you'd
have to sound competant and friendly, which would both be difficult
for Sloman.
Now, all he has to do is collect enough empty beer cans to pay for
it.
Jamie can't tell shit from shinola., and has no inhibitions aboutBillSlomanwrote:
On Oct 20, 11:58 pm, Jamie
jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
John Larkin wrote:
On Fri, 19 Oct 2012 21:01:19 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 20, 10:35 am, John Larkin <jlar...@highlandtechnology.com
wrote:
On Fri, 19 Oct 2012 15:02:51 -0700 (PDT),BillSloman
bill.slo...@ieee.org> wrote:
On Oct 19, 11:59 pm, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
BillSlomanwrote:
On Oct 19, 4:00 am, Phil Hobbs
pcdhSpamMeSensel...@electrooptical.net> wrote:
snip
My usual use for PLLs is
demodulation rather than frequency synthesis, so DDSes are pretty much
beside the point.
Why?
Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.
Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.
DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter.
Obviously. but what sort of idiot would use one that way?
Someone who wants to do a lot of DDS PLLs in an FPGA, without going
off chip to DACS and filters and comparators.
Of course,
if your DDS has a 500MHz inrternal clock, 2nsec of jitter might be
tolerable.
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds....
When I mentioned DDS's earlier in this thread I did mention that you
ought to filter the output, but I'd figured that people like you and
Phil Hobbs wouldn't need to be reminded.
We don't use standard DDS chips very often. We do our own DDS logic in
an FPGA, and sometimes use the MSB on-chip, sometimes go to a fast DAC
off-chip.
But reminded? By you? I design electronics, and you don't.
DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.
Actually, as long as the DAC refresh time is shorter than your low
pass filter 3dB point, you should do appreciably better than the DAC
resolution.
The "noise" on a pure staircase waveform is essentially a sawtooth
wave at the DAC refresh rate, and that ought to be a lot faster than
the frequency you are interested in, and correspondingly easy to
filter out. Four or six poles of low pass filter isn't going to cost
anything like as much as the DDS chip.
The filter takes a lot more area, and does often cost more.
At low frequencies, the filter output settles between phase
accumulator code transitions, so the waveform has plateaus. The
plateaus trip the comparator at fuzzy levels, so you get a lot of
jitter. As I said, period jitter of about 1/20000 RMS is typical for a
16 bit system. One trick is to keep the DDS frequency high, so the
filter stays in its sweet spot, and divide down after the comparator.
I don't understand why ADI makes so many DDS chips, but doesn't make
an integrated lowpass filter.
The real nuisance in a DDS is the damned lowpass filter.
You should have paid closer attention during the relevant lectures
What an ass you are. I got my EE degree before DDS was invented, and
you are even older than I am.
I can say one thing about slugman, it does not usually impersonate that
often, he's doing very well at being himself, the ASS.
Jamie may be slow, but he's persistent. Pity about the direction.
There is no amount of bull shit you can spread here that would change my
view of you using this place as a dumping ground.
Polluting is illegal in most places around the world.