EAGLE Netlist conversion

Robert Baer · Mar 30, 2005

Paul Burke wrote:

Robert Baer wrote:

If i remember correctly, TI had a dual comparitor with on-pin control.
Get nasty, log to DigiKey and try key-words like "comparitor".

Might do better with 'comparator'

Paul Burke
So, i am not only dyslexic on typing,but also badd on making witches

spells (err...spelling).

Leon Heller · Mar 30, 2005

"eeh" <eehobbyist@yahoo.com.hk> wrote in message
news:1112187223.260940.152400@f14g2000cwb.googlegroups.com...

I want to ask a question:

I am doing a project which needs a DSP chip with BGA package. It has
272 pins. Is double layer PCB enough for routing?

You'll need at least six layers!

Leon

James Morrison · Mar 30, 2005

On Wed, 2005-03-30 at 04:53 -0800, eeh wrote:

I want to ask a question:

I am doing a project which needs a DSP chip with BGA package. It has
272 pins. Is double layer PCB enough for routing?

If you need a DSP then presumably you need it because it needs to crunch
numbers. In that case you're going to need a good power and ground
plane and power distribution network. So two layers is certainly not
enough.

The number of layers you'll need depends on how the 272 balls are
configured on the package and how the signals go to those balls.

Analog devices has a 576-ball BGA in which there are only I/O signals on
the outer 4 layers around the outside of the BGA. The inside is all
ground and power pins. This makes breakout much easier. I was able to
lay that out with 4 signal layers. It could have been done with
2-layers with a few of the system requirements relaxed.

Other determining factors are what trace widths and separation rules you
can use/afford with your board shop and the pitch of the 272 balls, the
size of the overall board assembly, the pitch of the BGA balls, the via
drill size, the annular ring size, ....

If you could route the signals on two layers then at a bare minimum
you'll need 4-layers. I would imagine that will more than likely become
6-layers and quite possibly 8-layers. The board I did with 4 layers of
routing also had 4 layers of power/ground planes for a total of 8.

Take this as a reference only. Without knowing the rest of the details
I can only speculate. YMMV.

Cheers.

Mar 31, 2005

On Wed, 30 Mar 2005 16:22:12 -0500, James Morrison
<spam1@emorrison.ca> wrote:

On Wed, 2005-03-30 at 04:53 -0800, eeh wrote:
I want to ask a question:

I am doing a project which needs a DSP chip with BGA package. It
has
272 pins. Is double layer PCB enough for routing?

If you need a DSP then presumably you need it because it needs to
crunch
numbers. In that case you're going to need a good power and ground
plane and power distribution network. So two layers is certainly
not
enough.

The number of layers you'll need depends on how the 272 balls are
configured on the package and how the signals go to those balls.

Analog devices has a 576-ball BGA in which there are only I/O
signals on
the outer 4 layers around the outside of the BGA. The inside is
all
ground and power pins. This makes breakout much easier. I was
able to
lay that out with 4 signal layers. It could have been done with
2-layers with a few of the system requirements relaxed.

Other determining factors are what trace widths and separation
rules you
can use/afford with your board shop and the pitch of the 272 balls,
the
size of the overall board assembly, the pitch of the BGA balls, the
via
drill size, the annular ring size, ....

If you could route the signals on two layers then at a bare minimum
you'll need 4-layers. I would imagine that will more than likely
become
6-layers and quite possibly 8-layers. The board I did with 4
layers of
routing also had 4 layers of power/ground planes for a total of 8.

Take this as a reference only. Without knowing the rest of the
details
I can only speculate. YMMV.

Cheers.

You need to consider all of that, plus the characteristic trace
impedance and termination strategy. Also power plane decoupling. I
would not ever try this on a two layer board, plus I would thrash an
engineer who suggested it!

Brad Velander · Mar 31, 2005

Andy,
I don't have the document to send you but all PADs installs
have either a Help file or a separate document file that
describes the ASCII format completely. Ask a PADs user to look
for it for you. I believe that these days it is in the Help
system somewhere, used to be it was a separate document found in
one of the install directories.

--
Sincerely,
Brad Velander

"Andy Lintz" <al@ppsystems.com> wrote in message
news:1112196521.216137.194250@z14g2000cwz.googlegroups.com...

Does anyone have a document that described the Pads Ascii file
format?

I am a Protel user trying to import a large Pads PowerPCB V3.5
Ascii
file. It imports 99% correctly, all except the split planes.
If I
understood the Pads Ascii data a little better (particularly
the x and
y coordinate values and the various split plane settings), I am
pretty
sure I can tweak the file to get it to import 100% properly.
Thanks,
Andy

Guy Macon · Apr 10, 2005

The same item is $323.00+$0.00 instead of $254.95+$16.00 here:
[ http://www.hmcelectronics.com/cgi-bin/scripts/product/3080-0045 ]
That's $52 less. (Feel free to send me $20 for telling you this

)

Or you can simply buy a set of BK Precision TL 8 Tweezer Test Leads
[ http://www.testequipmentdepot.com/b+k%20precision/bktestleads.htm#TL-8 ]
or [ http://www.bkprecision.com/showproduct.asp?pn=TL%208 ].
for $25 and use a *good* DMM.

Robert Baer wrote:

kolotun@gmail.com wrote:

http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&category=25412&item=7506323975

When posting ebay URLs, do it like this:

<http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=7506323975>

1) For the size, Priority Mail Flat Rate is $3.85;

You are applying US shipping rates to a Canadian seller.

$10 is typical shipping and handling for an eBay seller. The person
doing the shipping doesn't work for nothing, packing material costs
a bit, etc. $16 for the first one and $5 for the second isn't out of
line. By comparison, Contact East has these shipping rates for the
same product at the same price:
http://www.contacteast.com/product/group.asp?parent_id=11165
http://www.contacteast.com/help/shipping-rates.asp
FedEx Ground $10.49
FedEx 2-Day $17.99
FedEx Standard Overnight $18.99
U.S.P.S. Parcel Post $11.99
U.S.P.S. Priority Mail $20.99

Now i see their specs; the
best is 1%, which absolutely KILLs 5 digits and underscores my
3 digit statement above.

I see the hoopla concerning Ac waveforms, but one must note that
there is *no* specification concerning AC!

There are other problems with the spec:

"DC Voltage: 0 to 800 mV (Up to 8V with
optional slide switch manual setting)"

That's a quite low voltage. They don't give maximums (another
warning sign); will a cap charged to 5V or 12V kill it? I also
wonder about the claimed 1uH-1H 10pF-900mF ranges.

There has been some online speculation based on zooming in on the
JPEG of the board that this item uses and AD9833 / CMOS switch
to make quadrature phase measurements. If you get one, please
open it up and post all of the part numbers. With that info,
any of the sci.electronics.design regulars can tell you the real
performance specs.

--
Guy Macon
<a href="http://www.guymacon.com/">
http://www.guymacon.com/
</a>

Graham Holloway · Apr 20, 2005

<r1y2g3@sina.com> wrote in message
news:1114006853.164531.239240@g14g2000cwa.googlegroups.com...

Dear Sir:
When I DRC in Protel DXP I get much this message
"[Un-Routed Net Constraint Violation] PCB1_998.PcbDoc Advanced PCB Net
DSP_AAOE
Warning - net contains unplated pads "

Someone can help me? thanks a lot!

I suspect that your routing involves a track that passes though a pad from
one layer to another. Verify that the pad(s) involved are plated through.

Graham Holloway
WPS/Accuphon Audio

Peter Bennett · Apr 21, 2005

On 20 Apr 2005 07:20:53 -0700, r1y2g3@sina.com wrote:

Dear Sir:
When I DRC in Protel DXP I get much this message
"[Un-Routed Net Constraint Violation] PCB1_998.PcbDoc Advanced PCB Net
DSP_AAOE
Warning - net contains unplated pads "

Someone can help me? thanks a lot!

Find the guilty pads and make them plated....

In Protel, even surface mount pads must be declared as "plated", with
a hole size of zero.

--
Peter Bennett, VE7CEI
peterbb4 (at) interchange.ubc.ca
new newsgroup users info : http://vancouver-webpages.com/nnq
GPS and NMEA info: http://vancouver-webpages.com/peter
Vancouver Power Squadron: http://vancouver.powersquadron.ca

Simon Peacock · Apr 21, 2005

you will have to look and see if its a problem. Usually they aren't, but
its best to move the split plane boarder by 10 thou to get rid of the error
so the next guy doesn't get it too.

And you should never disable DRC options.. except for component clearance
and acute angles.

Simon

<r1y2g3@sina.com> wrote in message
news:1114050055.580918.281160@o13g2000cwo.googlegroups.com...

Thanks Graham Holloway and Peter Bennett.
The problem had solved just as you said.

I have a new problem in DRC message
"Warning - Pad/Via touching plane splitting primitives"
Although I can disenable this option in DRC'option,But I want to know
if this is a really problem.
Can someone give me some advisement. Thanks

Peter Bennett · Apr 21, 2005

On Thu, 21 Apr 2005 21:27:46 +1200, "Simon Peacock"
<nowhere@to.be.found> wrote:

you will have to look and see if its a problem. Usually they aren't, but
its best to move the split plane boarder by 10 thou to get rid of the error
so the next guy doesn't get it too.

And you should never disable DRC options.. except for component clearance
and acute angles.

It is sometimes impossible to get rid of all DRC errors. It is OK to
have some on a finished board, as long as you know _why_ they are
there, and are sure the board is the way you want.

Having DRC errors does not prevent you from finishing the design
process and producing Gerber and drill files.

--
Peter Bennett VE7CEI
email: peterbb4 (at) interchange.ubc.ca
GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html
Newsgroup new user info: http://vancouver-webpages.com/nnq

Ariane · Apr 21, 2005

Hi, hier sind meine geilen Bilder!
My nude Pics!!!
http://www.geile-tipps.info/go/

--
Posted by News Bulk Poster
Unregistered version

Jim Thompson · Apr 22, 2005

On Fri, 22 Apr 2005 02:18:09 GMT, "Mike" <no.spam@please.com> wrote:

I'm trying to design a switch mode power supply of about 1200W. And I'd like
to simulate the noise I should expect to get from this circuit. So I want to
use OrCad Probe to plot out the spectrum in dBuV and compare it with the
requirements of FCC.

I know how to do the FFT. But I'm not sure what signal to FFT. Do I need to
simulate a LISN that is done in actual FCC compliance testing? Or do I
simply do an FFT on the line voltage assuming a small resistance in the
line?

Also, I'd like to plot on the same graph the maximum acceptable FCC noise in
dBuV, one for commercial, one for residential, for comparison purposes. How
do I do that on a plot of dBxx verses frequency?

Thanks.

480)460-2350 | |
| E-mail Address at Website Fax

blazeinferno · Apr 22, 2005

Hey Mike,

I'm not an EMI guru but I recently went through a few
EMI tests. The first question I would ask is: How good is your power supply
model? Is it very representative of what you see in practice?
You will probably have to go through conducted common mode, conducted
differential mode tests and radiation. We will neglect the immunity part.

At best your simulation model will give you an idea for differential mode
only (my opinion). For the common mode part, no component model (spice
based) includes the parasitic capacitance between the component and chassis,
transformer windings capacitance etc do you follow? You would probably have
to come up with a common mode simulation model based on approximations.

Although, the best tip I can give you is look for possible EMI sources:

1) Ringing due to reverse recovery of
diodes
2) Ringing due to power switches
(mosfets IGBTs etc)

I know fundamental switching frequency is a source but
what can we do about it?hahahah
Parts you might want to consider:

Add EMI common and
differential mode filters to your input and output usually it's a PI filter.
If you are using RC snubbers,
try using non inductive resistors (regular wirewound resistors usually ring
about 5MHz-10MHz range).
Be sure to be using a good
chasis connection

I hope these tips help you and let me know how your simulation model
goes.....It would be pretty cool if your method works.

Ciaooooooo
Fern

"Mike" <no.spam@please.com> wrote in message
news:B9Z9e.1789$Cz3.243719@monger.newsread.com...

I'm trying to design a switch mode power supply of about 1200W. And I'd
like
to simulate the noise I should expect to get from this circuit. So I want
to
use OrCad Probe to plot out the spectrum in dBuV and compare it with the
requirements of FCC.

I know how to do the FFT. But I'm not sure what signal to FFT. Do I need
to
simulate a LISN that is done in actual FCC compliance testing? Or do I
simply do an FFT on the line voltage assuming a small resistance in the
line?

Also, I'd like to plot on the same graph the maximum acceptable FCC noise
in
dBuV, one for commercial, one for residential, for comparison purposes.
How
do I do that on a plot of dBxx verses frequency?

Thanks.

Simon Peacock · Apr 22, 2005

True.. I often have 4 or 5.. but as you say.. each is documented.

One thing I'd like to see in the schematic ERC is the ability to put a
limited "no-erc" marker.. for example.. "no-erc-if-pin-not-connected" so
that anything other than not connected is an error.. in fact.. the pin
connected is also an error (invert the warning status)

Simon

"Peter Bennett" <peterbb@nowhere.invalid> wrote in message
news:mjvf615jhmmfqefu12vhimlnano6vngs5a@4ax.com...

On Thu, 21 Apr 2005 21:27:46 +1200, "Simon Peacock"
nowhere@to.be.found> wrote:

you will have to look and see if its a problem. Usually they aren't, but
its best to move the split plane boarder by 10 thou to get rid of the
error
so the next guy doesn't get it too.

And you should never disable DRC options.. except for component clearance
and acute angles.

It is sometimes impossible to get rid of all DRC errors. It is OK to
have some on a finished board, as long as you know _why_ they are
there, and are sure the board is the way you want.

Having DRC errors does not prevent you from finishing the design
process and producing Gerber and drill files.

--
Peter Bennett VE7CEI
email: peterbb4 (at) interchange.ubc.ca
GPS and NMEA info and programs:
http://vancouver-webpages.com/peter/index.html
Newsgroup new user info: http://vancouver-webpages.com/nnq

Brad Velander · Apr 22, 2005

Hey Simon, Peter,
Are you forgetting something or has it been corrected in DXP
( and does the user have the DXP SP# that solved the issue). The
connection issues with pads or vias on a split plane boundary? It
either doesn't connect or shorts the two split planes together,
remember? Then considering the split plane has calculated
negative image connections and ties you can't actually get a true
DRC determination on the issue.

The original poster needs to know precisely where that DRC is
originating (or multiple locations) and then either fix it by
moving the split plane boundary or at the very least manually
inspect the Gerbers very closely at those locations to make sure
there isn't an unexpected disconnect or short at those points. I
would go for moving it rather than waiting for Gerbers and then
finding out you had to move it anyway after it means more work to
move it. Or he could test the Gerbers now and pray it didn't
change at all in the final board because of some further
interactions with other file details.

--
Sincerely,
Brad Velander

"Simon Peacock" <nowhere@to.be.found> wrote in message
news:426899eb@news2.actrix.gen.nz...

True.. I often have 4 or 5.. but as you say.. each is
documented.

One thing I'd like to see in the schematic ERC is the ability
to put a
limited "no-erc" marker.. for example..
"no-erc-if-pin-not-connected" so
that anything other than not connected is an error.. in fact..
the pin
connected is also an error (invert the warning status)

Simon

Simon Peacock · Apr 22, 2005

good point.. I've never seen this particular bug as I always make sure
there's no plane connected via thru a split plane boundary. 99SE suffered a
similar fate from memory with direct connected vias.

Simon

"Brad Velander" <SpamThis@nowhere.com> wrote in message
news:WE2ae.1103377$6l.135626@pd7tw2no...

Hey Simon, Peter,
Are you forgetting something or has it been corrected in DXP
( and does the user have the DXP SP# that solved the issue). The
connection issues with pads or vias on a split plane boundary? It
either doesn't connect or shorts the two split planes together,
remember? Then considering the split plane has calculated
negative image connections and ties you can't actually get a true
DRC determination on the issue.

The original poster needs to know precisely where that DRC is
originating (or multiple locations) and then either fix it by
moving the split plane boundary or at the very least manually
inspect the Gerbers very closely at those locations to make sure
there isn't an unexpected disconnect or short at those points. I
would go for moving it rather than waiting for Gerbers and then
finding out you had to move it anyway after it means more work to
move it. Or he could test the Gerbers now and pray it didn't
change at all in the final board because of some further
interactions with other file details.

--
Sincerely,
Brad Velander

"Simon Peacock" <nowhere@to.be.found> wrote in message
news:426899eb@news2.actrix.gen.nz...
True.. I often have 4 or 5.. but as you say.. each is
documented.

One thing I'd like to see in the schematic ERC is the ability
to put a
limited "no-erc" marker.. for example..
"no-erc-if-pin-not-connected" so
that anything other than not connected is an error.. in fact..
the pin
connected is also an error (invert the warning status)

Simon

Jim Thompson · Apr 24, 2005

On 24 Apr 2005 13:36:05 -0700, meldahl@colorado.edu wrote:

get a free ipod!!! just use this link, fill out one silly little offer,
and get your free ipod just like me!!!
http://www.freeiPods.com/?r=16673510

480)460-2350 | |
| E-mail Address at Website Fax

Jim Thompson · Apr 25, 2005

On 25 Apr 2005 05:44:16 -0700, orangeKDS@mail.ru wrote:

I need to find formula for this function:

http://qrange.150m.com/misc/plot.htm

What is good program for nonlinear regression that could help me?

At the moment, I'm using this formula:
Y*X=22,5

or
I*V=22,5 Watt

but its not very precise.

BTW, I'm a total newbie.
It seems that all programs require knowledge of function form and then
they calculate parameters, right? So what form should I use?

480)460-2350 | |
| E-mail Address at Website Fax

Genome · Apr 25, 2005

"Franklin" <reply@newsgroup.plz> wrote in message
news:1pwt0s9wzlgp9$.13fl0fp3kyr3a.dlg@40tude.net...

I'm going to give Protel 99SE SP6 a try. Will be using it for design of
audio pcb's. A couple of years ago I have worked with Eagle which was very
basic and easy to work with.

What should I keep in mind when working with Protel regarding component
placement, inductance, resistance, etc.?

Thanks for any info.

Franklin

Well, assuming I am gay, and au fait with the general things involved in
relationships.

You will receive no advice.

DNA

Franklin · Apr 25, 2005

Op Mon, 25 Apr 2005 14:38:22 +0000, schreef Genome:

"Franklin" <reply@newsgroup.plz> wrote in message
news:1pwt0s9wzlgp9$.13fl0fp3kyr3a.dlg@40tude.net...
I'm going to give Protel 99SE SP6 a try. Will be using it for design of
audio pcb's. A couple of years ago I have worked with Eagle which was very
basic and easy to work with.

What should I keep in mind when working with Protel regarding component
placement, inductance, resistance, etc.?

Thanks for any info.

Franklin

Well, assuming I am gay, and au fait with the general things involved in
relationships.

You will receive no advice.

DNA

or......, you have not understood my question and could have saved the
energy for something worthwhile instead of this nonsense.

Franklin

EAGLE Netlist conversion

Robert Baer

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Leon Heller

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James Morrison

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Brad Velander

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Guy Macon

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Graham Holloway

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Peter Bennett

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Simon Peacock

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Peter Bennett

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Ariane

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Jim Thompson

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blazeinferno

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Simon Peacock

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Brad Velander

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Simon Peacock

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Jim Thompson

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Jim Thompson

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Genome

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Franklin

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