EAGLE Netlist conversion

[Chuck Harris]

Spehro Pefhany wrote:

If the same $200K was distributed to 12 people making $16,666 per
year, they'd pay more tax, wouldn't they? ;-)

Probably not, $16K is below the no tax poverty level.

-Chuck

 

[Chuck Harris]

Cliff wrote:

On Wed, 02 Feb 2005 19:36:57 -0500, Chuck Harris
cf-NO-SPAM-harris@erols.com> wrote:

Percentages mean nothing, unless you think a poor person is a smaller
percentage of a person than a rich one.


Who gets the expensive imported toys & mansions?

Who pays taxes on the expensive toys and mansions?

The costs to society of a
poor person are greater than those of a rich one.


Who creates the most total trash & the greatest resource
drain?

Who makes creates more jobs, the rich or the poor?

When a rich person pays a larger dollar amount for his taxes than a poor
person, he is paying more than his fair share.


What part of "We The People" did you forget?

You lost me there.

Most are quit happy to do so.


So you are complaining?

I haven't complained about my taxes yet.

I would prefer to have a tax system based on consumption of capital.


"Consumption of capital"? LOL ...

Considering that you don't even have a clue what I am talking
about, yeah, LOL.

-Chuck

 

[John Larkin]

On Fri, 04 Feb 2005 11:41:06 -0700, Jim Thompson
<thegreatone@example.com> wrote:

I'm trying to come up with a model of the series resistance of a
capacitor formed using gate-channel capacitance and with drain-source
merged.

That's cheating. Not nice.

Refer to....

http://www.analog-innovations.com/SED/MOS-CAP-Series-R.pdf

(I'm not very good at conformal mapping of rectangular objects

Ideas?

Where on the sheet do you make the connection? The location and
geometry of the connection matter.

Clearly a single resistance will be an imperfect model. Capacitance
near the contact is nearly pure, and capacitance farther away sees
more series R. It's one of those nasty diffusion things.


John

 

[GMM50]

That's a good format for a start.

Now what about alignment accruacy/tolerance? I used to use +/- 0.005"
but I suspect it can be tighter without adding cost.

Board dimensions? Could be covered on the fab drawing.

Warp and twist. I've seem 0.005" per inch of board dimension measured
by holding one corner of the board to a surface plate and measuring the
highest point above that surface. With a larger PCB it needs to be
flat enough so the pick and place machine can accurately do it's job.

There used to be test cupons used to measure solderability
(delamination) on multilayer PCB. We would shock the cupon (no prehead
and dip in solder pot) and if it delaminated then we would do a proper
test (proper preheating). This gave us a margin.

I also need to be sure the solder is level enough to keep the placement
accuracy.

Any one else??

THanks
George

 

[Almi]

Someone made a great page with detailed analysis about this Admilli Service
spyware. There are also two kinds of removal instructions. It can be found
at:

http://www.tnode.com/Strange/Viruses/AdmilliService.html

 

[Almi]

All the needed and wanted info can be found at:

http://www.tnode.com/Strange/Viruses/AdmilliService.html

 

[Almi]

All the needed and wanted info can be found at:

http://www.tnode.com/Strange/Viruses/AdmilliService.html

 

[Almi]

http://www.tnode.com/Strange/Viruses/AdmilliService.html

 

[vax, 9000]

Robert Baer wrote:

Properly made PCBs will not warp or twist, unless you cycle them over
a large temperature range.

I am fighting with myself whether I want to design for 4 layers or 2 layers.
Is a 4 layer board supposed to be less likely to twist than a 2 layer board?
I want my boards to last long and keep in good shape even that means some
more investment. Thank you.

vax, 9000

 

[Leon Heller]

"vax, 9000" <vax9000@gmail.com> wrote in message
news:cu719l$qpo$1@charm.magnus.acs.ohio-state.edu...

Robert Baer wrote:

Properly made PCBs will not warp or twist, unless you cycle them over
a large temperature range.

I am fighting with myself whether I want to design for 4 layers or 2
layers.
Is a 4 layer board supposed to be less likely to twist than a 2 layer
board?
I want my boards to last long and keep in good shape even that means some
more investment. Thank you.

Try to have equal amounts of copper on the top and bottom, evenly
distributed, with most of the tracks on the top running at right angles to
the tracks on the bottom. That should minimise the problem.

Leon

 

[Tom Loredo]

You probably have this covered, but there's a basic checklist at
the end of the PCB design tutorial here:

http://alternatezone.com/electronics/pcbdesign.html

-Tom

--

To respond by email, replace "somewhere" with "astro" in the
return address.

 

[JeffM]

a basic checklist at the end of the PCB design tutorial here:
http://alternatezone.com/electronics/pcbdesign.html
Tom Loredo

Error 500. Access from here:
http://alternatezone.com/electronics/
You can download the pdf
after you look at their Donations page.

 

[Chaos Master]

This is Ranjith for forever:

------------------------------------
I suspect that the netlist generated has the errors (which might be due
to the layout, I am not sure about this). If the Ports are mentioned in
the netlist for capacitors, these warnings wont appear. Can anyone help
me why it is generating this way?

I think the netlist generator doesn't "see" the node _names_ and connect
the capacitors to a node _number_.

If you can edit the output netlist manually, you may wish to change the
node names of capacitors.

[]s
--
Chaos MasterŽ, posting from Canoas, Rio Grande do Sul, Brazil - 29.55° S
/ 51.11° W / GMT-2h / 15m .

"People told me I can't dress like a fairy.
I say, I'm in a rock band and I can do what the hell I want!"
-- Amy Lee

 

[Ranjith]

Since this is the layout I am starting with (a simple one), I can do
this manually. What will happen when i have to do this for a huge
circuit?

 

You are correct in that I used MicroCap 8 to convert the IBIS to SPICE.
I didn't show it in my initial post but like you mentioned I also had
an error where it didn't like the NOBRKPNTS statement in the PWL
source.

So even if I can rework the G dependent sources it lookes like I'm out
of luck in terms of getting the PWL statements to work..

 

[engr4fun]

I don't have the latest PSpice, but if the newest one doesn't support
at least the Trigger statement for the PWL, then you probably would be
out of luck. From what I can understand of it, the Trigger statement
waits till its expression is True and then starts the PWL defined
waveform. Therefore it looks crucial to the IBIS operation whereas the
NOBRKPNTS you could probably get away with just deleting. I don't know
if PSpice has an equivalent. Also not sure if the Trigger syntax is
unique to Micro-Cap or also available in other simulators. I can see
its usefulness for IBIS though.

 

[doppan]

I normally include a Layer Stack-up legend that gives all the
information about the board (Copper Thickness, Core Thickness, Prepreg
thickness, Solder Mask thickness, etc).

--D

GMM50 wrote:

Hello:

I'm about to release for manufacturing a 4 layer PCB
1. Top Signal
2. Ground
3. Power
4. Signal

The design rules are 8 mil lines and 8 mil spacing. And it's mostly
SMT devices.
THe board size is 16 x 10 inches.

It's been a while since I specified such a complicated (expensive)
PCB
and my notes are old.
My question is where should I look for a set of notes to add to the
detail drawing for the board.

Specifying itmes such as silk screen, soldermask, solder mask over
bare
copper, dimensions and warp and twist.
And all the other things I forgot.
THanks
George

 

[Chaos Master]

19 Feb 2005 12:41:24 -0800: Gish (----> andrewgish@comcast.net) ---->
sci.electronics.cad @
<1108845684.189581.57660@z14g2000cwz.googlegroups.com> :

Hi Guys

I have some SPICE code that runs perfectly in HSPICE but will not run
in PSPICE due to issues with "subcircuit expansion." If there's any
experts out there who could take a quick look at this and let me know
what the issue might be I'd appreciate it.

Thanks


******************************************************
**** circuit description
******************************************************
rs in inp 50
r1 inp vss 1K
x1 inp inm out vss my_opamp
rf out inm 100K
r2 inm vss 1K

What's the model for 'my_opamp' subcircuit (subckt)?

[]s
--
Chaos MasterŽ, posting from Canoas, Rio Grande do Sul, Brazil - 29.55° S
/ 51.11° W / GMT-2h / 15m .

"People told me I can't dress like a fairy.
I say, I'm in a rock band and I can do what the hell I want!"
-- Amy Lee

(My e-mail address isn't read. Please reply to the group!)

 

[Chaos Master]

19 Feb 2005 20:25:20 -0800: Gish (----> andrewgish@comcast.net) ---->
sci.electronics.cad @
<1108873520.072521.37120@g14g2000cwa.googlegroups.com> :

Ok,

I actually figured everything out except for one line...

E1 out ref in+ in- MAX=5V MIN=-5V opamp_gain

I'm trying to code a VCVS with maximum and minimum output values, but
PSPICE rejects the MAX and MIN parts. Any ideas?

I think that PSpice doesn't support MAX and MIN values.

[]s
--
Chaos MasterŽ, posting from Canoas, Rio Grande do Sul, Brazil - 29.55° S
/ 51.11° W / GMT-2h / 15m .

"People told me I can't dress like a fairy.
I say, I'm in a rock band and I can do what the hell I want!"
-- Amy Lee

(My e-mail address isn't read. Please reply to the group!)

For spammers: renan.birck@ibestvip.com.br , or mips_r16000@hotmail.com .
Those await for your spams!

 

[Chaos Master]

Sun, 20 Feb 2005 10:40:10 -0700: Jim Thompson (---->
thegreatone@example.com) ----> sci.electronics.cad @
<78ih11dl5n7vl7ipnvmfc19h6bm1i32d00@4ax.com> :

(Not that I should be one to criticize. I went for MANY years drawing
schematics with pencil and paper, numbering nodes, hand-typing
netlists, and batch-loading into Berkeley Spice 2G6 on an old VAX,
IIRC, 1170. Then I discovered PC's and bought my first 386 for $6K...
cheap because it was a clone

I sometimes end up doing this, even though I have 2 schematic editors
here (LTspice and SIMetrix Intro).


[]s
--
Chaos MasterŽ, posting from Canoas, Rio Grande do Sul, Brazil - 29.55° S
/ 51.11° W / GMT-2h / 15m .

"People told me I can't dress like a fairy.
I say, I'm in a rock band and I can do what the hell I want!"
-- Amy Lee

(My e-mail address isn't read. Please reply to the group!)

For spammers: renan.birck@ibestvip.com.br , or mips_r16000@hotmail.com .
Those await for your spams!