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chrisv <chrisv@nospam.invalid> says...
tholen@antispam.ham wrote:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.
Click to expand...
Baby Ducks! Plasma! Affection!!!
 
chrisv writes:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.
Click to expand...
What is allegedly so amazing about Brown's non sequitur, chrisv?
 
In <10f8hq3n5hasmc7@corp.supernews.com>, <@.> writes:

chrisv <chrisv@nospam.invalid> says...

I wrote:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.

Baby Ducks! Plasma! Affection!!!
Click to expand...
What does that have to do with OS/2, @.?
 
tholen@antispam.ham wrote:

What is allegedly so amazing about Brown's non sequitur, chrisv?
Click to expand...
Brown doesn't have non sequiturs. He has cows.
 
In <rLabYx1iiM0c675AB94C8WqChOJacqZs@alt.binaries.nude.celebrities.female>, "tholen@antispam.ham, the shit-stained, hurling penile wart" <Tt5H7OXi68BA@alt.binaries.nude.celebrities.female> writes:

What is allegedly so amazing about Brown's non sequitur, chrisv?

Brown doesn't have non sequiturs. He has cows.
Click to expand...
Non sequitur. Still faking someone else's identity, eh?
 
"learner" <sonalsingh28@yahoo.com> wrote in message
news:40cfbbf5.0407140048.474e9ed4@posting.google.com...
: Hi,
: I auto routed my design and when I do a DRC, it say
: Processing Rule : Clearance Constraint (Gap=8mil) (On the
board ),(On
: the board )
: Violation between Pad 386EXTC-130(4878.303mil,9968.678mil)
TopLayer
: and
: Pad 386EXTC-129(4897.988mil,9968.678mil)
: TopLayer
:
: How can I remove this error? It shows the same error for all the
pads
: of my processor. I made the footprint according to the package
info.
: Is it due to auto routing?
: Any help is appreciated.
: Thanks
: Learner

Measure the Foot print! If the space between the pads is less
than the "Clearance Constraint" the error is valid, which means
you need to:

1: redraw the foot print with wider spaces (not very practical)

2: Set the clearance constraint to slightly less than the
separation between the pads. For example IF the space between the
pads is 5 mil, set Clearance Constraint to 4.8 mil so the board
will give a clean DRC.

You may change the Constraint as a last test, leave it the at 8
mil for routing.
 
tholen@antispam.ham wrote:

chrisv writes:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.

What is allegedly so amazing about Brown's non sequitur, chrisv?
Click to expand...
You are erroneously presupposing that my "amazing" referred to Brown's
non sequitur, Tholen.
 
chrisv writes:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.

What is allegedly so amazing about Brown's non sequitur, chrisv?

You are erroneously presupposing that my "amazing" referred to Brown's
non sequitur, Tholen.
Click to expand...
Illogical, chrisv; what else could it be?
 
Learner,
Alternatively you can devise a special rule to handle this
instance.

It is not uncommon for some SMT fine pitch parts today to
violate 8 mil DRC spacing. I have several times had to use 7.X
mil spacing on particular part's pads.

I note that there is slightly less than 20mils (19.685mils)
spacing between your pads. Subtract one pad width from that
figure and you will have the minimum spacing between pads.
(Assuming the two pads are equal sizes.)

Here is how I would do it.

A) Set up a Pad Class for your U??? Components pads, include all
of it's pads.
B) In DRC set a new rule using for Scope A the Pad Class that you
just created.
C) For scope B, set the same pad Class.
D) For your minimum clearance set a suitable spacing.
E) Make sure that it is set for "Different Nets Only".
F) Give your new Rule a name, Click OKAY.

--
Sincerely,
Brad Velander

"Roger Gt" <not@here.net> wrote in message
news:AndJc.20290$8m7.4190@newssvr27.news.prodigy.com...
"learner" <sonalsingh28@yahoo.com> wrote in message
news:40cfbbf5.0407140048.474e9ed4@posting.google.com...
: Hi,
: I auto routed my design and when I do a DRC, it say
: Processing Rule : Clearance Constraint (Gap=8mil) (On the
board ),(On
: the board )
: Violation between Pad 386EXTC-130(4878.303mil,9968.678mil)
TopLayer
: and
: Pad 386EXTC-129(4897.988mil,9968.678mil)
: TopLayer
:
: How can I remove this error? It shows the same error for all
the
pads
: of my processor. I made the footprint according to the
package
info.
: Is it due to auto routing?
: Any help is appreciated.
: Thanks
: Learner

Measure the Foot print! If the space between the pads is less
than the "Clearance Constraint" the error is valid, which means
you need to:

1: redraw the foot print with wider spaces (not very practical)

2: Set the clearance constraint to slightly less than the
separation between the pads. For example IF the space between
the
pads is 5 mil, set Clearance Constraint to 4.8 mil so the
board
will give a clean DRC.

You may change the Constraint as a last test, leave it the at 8
mil for routing.
Click to expand...
 
tholen@antispam.ham wrote:
chrisv writes:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.

What is allegedly so amazing about Brown's non sequitur, chrisv?

You are erroneously presupposing that my "amazing" referred to
Brown's non sequitur, Tholen.

Illogical
Click to expand...
Frogery.
 
Hello,

You can try SILKedit software. This PowerPCB utility program copy
silkscreen layer into a 2D layer. When you copy paste a job, PowerPCB copy
all items but 2d line ref-des are copied like free texts.
 
Hi,

You can try BMPinPCB program. This tools converts a bitmap logo into
gerber. I know that it works with PADS-PowerPCB maybe it works with
another EDA software.
 
Hi,

You can try BMPinPCB program. This tools converts a bitmap logo into
gerber. I know that it works with PADS-PowerPCB maybe it works with
another EDA software.

Jean
 
In <az8tA46bjEN0ACABF0D7wicuoStr3DYp@alt.binaries.nospam.denim.shorts>, "tholen@antispam.ham, the pig drover" <bD3tH0fGdnhs@alt.binaries.nospam.denim.shorts> writes:

chrisv writes:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.

What is allegedly so amazing about Brown's non sequitur, chrisv?

You are erroneously presupposing that my "amazing" referred to
Brown's non sequitur, Tholen.

Illogical

Frogery.
Click to expand...
Non sequitur. Still faking your identity, eh?
 
"j_boin" <jean_boin@hotmail.com> wrote in message
news:fcc80e2aec1c595450ea70cb2137fd99@localhost.talkaboutelectronicequipment
..com...
Hi,

You can try BMPinPCB program. This tools converts a bitmap logo into
gerber. I know that it works with PADS-PowerPCB maybe it works with
another EDA software.

Jean
Click to expand...
From where do you get this BMPinPCB programme ? - I cannot seem to find it.
 
chrisv writes:

James Brown <Godfather@Of.Soul> writes:

Non sequitur.

PAPA'S GOT A BRAND NEW BAG !

Also non sequitur.

Amazing.

What is allegedly so amazing about Brown's non sequitur, chrisv?

You are erroneously presupposing that my "amazing" referred to Brown's
non sequitur, Tholen.

Illogical, chrisv;

Classic unsubstantiated and erroneous claim.
Click to expand...
On your part, chrisv.

what else could it be?

It could be that I think that you are amazing, Tholen.
Click to expand...
Illogical, given that that would be non sequitur, chrisv.
 
In <H9GISGAb45VL1F9F1A8Ac0nWuKXwlbOU@alt.binaries.pictures.alley-baggett>, "tholen@antispam.ham, the sneaking, improving airhead" <QR2v2h8m0UK8@alt.binaries.pictures.alley-baggett> writes:

chrisv writes:

It could be that I think that you are

Illogical

Snipped for accuracy.
Click to expand...
Still faking someone else's identity for deceit.
 
John Larkin wrote:
Hey, Here's my latest gadget:

http://www.highlandtechnology.com/DSS/P400DS.html

Actually, three of us here worked on this for about three years as
sort of a background project, when we didn't have a paying customer
screaming for delivery on something. I never appreciated how much
hassle a benchtop instrument would really be until this got serious. A
VME or PCI board is blindingly simple compared to all the stuff you
have to put into a box like this. And by the time you finish it,
things have changed so much you're dying to redesign it again from
scratch. m.u.s.t..r.e.s.i.s.t..t.e.m.p.t.a.t.i.o.n.

John
Click to expand...

I like that more than the air freshener, I'm afraid.



--
_____________________
Christopher R. Carlen
crobc@earthlink.net
Suse 8.1 Linux 2.4.19
 
John Larkin wrote:
Hey, Here's my latest gadget:

http://www.highlandtechnology.com/DSS/P400DS.html

Actually, three of us here worked on this for about three years as
sort of a background project, when we didn't have a paying customer
screaming for delivery on something. I never appreciated how much
hassle a benchtop instrument would really be until this got serious. A
VME or PCI board is blindingly simple compared to all the stuff you
have to put into a box like this. And by the time you finish it,
things have changed so much you're dying to redesign it again from
scratch. m.u.s.t..r.e.s.i.s.t..t.e.m.p.t.a.t.i.o.n.
Click to expand...
I'm impressed. OK, how much does it cost? I'd like to see a
scaled-back version, with 0.1ns resolution, and 8 channels, etc.
Smaller perhaps and cheaper. Scalable to 16, 24, 32 channels.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)
 
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