cell libraries and place and route

[DReynolds]

Kev,
to avoid this problem, I keep two copies of the cells, one with globals
and one with the power and ground pins added to them. I let the digital
tools use the ones with globals (because that is what they expect) and
I substitute in the ones with power pins when it comes back to me. It
is a bit of a hassle, but I find it works out well because I can always
tell where my cells are connected.

Yes, I have had issues in the past with globals and LVS....


David

kev wrote:

I got a bit sidetracked here with cdlin - when in fact I am more
concerned on how to simulate a standard cell lib.

I can simualte if I convert the nodes VSS and VDD to VSS! and VDD! in
the netlist. but then that means that I ahev 2 global nodes i.e.e all
my stanard cell instances will be shorted through these nodes. Now I
want to be able to replace these nodes by inherited connections but I
can seem to get the cdf paramters correct for netlisting....

Kevin


DReynolds wrote:

Kev, it sounds like you are not getting the correct primitives, which
usually means you are not telling cdlin where your PDK devides are when
you run cdlin.

David
kev wrote:
Hi

I now final have a proper cdl netlist. However, when I try to cdlin
the netlsit all i get is a "mos" cell created.

I ahve also converted the netlist to spectre and am having problems
as I want to add inherited supplies to the stanard cell lib rather that
have
global VDD and VSS. I get it to netlist but it doen't work. [simple
inverter]

I changed to standard cell description fo an inverter from/to the
follwoing:

.subckt INVX1 Y A
M0 Y A VSS VSS NCH l=0.18u w=0.6u
M1 VDD A Y VDD PCH l=0.18u w=0.9u
.ends INVX1

to

simulator lang=spectre

subckt INVX1 Y A inh_vdd inh_vss
M0 ( Y A inh_vss inh_vss ) nch l=0.18u w=0.6u
M1 ( inh_vdd A Y inh_vdd ) pch l=0.18u w=0.9u
ends INVX1

However, it doesn't work so it seems that the inherited suppiles are
not being passed properly by the cdf. [componentName = INVX1 termOrder
"Y" "A" are the only 2 cdf params I set].

However if one draws a schmatci of such and inverter with inherited
supplies the componentName = subcircuit and not INVX1.

Any ideas?

Kevin


DReynolds wrote:

Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David


kev wrote:
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd

 

[Andrew Beckett]

On 16 Jan 2007 12:35:47 -0800, "DReynolds" <spurwinktech@gmail.com> wrote:

Kev,
to avoid this problem, I keep two copies of the cells, one with globals
and one with the power and ground pins added to them. I let the digital
tools use the ones with globals (because that is what they expect) and
I substitute in the ones with power pins when it comes back to me. It
is a bit of a hassle, but I find it works out well because I can always
tell where my cells are connected.

Yes, I have had issues in the past with globals and LVS....


David

That's exactly the problem that Inherited connections are intended to solve. By
using inherited connections, you can have pins or nets in your low level digital
standard cells which don't appear on the symbols - they default to global nets,
but can be overridden at some higher level in the hierarchy using netSet
properties.

In the resulting transistor level netlists, extra pins will be added to
subcircuits to pass the power supplies. Verilog netlists however would not go
down as far as the transistor level circuits, and so would not see the net
expressions, and consequently not need to add the additional power pins - which
would line up with usual digital usage of not having to connect up power
supplies.

There's a good inherited connections tutorial on sourcelink (see previous
postings from my esteemed colleague John Gianni on this), so I suggest taking a
look at that.

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.

 

[Svenn Are Bjerkem]

On Jan 18, 6:51 am, Andrew Beckett <andr...@DcEaLdEeTnEcTe.HcIoSm>
wrote:

On 16 Jan 2007 12:35:47 -0800, "DReynolds" <spurwinkt...@gmail.com> wrote:

Kev,
to avoid this problem, I keep two copies of the cells, one with globals
and one with the power and ground pins added to them. I let the digital
tools use the ones with globals (because that is what they expect) and
I substitute in the ones with power pins when it comes back to me. It
is a bit of a hassle, but I find it works out well because I can always
tell where my cells are connected.

Yes, I have had issues in the past with globals and LVS....

DavidThat's exactly the problem that Inherited connections are intended to solve. By
using inherited connections, you can have pins or nets in your low level digital
standard cells which don't appear on the symbols - they default to global nets,
but can be overridden at some higher level in the hierarchy using netSet
properties.

What (built-in) tools would you recomend when rearranging the inherited
nets when, let's say, power pins are added or removed? Is there a way
to create a tree-view of how cells are attached to the various
inherited nets? Currently interesting is IC5.1 but sooner or later
everybody run >IC6.*

We use inherited nets a lot and I think the concept is working good. I
find that there is a huge lack in supporting tools for rearranging.

--
Svenn

 

[Svenn Are Bjerkem]

On Mar 6, 9:31 am, "art.chipdes...@gmail.com"
<art.chipdes...@gmail.com> wrote:

Hi Designers,

Felt a bit intimidated by the wording of the posting. Looked very much
like that of most emails that go unread into my spam mailbox. I
decided to give it a decent chance and went over to see what the page
has to offer.

I would classify it as the possible beginning of something that could
be interesting if more flesh is added to the bone. It doesn't hurt to
go there and see for yourselves, but don't expect to find exhausting
answers to any problem. All suggestions have to go via email so unless
the initiator drives this himself, I find it hard to offer supportive
feedback from the users.

Don't get me wrong, I do support open information sources like this.
All too often I hit these pay-per-article and paper publication sites
when I search for answers to fundamental things in design. Looks like
IEEE have google index all the papers just to bring everybody
searching to the ieeeexplore site. Other academic organizations have
followed, and I suspect that in the end no publications will be
available freely on the net.

First impression (posting here) was not so good, second one was better
and I hope third impression will improve even more.
--
Svenn

 

[lorak88ATgmail.com]

hi,

is it possible to use envSetVal to set the values for numberNotation
and precision? If yes, how? thanks!


S. L.

 

[Andrew Beckett]

On 6 Apr 2007 08:43:37 -0700, "lorak88ATgmail.com" <lorak88@gmail.com> wrote:

hi,

is it possible to use envSetVal to set the values for numberNotation
and precision? If yes, how? thanks!


S. L.

What values for numberNotation and precision? I don't understand what you're
trying to set.

Is this for a particular simulation?

Ask a precise answer and you're much more likely to get a precise answer.

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.

 

Okay - I have found ways of determining the current state and its
location by overloading the sevLoadState and related functions thanks
to this post:

http://groups.google.com/group/comp.cad.cadence/browse_thread/thread/ded86660b249341d/c6ddc40d685bed1d?lnk=gst&q=state&rnum=4#c6ddc40d685bed1d

Are functions such as aaAddEventCB and sevLoadStateFromForm documented
anywhere?

Also, it seems that the entire contents of the state directory are
obliterated when a state is re-saved (making it difficult to stash
additional data here). Is this correct?

Thanks,

Phil.

 

[Svenn Are Bjerkem]

Would be nice if that scrambler could take existing verilog code and
create new, working hardware. You just didn"t know really how it
worked. But, hey, use the source, Luke.
--
Svenn

 

[John Gianni]

On May 3, 2:00 am, phil.jones2...@googlemail.com wrote:

Are functions such as aaAddEventCB and sevLoadStateFromForm documented
anywhere?

Sorry I haven't perused comp.cad.cadence in a long while ... but I
happened to notice this user request from earlier this month regarding
the documentation & support status of aaAddEventCB() and
sevLoadStateFromForm() SKILL functions.

The best answer is to let you know that you can easily determine the
support status of any SKILL function merely by putting that function
into a properly formatted file and mailing that file to a certain
email address at Cadence.

The automated result, generally by return mail, will provide not only
the status of the functions, but also a plethora of useful information
about the functions, specifically whether any have been deleted or
changed (with argument pre and post differences) between releases, and
in what releases, replacement equivalents, helpful advice, etc.

The simplest way to create that properly formatted file is to press
the Virtuoso CIW: Tools -> SKILL -> Survey button; and then, when the
resultant three files are generated (named skillTab.defn,
skillTab.info, & skillTab.out), to click on the button to email the
summary file (i.e., skillTab.out) to Cadence for automated analysis by
return email.

Notice it takes only two mouse clicks, plus filling in two simple
forms, to complete both operations. This will result in you knowing
EVERY function you've called, every function you've defined, where you
called them, where you defined them, and the status of every one of
those functions, in every Virtuoso release from IC440 onward including
the latest Virtuoso IC61 releases. That's less effort (IMHO) than it
takes to type this response.

In addition, you can run the SKILL Finder to locate the short-form
documentation on any function (in addition to a search in the full
Cadence documentation system). The SKILL Finder is located at CIW:
Tools -> SKILL -> Finder

Having said that, specifically the two functions you noted above are
listed as private. Private functions are undocumented & unsupported
SKILL functions generally not intended for use by Customers. There is
a private-function-resolution process which Cadence Customer Support
can kick into gear for you which will work with you to provide a
solution to your needs which uses fully documented & supported SKILL
functions.

As always, I hope this response helps many others, in addition to the
requester,
John Gianni
--
Nothing I state here is prior sanctioned nor reviewed by my employer.

 

[lorak88ATgmail.com]

Hi,

Could someone know why cadence's spectre transient simulation does
not like what I did to the multitone verilog-a code generated by the
ModelWriter.

I modified the voltage summation to something like this:
----------------------------------------------------
Vout_internal = 0
for (i_index==0; i_index < 4; i_index = i_index+1) begin
Vout_internal = Vout_internal +
amp[i_index+1] * sin(2*`M_PI *freq[i_index+1] *
$abstime )
end
V(vout) <+ Vout_internal
----------------------------------------------------
but all i got from a transient simulation was zero for all time
value.

Thanks for any help/advise.

 

[oliver]

I think you should have "i_index=0" and not "i_index==0" in the for
loop:

for (i_index=0; i_index < 4; i_index++) ...

 

[nganguyen]

Hi, I also experienced with this warning message. I saw the time you posted
was so long ago anyway I still need your help.
Can you please explain more detail about the warning? How can I eliminate
this warning? This warning is serious to the circuit?

--
Message posted using http://www.talkaboutcad.com/group/comp.cad.cadence/
More information at http://www.talkaboutcad.com/faq.html

 

[sbrickles]

This problem is still manifesting itself in the latest version of Cadence
(5.1.41 USR 5). Did you ever find out what was causing this ? I tried to
file a Cadence Support request for this and they were unable to recreate
it. Unfortunately the problem is not reproducible in a standalone test
case - it seems to have something to do with network files. Interested to
hear what others have to say on this.

Stephen

--
Message posted using http://www.talkaboutcad.com/group/comp.cad.cadence/
More information at http://www.talkaboutcad.com/faq.html

 

[Brad Barnett]

Andrew,

Any luck with saving Parametric setup as part of a saved state? We'd
really find this handy!

by Andrew Beckett <andrewb@[EMAIL PROTECTED] > Jun 3, 2004 at 12:34 PM

I don't think there's any public way of doing this - sorry!

There are some PCRs to unify the things that aren't part of the main
states (like Monte Carlo and Parametric analysis) - but it's not been
done yet. Perhaps when that happens an API might be added? (wild
speculation on my part - don't take that as fact)

Andrew.

On Thu, 3 Jun 2004 10:15:37 +0200, "S. Badel" <stephane.badel@[EMAIL
PROTECTED] wrote:

Is there a way i can save additional data in an artist state, I mean a
clean way without hacking anything ?

I'd like to implement an extension to artist and would like the data to
be saved when one uses 'save state', and retrieved when 'load state'.

I noticed tools like parametric analysis or monte-carlo do have their
own saving mechanism (not practical), moreover i couldn't find anything
in the documentation. The only way I'm thinking of is to Hack the
sevSaveState() procedure, or the Save State menu item.

Thanks,

Stéphane


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

Brad,

Parametric analysis setup is not part of the ADE state still.

However, in IC61, you have ADE-XL, and if you define your sweeps in ADE-XL, then
they become part of the adexl view you create. Similarly with monte-carlo setup.
So effectively it's done in ADE-XL.

Regards,

Andrew.

Brad Barnett wrote, on 02/27/08 12:05:

Andrew,

Any luck with saving Parametric setup as part of a saved state? We'd
really find this handy!

by Andrew Beckett <andrewb@[EMAIL PROTECTED] > Jun 3, 2004 at 12:34 PM
I don't think there's any public way of doing this - sorry!

There are some PCRs to unify the things that aren't part of the main
states (like Monte Carlo and Parametric analysis) - but it's not been
done yet. Perhaps when that happens an API might be added? (wild
speculation on my part - don't take that as fact)

Andrew.

On Thu, 3 Jun 2004 10:15:37 +0200, "S. Badel" <stephane.badel@[EMAIL
PROTECTED] wrote:

Is there a way i can save additional data in an artist state, I mean a
clean way without hacking anything ?

I'd like to implement an extension to artist and would like the data to
be saved when one uses 'save state', and retrieved when 'load state'.

I noticed tools like parametric analysis or monte-carlo do have their
own saving mechanism (not practical), moreover i couldn't find anything
in the documentation. The only way I'm thinking of is to Hack the
sevSaveState() procedure, or the Save State menu item.

Thanks,

Stéphane


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Pete nospam Zakel]

In article <da7b4961-fb5d-4466-a226-592ce76a6203@e39g2000hsf.googlegroups.com> Reotaro Hashemoto <ahmad.abdulghany@gmail.com> writes:

Hi all,

I have a list of basic SKILL question, i hope that you can put some
answers to them.

Q1. I don't have Netscape, but only firefox, is it possible to display
cdsdocs contents in firefox? How can i do it?

Try setting the environment variable CDS_DEFAULT_BROWSER to firefox. I
think cdsdoc pays attention to that

Q2. When I type "openbook" anything in terminal, it gives me "command
not found", what should i do to see it?

Try cdsdoc instead of openbook.

Q3. Where to read about bindkeys setting, modification and
particularly bindkeys "events"?

Sample bindkeys files are in <CDShier>/tools/dfII/samples/local.
Also, cdsdoc has a lot of stuff on that. And the documentation is also
available through sourcelink, as far as I know.

Q4. Is there a meaning for every built-in Skill functions suffixes?
Like hi..., ge... dmb... and so on?? Where can i find explanation or
comments about them?

Yes. hi == Human Interface. ge == Graphics Editor. I forget what dmb is.
le == Layout Editor. etc.

Q5. I want to pass certain string to a function like hiSetWindowName,
and that string needs to have a variable value to be substituted when
calling the function, in Tcl we can put the string between double-
quotation pairs and put the variable as $var, is there a way to do
similar thing in Skill??

Lets says the variable name is StringVar. You can do:

MyWindowName = strcat( "prefix " StringVar " postfix" )

or

MyWindowName = sprintf( nil "prefix %s postfix" StringVar )

for example.

Q6. I need to read dedicated example(s) about circuit building
(instance placing, wiring the circuit, and biasing it) in Skill, this
is dedicated to create an automated flow for some devices test. Where
to find that?

That I don't know (I'm a GUI person).

Q7. Why don't i see the menu when creating it using hiCreateSimpleMenu
in the CIW? Should i use also any function to initialize CIW menus?

CIW menus should be initialized with the ciw.menus file. hiCreateSimpleMenu()
just creates the menu, you have to use hiAddBannerMenu() to add it to a
window, but you really want to set up the ciw.menus files, since that tends
to override what's place programmatically. The menus files are all in
<CDShier>/tools/dfII/etc/tools/menus.

Q8. When I create a menu in certain window banner, is there a way to
place the menu to right of the window (like the help menu)?

No.

Q9. Finally,How to know information about cadence stuff like menu
names (e.g. file, edit, ...) , window names, and so on?

Partly experience, partly documentation, partly looking at the log file...

-Pete Zakel
(phz@seeheader.nospam)

"we will invent new lullabies, new songs, new acts of love,
we will cry over things we used to laugh &
our new wisdom will bring tears to eyes of gentile
creatures from other planets who were afraid of us till then &
in the end a summer with wild winds &
new friends will be."

 

[Pete nospam Zakel]

In article <a31162a4-bde0-4a97-8193-39c81857b07f@26g2000hsk.googlegroups.com> nour <nour.laouini@gmail.com> writes:

hello,

I have a problem:

I want to update the last element in a skill list by incrementing it ,
for example I have the following list: list='(4 6) and I want to
transform it to this one list='(4 7).

There is a skill fonction which can do it: rplacd(name_liste
new_value) but it works only when I give the exact new_value, for
example i must tape
rplacd( list '(7))

Please help me because i must use it in a "for" fonction so the
incrementation must happen automatically ....

I've tried this but it didn't work:

y=nth( 1 list)+1
rplacd( list ')

it generate the following list: (4 y)

thanks a lot for the one who will help me

It's replacing the last element with the symbol y because that's what you
are telling it to do. The single quote in front of the open paren says
"don't evaluate symbols, pass them as is".

if you do:

y = nth( 1 list )+1
rplacd( list list )

it will do what you are asking for, since the list function evaluates its
arguments.

The following will also work:

y = list( nth( 1 list )+1 )
rplacd( list y )

Your statement:

rplacd( list ' )

is equivalent to:

rplacd( list list( 'y ) )

-Pete Zakel
(phz@seeheader.nospam)

Felson's Law:
To steal ideas from one person is plagiarism; to steal from
many is research.

 

[Pete nospam Zakel]

In article <48124c55$1@news.cadence.com> pxhxz@cadence.com (Pete nospam Zakel) writes:

Your statement:

rplacd( list ' )

is equivalent to:

rplacd( list list( 'y ) )

P.S. rplacd doesn't replace the last item, it replaces the cdr (all the list
items following the first element, a/k/a the car).

For example:

y = list( 1 5 6 7 8 9 )
(1 5 6 7 8

9
)

rplacd( y list( 2 3 4 ) )
(1 2 3 4)

-Pete Zakel
(phz@seeheader.nospam)

"Enzymes are things invented by biologists that explain things which
otherwise require harder thinking."
-Jerome Lettvin

 

[Pete nospam Zakel]

In article <217a2667-da6b-45a6-a392-87534b49afa0@a1g2000hsb.googlegroups.com> Reotaro Hashemoto <ahmad.abdulghany@gmail.com> writes:

I have tried hiGetWindowMenu(window(1)) for example, and it always
returns nil, did i make a mistake?

"Window Menu" is the RMB popup (or MMB on older releases) on a graphics
window (and some other windows), and the CIW doesn't have one of those.
The banner menus are gotten with hiGetBannerMenus().

-Pete Zakel
(phz@seeheader.nospam)

"Probably the best operating system in the world is the [operating system]
made for the PDP-11 by Bell Laboratories." - Ted Nelson, October 1977

 

[Pete nospam Zakel]

In article <1209371450_3825@sicinfo3.epfl.ch> stephane.badel@REMOVETHISepfl.ch writes:

Q1. When I define two procedures as following: procedure( proc1()
x=10) and the other is: procedure(proc2() x); if i called the first
one (i.e. proc1) it will return the value of the variable x defined
there, why when i call proc2 it gives me error that variable x is
undefined? Although i am not using either prog or let for making it
local? I think i misunderstand the concept! How to let a variable
global?

No... it should really work...

x won't be defined until after you invoke proc1(). Just declaring x within
a statement in proc1() doesn't define it:

# skill

procedure( proc1() x=10)
proc1
procedure(proc2() x)
proc2
x
*Error* toplevel: undefined variable - x
proc2()
*Error* eval: unbound variable - x
proc1()
10
x
10
proc2()
10

However, I wouldn't use "x" as a global since it's likely to be clobbered
by other routines. And you shouldn't begin any globals you create with a
lowercase letter.

-Pete Zakel
(phz@seeheader.nospam)

"Walking on water and developing software from a specification are easy
if both are frozen."
-Edward V. Berard