cell libraries and place and route

Does your input voltage source have some source resistance?


bhargavalluri@gmail.com wrote:
Let me explain the situation better, I have two diodes as you said, a
diode from vdd to input and another from input to gnd. my vdd is 1.8 v
, and my input voltage swings from 0v to 5v. When my input is at 5v the
diode which is connected to vdd should turn ON and my output should be
1.8 v,but i am getting same 5v at output. I have tried many things like
connecting a resistor at the output and taking output from that
resistor, but nothing seems to work.


linkin wrote:
Exactly what kind of ESD functionality do you want?

For example, an analog ESD circuit might have a diode from VDD to the
input, and another diode from the input to GND. Both diodes nominally
will be reverse-biased, and it is actually desirable that your output
voltage is equal to the input voltage (they are actually the same node
in this case). Ideally you don't want the presence of ESD diodes to
impact the performance of the signal during normal operation.



bhargavalluri@gmail.com wrote:
Hi,

I am trying to simulate a simple ESD ciruit( containing 2 diodes) using
cadence spectre, but my circuit is not functioning as expected.
Whatever voltage i give at the input is coming out to the output. Can
anyone tell me what can be the reason for this behavior and how i can
overcome it.

Thanks,
Alluri.
Click to expand...
 
NO,my input voltage source doesnt have any resistance and i also have a
resister at the output to compensate for any forward resistance the
diode might have.
linkin wrote:
Does your input voltage source have some source resistance?


bhargavalluri@gmail.com wrote:
Let me explain the situation better, I have two diodes as you said, a
diode from vdd to input and another from input to gnd. my vdd is 1.8 v
, and my input voltage swings from 0v to 5v. When my input is at 5v the
diode which is connected to vdd should turn ON and my output should be
1.8 v,but i am getting same 5v at output. I have tried many things like
connecting a resistor at the output and taking output from that
resistor, but nothing seems to work.


linkin wrote:
Exactly what kind of ESD functionality do you want?

For example, an analog ESD circuit might have a diode from VDD to the
input, and another diode from the input to GND. Both diodes nominally
will be reverse-biased, and it is actually desirable that your output
voltage is equal to the input voltage (they are actually the same node
in this case). Ideally you don't want the presence of ESD diodes to
impact the performance of the signal during normal operation.



bhargavalluri@gmail.com wrote:
Hi,

I am trying to simulate a simple ESD ciruit( containing 2 diodes) using
cadence spectre, but my circuit is not functioning as expected.
Whatever voltage i give at the input is coming out to the output. Can
anyone tell me what can be the reason for this behavior and how i can
overcome it.

Thanks,
Alluri.
Click to expand...
 
If your input voltage source is directly tied to your input, and it has
no source resistance, how can the voltage on your input be anything
other than 5 V? As a sanity check, probe the current going through the
diode. Is it large?

bhargavalluri@gmail.com wrote:
NO,my input voltage source doesnt have any resistance and i also have a
resister at the output to compensate for any forward resistance the
diode might have.
linkin wrote:
Does your input voltage source have some source resistance?


bhargavalluri@gmail.com wrote:
Let me explain the situation better, I have two diodes as you said, a
diode from vdd to input and another from input to gnd. my vdd is 1.8 v
, and my input voltage swings from 0v to 5v. When my input is at 5v the
diode which is connected to vdd should turn ON and my output should be
1.8 v,but i am getting same 5v at output. I have tried many things like
connecting a resistor at the output and taking output from that
resistor, but nothing seems to work.


linkin wrote:
Exactly what kind of ESD functionality do you want?

For example, an analog ESD circuit might have a diode from VDD to the
input, and another diode from the input to GND. Both diodes nominally
will be reverse-biased, and it is actually desirable that your output
voltage is equal to the input voltage (they are actually the same node
in this case). Ideally you don't want the presence of ESD diodes to
impact the performance of the signal during normal operation.



bhargavalluri@gmail.com wrote:
Hi,

I am trying to simulate a simple ESD ciruit( containing 2 diodes) using
cadence spectre, but my circuit is not functioning as expected.
Whatever voltage i give at the input is coming out to the output. Can
anyone tell me what can be the reason for this behavior and how i can
overcome it.

Thanks,
Alluri.
Click to expand...
 
On Nov 13, 5:56 pm, "kev" <kevin.kelli...@gmail.com> wrote:
Hi

I am a newbie to cadence. Well I am actually a designer and didn't
really care that much before how cadence worked - I should have.
Anyway, I need to simulate standard library compnents [artisan] and
can't work out how to link these to the artist simulator. All I know is
that I have cdl netlist for the standard lib and some symbol views. I
guess I need to link the views with correct port mapping info
for the simulator. I have tried converting netlists to spectre,
modifying cdf props etc. but to be honest I don't know what am am
really doing and the cadence doc is not helpful or at least I can't
find anything.
Click to expand...
I am curious why you would like to take the effort to redo the work
that Artisan has already done. I thought it was Artisans business model
to provide their customers with already characterized libraries for
whatever technology.

If all you want to do is to have a look at the structures of the
libraries, there is a commercial tool called SpiceVision from Concept
Engineering which does a great job in recognizing structures in
netlists.

--
Svenn
 
On Nov 11, 11:17 pm, "spectrallypure" <jorgela...@gmail.com> wrote:
Dear all,

Two slightly related questions:

(Q1) Could anybody please tell if the IC tool (v5.10.41_USR2) includes
any default model files for the transistor cells "nmos4" and "pmos4" in
the "analogLib" library, that could be used in Spectre simulations?
I would like to simulate a simple inverter made with these components
whenever I need to check if an installation of this tool is working
properly on a PC, without any design kit installed yet. If the
simulation runs smoothly, the installation is considered successful. I
need to do this several times because I am trying to install cadence in
different linux distros and versions (mostly Fedora).
Click to expand...
Why bothering with Fedora?

Using the command line, I tried to find any files that could contain
the models, by running the following in the top directory if IC:

# grep -i "model .nmos4" `find . -name "*" -print`
Click to expand...
check your aliases. I experience that system administrators create
aliases to commands and "provide" these aliases to the user without
telling them. I am an enemy of "provided" aliases because they fool the
luser to think that _that_ is the proper way of functionality. I
specially think of the -i flags to mv and cp which make lusers do
stupid things on non-aliased machines. You get the pure, unaliased
version by inserting a \ "backslash" in front of the command.

However, this command, which works just fine in Solaris, doesn't work
at all in Fedora -I don't know why. And to make things worse, I HAVE
NOT been able to find a way of performing this type of content-based
file searchs by using the graphical tools for file management provided
by default with Fedora (Nautilius, etc). So, (Q2) could anybody please
tell if there exists (in Fedora 5) a way for finding files with
specific contents? I am sure there has to be some reasonable way!
Click to expand...
If your Fedora also has a decent desktop installed look for "kfind"
which has the features you want.
 
Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
 
Bernd Fischer wrote:

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.
Click to expand...
If I would have to do a lot of netlist conversion work, I would really
recomend SpiceVision and its SKILL out functionality. The price of the
license is saved worktime. I have tried the import function of ic61 and
compared to SV it is lightyears behind.

--
Svenn
 
I finally found the error (sometimes RTFM really helps;-) ). According
to the VXL UG:
Global nets or nets connected to I/O pins always survive
My Problem is now that both terminals of the inductor are connected to
an I/O pin. Therefore both nets survive and this causes the LVS errors.

Thanks for your efforts
Thomas

Andrew Beckett wrote:
On Fri, 03 Nov 2006 19:38:56 -0800, Edward Kalenda <diva@cadence.com> wrote:

On Fri, 03 Nov 2006 11:23:22 +0000, Andrew Beckett
andrewb@DcEaLdEeTnEcTe.HcIoSm> wrote:

On Wed, 01 Nov 2006 11:15:39 -0800, Edward Kalenda <diva@cadence.com> wrote:

On Wed, 01 Nov 2006 19:45:05 +0100, Thomas Ussmueller
ussmueller_wrong_email@gmx.de> wrote:

Hello all,

I have a problem with DIVA LVS and the lxRemoveDevice property. I have
included a parasitic inductor in my schematic. For LVS I want to remove
the device. Therefore I have set the lvsIgnore property to true and the
lxRemoveDevice property to (short(PLUS MINUS)).

The inductor is removed from the netlist, but the nets (net16 and
off_chip1) don't seem to be shorted. Therefore DIVA thinks that these
two nets are seperate nets and that's the reason why the netlists don't
match.

Does anybody know what I can do to fix this error?

Thanks
Thomas
Sounds like you're using Diva LVS in Analog mode. Try only setting the
lxRemoveDevice property. I think the lvsIgnore property is taking
precedence.
Ed, does Diva know about lxRemoveDevice? If it does, perhaps it is only in
recent versions? lxRemoveDevice is for VirtuosoXL, but I didn't know that
Diva had been extended to support that too?

Anyway, the other way to do this is to use the removeDevice() command in your
LVS rules - this is the Diva way of shorting devices.

Regards,

Andrew.
In Analog Artist mode, several of the Diva operations are over-ridden by
Artist. Netlisting is one of these. There is a separate OSS netlisting
module for analog mode which does various modifications to the LVS
netlist before invoking the Diva LVS binary, then it massages the LVS
output files. The lxRemoveDevice property may, or may not, be understood
by Artist LVS netlisting. I know Diva LVS netlisting does not support
any of those properties, unless OSS itself supports them under the
covers.

Hi Ed,

I'm pretty certain the Artist netlisting doesn't support this. The parasitic
filtering stuff there (which predates Diva's removeDevice()) hasn't changed in
years, AFAIK.

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
Click to expand...
 
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
Click to expand...
 
Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David


kev wrote:
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
Click to expand...
 
Hi David,
The cdl I was given was not correct so i have to wait for that.
I had tried the cdlin with that netlist but didn't seems to work but
maybe
the netlist didn't match the symbols...
will let you know how i get on.
Kevin


DReynolds wrote:

Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David


kev wrote:
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
Click to expand...
 
On 26 Nov 2006 14:43:59 -0800, "Edward" <edward.dodge@gmail.com> wrote:

I understand SLIME, the "Superior Lisp Interaction Mode for EMACS,"
is only advertised to work with these LISP implementations:

* CMU Common Lisp (CMUCL)
* Steel Bank Common Lisp (SBCL)
* OpenMCL
* LispWorks
* Allegro Common Lisp
* CLISP

http://common-lisp.net/project/slime/

But I'm wondering if anyone has found a way to get SLIME to couple with
icfb in non-graphics mode. Any ideas, Mr. Beckett?

Edward
Click to expand...
No idea, sorry. If I had a free moment, I'd give it a try. I'm not really an
EMACS person, otherwise I might have come across this and tried it out.
(I tend to use vi in lisp mode for writing SKILL code, as I know vi inside out).

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
 
You can add zero voltage DC source in series with your pin. Save the
current flowing into the + terminal.


jonashat@gmail.com wrote:
Hi all,

I was wondering if there is a way to annotate the current value coming
out of a pin in a schematic.
Click to expand...
 
unreachable point: the points those eventually do not effect the
primary output of the design.
unmapped points mean that the Golden or Revised design has no
coressponding points.

Davy źgšDĄG

Hi all,

I heard "unreachable" in Conformal mean the register do not contribute
to output. But what's "unmapped point" in Conformal mean? Does it mean
after synthesis, the net-list have no such point? And what's difference
with "unreachable" and "unmapped"?

Thanks,
Davy
Click to expand...
 
On 6 Dec 2006 01:28:57 -0800, tempora@gazeta.pl wrote:

Hello,

I have some convergence problem during pss analysis. My circuit is an
LC oscillator and when I run transient analysis it will start
oscillating properly after some 5ns. I can read the fundamental
frequency then.

However, when I run pss analysis with fund=previously_found_freq
tstab=5n the analysis will fail to converge or sometimes will find a
fundamental approximately 10x higher that that from transient analysis.

My question therefore is if I could skip the initial transient analysis
(which is run before pss) and use the results and fundamental frequency
from my transient analysis.

writefinal="./file" option in transient analysis and readns="./file"
option in pss analysis don't work.

Thank you for your help.
Click to expand...
Well, if it's finding the wrong fundamental, something is a bit fishy anyway...

Are you using a recent version?

If you use MMSIM61 (might be MMSIM611) for the simulator, you can use
the save/restart mechanism for doing this. This has been in transient for a
while, but can now be used to initialise the transient part of the pss.

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
 
Hi

I now final have a proper cdl netlist. However, when I try to cdlin
the netlsit all i get is a "mos" cell created.

I ahve also converted the netlist to spectre and am having problems
as I want to add inherited supplies to the stanard cell lib rather that
have
global VDD and VSS. I get it to netlist but it doen't work. [simple
inverter]

I changed to standard cell description fo an inverter from/to the
follwoing:

..subckt INVX1 Y A
M0 Y A VSS VSS NCH l=0.18u w=0.6u
M1 VDD A Y VDD PCH l=0.18u w=0.9u
..ends INVX1

to

simulator lang=spectre

subckt INVX1 Y A inh_vdd inh_vss
M0 ( Y A inh_vss inh_vss ) nch l=0.18u w=0.6u
M1 ( inh_vdd A Y inh_vdd ) pch l=0.18u w=0.9u
ends INVX1

However, it doesn't work so it seems that the inherited suppiles are
not being passed properly by the cdf. [componentName = INVX1 termOrder
"Y" "A" are the only 2 cdf params I set].

However if one draws a schmatci of such and inverter with inherited
supplies the componentName = subcircuit and not INVX1.

Any ideas?

Kevin


DReynolds wrote:

Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David


kev wrote:
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
Click to expand...
 
Kev, it sounds like you are not getting the correct primitives, which
usually means you are not telling cdlin where your PDK devides are when
you run cdlin.

David
kev wrote:
Hi

I now final have a proper cdl netlist. However, when I try to cdlin
the netlsit all i get is a "mos" cell created.

I ahve also converted the netlist to spectre and am having problems
as I want to add inherited supplies to the stanard cell lib rather that
have
global VDD and VSS. I get it to netlist but it doen't work. [simple
inverter]

I changed to standard cell description fo an inverter from/to the
follwoing:

.subckt INVX1 Y A
M0 Y A VSS VSS NCH l=0.18u w=0.6u
M1 VDD A Y VDD PCH l=0.18u w=0.9u
.ends INVX1

to

simulator lang=spectre

subckt INVX1 Y A inh_vdd inh_vss
M0 ( Y A inh_vss inh_vss ) nch l=0.18u w=0.6u
M1 ( inh_vdd A Y inh_vdd ) pch l=0.18u w=0.9u
ends INVX1

However, it doesn't work so it seems that the inherited suppiles are
not being passed properly by the cdf. [componentName = INVX1 termOrder
"Y" "A" are the only 2 cdf params I set].

However if one draws a schmatci of such and inverter with inherited
supplies the componentName = subcircuit and not INVX1.

Any ideas?

Kevin


DReynolds wrote:

Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David


kev wrote:
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
Click to expand...
 
I got a bit sidetracked here with cdlin - when in fact I am more
concerned on how to simulate a standard cell lib.

I can simualte if I convert the nodes VSS and VDD to VSS! and VDD! in
the netlist. but then that means that I ahev 2 global nodes i.e.e all
my stanard cell instances will be shorted through these nodes. Now I
want to be able to replace these nodes by inherited connections but I
can seem to get the cdf paramters correct for netlisting....

Kevin


DReynolds wrote:

Kev, it sounds like you are not getting the correct primitives, which
usually means you are not telling cdlin where your PDK devides are when
you run cdlin.

David
kev wrote:
Hi

I now final have a proper cdl netlist. However, when I try to cdlin
the netlsit all i get is a "mos" cell created.

I ahve also converted the netlist to spectre and am having problems
as I want to add inherited supplies to the stanard cell lib rather that
have
global VDD and VSS. I get it to netlist but it doen't work. [simple
inverter]

I changed to standard cell description fo an inverter from/to the
follwoing:

.subckt INVX1 Y A
M0 Y A VSS VSS NCH l=0.18u w=0.6u
M1 VDD A Y VDD PCH l=0.18u w=0.9u
.ends INVX1

to

simulator lang=spectre

subckt INVX1 Y A inh_vdd inh_vss
M0 ( Y A inh_vss inh_vss ) nch l=0.18u w=0.6u
M1 ( inh_vdd A Y inh_vdd ) pch l=0.18u w=0.9u
ends INVX1

However, it doesn't work so it seems that the inherited suppiles are
not being passed properly by the cdf. [componentName = INVX1 termOrder
"Y" "A" are the only 2 cdf params I set].

However if one draws a schmatci of such and inverter with inherited
supplies the componentName = subcircuit and not INVX1.

Any ideas?

Kevin


DReynolds wrote:

Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David


kev wrote:
Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

Bernd Fischer wrote:

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd
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