cell libraries and place and route

[Andrew Beckett]

Erik,

OP is not an OCEAN function. It is an ADE calculator function, and only properly
works when the simulation is run from ADE. Similarly, VT, VF, etc.

You should use the OCEAN pv() function instead. Similarly for VT, VF, you
should use v(). Sometimes OP and VT, VF etc work (as you've seen), but
not always - and it is _much_ safer to use the documented OCEAN data access
functions in an OCEAN script.

Andrew.

On 10 Jul 2003 20:55:22 -0700, erikwanta@starband.net (Erik Wanta) wrote:

I have an OCEAN script. If I don't use resultsDir() and then do
OP("/R0" "i") I get 3mA. When I use resultsDir(), I get nil for
OP("/R0" "i"). Note that the model for R0 is a subcircuit. Why does
it work w/o resultsDir() and not without? I am thinking it has
something to do with the ananlog mapping directory (amap).
---
Erik

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Erik Wanta]

Andrew:
I wrote a program that:
1. has the user create output expressions in ADE
2. generates several OCEAN scripts with asiWriteOceanScript
3. submits the scripts in parallel with SGE or LSF
4. I was going to use resultsDir to specify a unique results
directory for each script so that the runs don't overwrite themselves

I would have to parse the generated ocean script and look for OP, VT,
VF, ... in the output expressions and replace them with OCEAN DA
functions. That seems too painful.

pv() doesn't work either. I have a resistor subcircuit that is made
up of 2 resistors and 3 capacitors. I can get the current through
each resistor in the subcircuit, but pv("/R0" "i") doesn't work.
OP("R0.res1" "i") and pv("R0.res1" "i") work. I think the reason why
OP("R0" "i") works when I don't use resultsDir() has to do with the
amap directory in the netlist directory, correct? The netlist I am
specifying with design() in the OCEAN script has an amap directory. I
don't understand why it would use the amap directory w/o resultsDir()
and not with. Any ideas?
---
Erik


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<63usgv8fkpap8l02pb64tqq61n71bjlv2p@4ax.com>...

Erik,

OP is not an OCEAN function. It is an ADE calculator function, and only properly
works when the simulation is run from ADE. Similarly, VT, VF, etc.

You should use the OCEAN pv() function instead. Similarly for VT, VF, you
should use v(). Sometimes OP and VT, VF etc work (as you've seen), but
not always - and it is _much_ safer to use the documented OCEAN data access
functions in an OCEAN script.

Andrew.

On 10 Jul 2003 20:55:22 -0700, erikwanta@starband.net (Erik Wanta) wrote:

I have an OCEAN script. If I don't use resultsDir() and then do
OP("/R0" "i") I get 3mA. When I use resultsDir(), I get nil for
OP("/R0" "i"). Note that the model for R0 is a subcircuit. Why does
it work w/o resultsDir() and not without? I am thinking it has
something to do with the ananlog mapping directory (amap).
---
Erik

 

[Andrew Beckett]

Quick answer...

The save OCEAN script option does the translation of VT, VF etc I think...
for this very reason (I may be wrong).
With pv(), you need to have done the selectResults() first, to pick
the dcOp results. Otherwise you need to use the ?result arg to pv
to pick the results you want.

Got to go...

Andrew.

On 11 Jul 2003 07:47:23 -0700, erikwanta@starband.net (Erik Wanta) wrote:

Andrew:
I wrote a program that:
1. has the user create output expressions in ADE
2. generates several OCEAN scripts with asiWriteOceanScript
3. submits the scripts in parallel with SGE or LSF
4. I was going to use resultsDir to specify a unique results
directory for each script so that the runs don't overwrite themselves

I would have to parse the generated ocean script and look for OP, VT,
VF, ... in the output expressions and replace them with OCEAN DA
functions. That seems too painful.

pv() doesn't work either. I have a resistor subcircuit that is made
up of 2 resistors and 3 capacitors. I can get the current through
each resistor in the subcircuit, but pv("/R0" "i") doesn't work.
OP("R0.res1" "i") and pv("R0.res1" "i") work. I think the reason why
OP("R0" "i") works when I don't use resultsDir() has to do with the
amap directory in the netlist directory, correct? The netlist I am
specifying with design() in the OCEAN script has an amap directory. I
don't understand why it would use the amap directory w/o resultsDir()
and not with. Any ideas?
---
Erik


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<63usgv8fkpap8l02pb64tqq61n71bjlv2p@4ax.com>...
Erik,

OP is not an OCEAN function. It is an ADE calculator function, and only properly
works when the simulation is run from ADE. Similarly, VT, VF, etc.

You should use the OCEAN pv() function instead. Similarly for VT, VF, you
should use v(). Sometimes OP and VT, VF etc work (as you've seen), but
not always - and it is _much_ safer to use the documented OCEAN data access
functions in an OCEAN script.

Andrew.

On 10 Jul 2003 20:55:22 -0700, erikwanta@starband.net (Erik Wanta) wrote:

I have an OCEAN script. If I don't use resultsDir() and then do
OP("/R0" "i") I get 3mA. When I use resultsDir(), I get nil for
OP("/R0" "i"). Note that the model for R0 is a subcircuit. Why does
it work w/o resultsDir() and not without? I am thinking it has
something to do with the ananlog mapping directory (amap).
---
Erik

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Erik Wanta]

Vicky:
Please provide more details. What is ilim and ASW?
---
Erik


mvvijay78@rediffmail.com (Vicky) wrote in message news:<b82ef6fb.0307090328.3e2030be@posting.google.com>...

Hi,
Can some one explain how these parts are modeled.
Vicky

 

[Erik Wanta]

Jason:
You can convert psf to ascii with:
psf -i tran.tran -o tran.txt

Cadence has an eye diagram function:
eyeDiagram ( o_waveform n_start n_stop n_period ) => o_waveform/nil

This function gives an eye-diagram plot of the input waveform signal.
It returns the waveform object of the eye-diagram plot.

See the Affirma RF Simulator (SpectreRF) User Guide, Chapter 13
Behavioral Models and Methods for Top Down Design for some examples.

Check out awvSimplePlotExpression and awvPlotExpression.
---
Erik


"Jason D. Bakos" <jbakos@cNOs.pSPAMitt.edu> wrote in message news:<bev3dd$k86$1@usenet01.srv.cis.pitt.edu>...

Hi everyone!

My research group has recently switched from Tanner to a set of the Cadence
tools for doing IC design. Recently I've been spending some time simulating
my designs with Spectre/Affirma (Analog Environment): Affirma Analog
Circuit Design 4.4.6.100.81. I need to generate eye diagrams, so I'm
plotting against a dummy sawtooth voltage source. Unfortunately, this
causes redraw lines which makes the plot look terrible. If you switch to
"data points only"-mode for the curves, you get thousands of rather large
numbers on the plots. This is okay, but the big numbers on the plots just
don't look very good. So here are my questions:

1. When plotting in "data points only"-mode, is there a way to have Spectre
plot small shapes (or dots) instead of the traditional curve numbers? If
not, is there any way to change the font size of the numbers (to "tiny") to
make the plot more readable? I assume that if such a feature exists, it
would be an undocumented command-line command.

2. Is there any way I can export the plot data to an ASCII format? If not,
does anyone have any ideas about the binary format specification for the
"tran.tran" datafile that's generated by Spectre? If I could figure out the
format of this file, I could easily write a small program that will perform
an ASCII conversion. I'm aware that you can export PostScript versions of
the plot, but if I could get the raw data as ASCII, I could generate the eye
diagrams in Excel.

Thanks so much!

-Jason D. Bakos
Research Assistant
Microelectronics Lab
Department of Computer Science
University of Pittsburgh

 

[Erik Wanta]

Selvakumar:
Option 1:
All the documentation is at sourcelink.cadence.com.

Option 2:
SE 5.4 has html in the doc folder.

Option 3:
As far as I know, *.obk are just Adobe framemaker files. To open,
just type the following if you have framemaker:
fmclient -f chap1.obk &

Option 4:
obk stands for openbook. Just type openbook & to view the *.obk
files. openbook is just a framemaker wrapper from what I can see.
---
Erik


selvakumar_in@hotmail.com wrote in message news:<63f7196c.0307150342.1c81ead3@posting.google.com>...

hello there,

We are having cadence dsmse53 package, which includes documentations
also.

The problem was I can't read the documentation files ,as they are
*.obk extension files.

Is there any provision to read that kind of files ?

or any method to convert it into html files ?

our cadence tool is installed in sun solaris sparc version.

your suggestions are most welcomed.

regards

selvakumar

 

[Svenn Are Bjerkem]

Svenn Are Bjerkem wrote:

For the record, on http://www.xfree86.org/4.2.1/XF86Config.5.html in the
section on Visual, TrueColor is listed as one of the alternatives. I know
that I don't have that option set on the linux workstation, yet ...

Well, no luck. The Visual "TrueColor" is default, so I already had
true-color display. Color are still flashing. Turning back to backup
solution with X-Win32 and pseudocolors, *sigh*
--
Svenn Bjerkem

 

[Pete nospam Zakel]

In article <bf1j4u$gnh$04$1@news.t-online.com> svenn@bjerkem.de writes:

Svenn Are Bjerkem wrote:

For the record, on http://www.xfree86.org/4.2.1/XF86Config.5.html in the
section on Visual, TrueColor is listed as one of the alternatives. I know
that I don't have that option set on the linux workstation, yet ...

Well, no luck. The Visual "TrueColor" is default, so I already had
true-color display. Color are still flashing. Turning back to backup
solution with X-Win32 and pseudocolors, *sigh*

Are you *sure* 24-bit TrueColor is the root visual? You should verify with
xdpyinfo. You can also use xwininfo to check the visual being used by DFII
windows.

-Pete Zakel
(phz@seeheader.nospam)

"The hearing ear is always found close to the speaking tongue, a custom
whereof the memory of man runneth not howsomever to the contrary, nohow."

 

[eda support guy]

Vladimir wrote:

Hi!
Does anybody know any information about a bug of StreamOut or
StreamIN? I heard something like that from my friend. But recently we
met the same situation. When I translated GDS file we transferred to
foundry (only one layer) back to Cadence I found out the original
layout and GDS translated layout are different.
I checked PIPO.log file. There is no error. Moreover the missed layout
according to PIPO.log was succesfully translated. I checked statistics
related to missed block. That showed that a hadred of rectangulars,
poligons, cell and so on was successfully translated without any
problem. The only one layer was translated. But when I opened layout
one block has no layout. I suppose this happened for version 4.4.5 or
4.4.6.
Vladimir Fomin

Vladimir,

Masks are expensive enough... When tapeing-out I d recommend you put
yourself in paranoid mode and perform a check like this:
-stream-out
-snap gds2 to mask grid
-stream-in
-use dracula/diva/assura to Xor the streamed-in and source db's.

 

[eda support guy]

Kuan Zhou wrote:

Hi,
Are you using Cadence too?I remember you are an FPGA guy.
Exceed 7.0 also has the same problem.I use Xmanager instead of Exceed.
The cadence program requires pseudo 8 bit color plane.Exceed can't solve
this problem perfectly.
I disagree on this: all versions I used with cadence df2, from exceed

5 to 8, can provide a pseudocolor visual that works OK. I could also set
it up in version 6.2 to provide pseudocolor visual under a truecolor
root window, which removes all color-flashing problems, but could not
reproduce this successfully in version 8. I think that only big names
like sun and sgi do this correctly; maybe exceeed is just not there yet.

The magic setup with 6.2 was:
color mode= truecolor (24 bit)
max backing store = always
default ~ = when mapped
minimum ~ = when mapped

If you then run xdpyinfo you should see that the root visual color
class is truecolor in a depth of 24 , but that at the same time
pseudocolor in 8 bit depth is also listed as available. I have been
using 4.4.2 with this, and even sometimes 4.4.2 with LBX compression
(over a WAN access) but this tended to crash more than once a day, thus
above the the icfb floor crash rate ;-)
I ve tried a few Xservers, including those from thin clients like
exceed-on-demand, citrix ICA /metaframe , ultraVNC , NX (the follower of
DXPC), those from unices like Xsun and HPUX, and off course XFree86, and
some PC implementations I forgot the name of. I consider exceed a rather
good server.

 

[eda support guy]

First, a few remarks on Thomas' problem:
- the callbacks from AMS are in password encrypted skill files.
- the m factor, support can easily be dropped by those writing the aulvs
CDF or the diva extraction and verification decks. Our layouters often
perform this kind of schematic modification (replacing multiplicity
factor by a vector of devices) to put themselves out of troubles -or to
simply get the possibility to put rings where the pcell didn t allow it.
Identical problems appear with "fold", or "serpentine" parameters, maybe
because these are in the grey area between circuit and device.

Using instance names such as IX<3:0> is less efficient than using an m-factor
of 4 for simulation purposes. With IX<3:0> you get four devices in the netlist,
which means that there are four sets of equations for the simulator to have
to compute, rather than a multiplier in one set of equations.
Since VXL can handle the m-factor to split into multiple devices (and has been
able to for many releases), it seems that the kit is forcing you into worse
simulator performance!

Andrew,

You mention here something that always puzzled me. Putting 2 identical
devices, in parallel in a netlist does increase the simulation cpu-time
compared to putting one device with m=2. This is true with spectre, and
also with any spice-like simulator I know of.

Now, would it not be easy to do a little "network preprocessing" in
spectre and replace identical devices in parallel by devices with an M>1
? This, of course applies not only to device models or devices modelled
as subcircuits, to any subcircuit, or two identical "parts" in a circuit.
Those two identical parts should have their nodes virtually shorted,
so that the admittance matrix size will be reduced.

I admit this can bring it share of problems, when DCmatch or other
sensitivity analysis, but the simulation speedup would be quite worth
the trouble, wouldn t it ? It would be too easy, so I m probably

--
Frederic

 

[Erik Wanta]

First, a few remarks on Thomas' problem:
- the callbacks from AMS are in password encrypted skill files.
no they are not

Why do you want to drop the m factor and replace with iterated
instances instead of using m with generate multiple instances selected
in VXL?
---
Erik


eda support guy <cad_support_at_catena_dot_the_netherlands> wrote in message news:<3f17d2e2@shknews01>...

First, a few remarks on Thomas' problem:
- the callbacks from AMS are in password encrypted skill files.
- the m factor, support can easily be dropped by those writing the aulvs
CDF or the diva extraction and verification decks. Our layouters often
perform this kind of schematic modification (replacing multiplicity
factor by a vector of devices) to put themselves out of troubles -or to
simply get the possibility to put rings where the pcell didn t allow it.
Identical problems appear with "fold", or "serpentine" parameters, maybe
because these are in the grey area between circuit and device.

Using instance names such as IX<3:0> is less efficient than using an m-factor
of 4 for simulation purposes. With IX<3:0> you get four devices in the netlist,
which means that there are four sets of equations for the simulator to have
to compute, rather than a multiplier in one set of equations.
Since VXL can handle the m-factor to split into multiple devices (and has been
able to for many releases), it seems that the kit is forcing you into worse
simulator performance!

Andrew,

You mention here something that always puzzled me. Putting 2 identical
devices, in parallel in a netlist does increase the simulation cpu-time
compared to putting one device with m=2. This is true with spectre, and
also with any spice-like simulator I know of.

Now, would it not be easy to do a little "network preprocessing" in
spectre and replace identical devices in parallel by devices with an M>1
? This, of course applies not only to device models or devices modelled
as subcircuits, to any subcircuit, or two identical "parts" in a circuit.
Those two identical parts should have their nodes virtually shorted,
so that the admittance matrix size will be reduced.

I admit this can bring it share of problems, when DCmatch or other
sensitivity analysis, but the simulation speedup would be quite worth
the trouble, wouldn t it ? It would be too easy, so I m probably

 

[eda support guy]

This is "frame" format from adobe.

There was a blessed time when adobe gave-out the viewer for frame files,
running under windows3.1
It worked OK with the docs from 4.4.2 , but last time I went tried adobe
download site, there was no more viewer, but you might be lucky if you
search all the repositories like simtel, tucows and such.

I once wrote a framemaker script to convert all openbooks to pdf. If you
have framemaker, I can sent this to you.

 

[B]

Me wrote:

Hi all,

We have designed a memory generator for a customer. But they have some
complaints. One of them is that we have given them pin names in the
style "dout_0", but they want the style "dout[0]". (Which is the
default naming convention for buses in Synopsys Liberty, although it
can be changed in Liberty).

So I went to my code to change the pin names, and found that ROD/SKILL
will not accept square brackets in net names:

\w *WARNING* rodCreatePath: ?netName: "[" characters in name not
allowed - "dout[0]"
\w *WARNING* rodCreatePath: ?netName: "]" characters in name not
allowed - "dout[0]"
\w *WARNING* rodCreatePath: ?termName: "[" characters in name not
allowed - "dout[0]"
\w *WARNING* rodCreatePath: ?termName: "]" characters in name not
allowed - "dout[0]"
\e *Error* rodCreatePath: command failed

So what do I do? Is there any way to get square brackets into the
names. (Backslashes didn't help).

Perhaps my problem is that I am using rodCreatePath to make my pins
(ROD does not have "pins" or "ports" as such). Is that wrong? How
should I be creating pins/ports in SKILL? The customer is using LEF
and Liberty and I think they will be using the memories in ASIC
designs being put together with Silicon Ensemble.

This has been my company's first attempt at using Cadence tools, so
perhaps we have gone about pins/ports in the wrong way. Any advice
appreciated.

Peter
One quicker way to do it is

1)name your busses using <> (instead of the [])
2)use perl (or whatever you know) to change the output file (from <> to []).
HTH

 

[B]

JC7 wrote:

We are using Cadence on Sun/Solaris8 with two monitors, but can not get it
setup to where we can drag a window from monitor to the other. I would like
to have my layout fill up one monitor and have the LSW, CIW, Lib Browser,
etc. on the other monitor.
Anyone know how to do this?

Thanks,

Joe Clark
joe.clark@NoSpam@adtran.com





Don't have the above config. But here is an idea that might work

I am assuming that both monitors get the same data in the begining
(which is a reasonable assumption)
Normally you've 4 virtual desktops(VD) (by default). For convenience,
call one of them "layout" and another "ciw"
move the layout window to "layout" VD. The CIW and the rest are left
in the "ciw" VD.

Now on the second monitor which is reserved for layout, click in
the "layout" VD.

Let me know if this works

 

[Pete nospam Zakel]

In article <xvcTa.307$R27.35@fe01.atl2.webusenet.com> "JC7" <no@spam.com> writes:

We are using Cadence on Sun/Solaris8 with two monitors, but can not get it
setup to where we can drag a window from monitor to the other. I would like
to have my layout fill up one monitor and have the LSW, CIW, Lib Browser,
etc. on the other monitor.
Anyone know how to do this?

The problem is that the two monitors are separate displays, and our software
(like most software) only deals with one display at a time.

If you want to treat the two monitors as one display, use +xinerama mode.
Note you'll want to have the same graphics card for both monitors for this
to work well.

Do "man Xsun" to get information about it. You add the argument to the
line beginning with ":0" at the end of the file /etc/dt/config/Xservers.
If this file doesn't exist, copy it from /usr/dt/config/Xservers.

Note also that we don't test this configuration at Cadence, as far as I know.

-Pete Zakel
(phz@seeheader.nospam)

"Don't worry over what other people are thinking about you. They're too
busy worrying over what you are thinking about them."

 

[daytripper]

On 22 Jul 2003 10:53:41 -0700, pxhxz@cadence.com (Pete nospam Zakel) wrote:

In article <xvcTa.307$R27.35@fe01.atl2.webusenet.com> "JC7" <no@spam.com> writes:
We are using Cadence on Sun/Solaris8 with two monitors, but can not get it
setup to where we can drag a window from monitor to the other. I would like
to have my layout fill up one monitor and have the LSW, CIW, Lib Browser,
etc. on the other monitor.
Anyone know how to do this?

The problem is that the two monitors are separate displays, and our software
(like most software) only deals with one display at a time.

If you want to treat the two monitors as one display, use +xinerama mode.
Note you'll want to have the same graphics card for both monitors for this
to work well.

Do "man Xsun" to get information about it. You add the argument to the
line beginning with ":0" at the end of the file /etc/dt/config/Xservers.
If this file doesn't exist, copy it from /usr/dt/config/Xservers.

Note also that we don't test this configuration at Cadence, as far as I know.

-Pete Zakel
(phz@seeheader.nospam)

"Don't worry over what other people are thinking about you. They're too
busy worrying over what you are thinking about them."

fwiw, you can stretch any tool window across three 21" monitors - at least
when they're attached to a Parhelia and running XP Pro.

Even better: running multiple tools each in their own, full, screen. The bees
knees for board design, with schematic capture on one monitor, board layout in
another, and si suite running in the third.

Having a pair of 3ghz Xeon's under the hood doesn't hurt...

/daytripper (If you have the means, I highly recommend it ;-)

 

[JC7]

Thanks for the reply.

That would work, but I want to see the layout, LSW and CIW all at one time,
just
over more real estate.


"B" <bekeur@fnal.gov> wrote in message news:bfjr99$ms$1@info4.fnal.gov...

JC7 wrote:
We are using Cadence on Sun/Solaris8 with two monitors, but can not get
it
setup to where we can drag a window from monitor to the other. I would
like
to have my layout fill up one monitor and have the LSW, CIW, Lib
Browser,
etc. on the other monitor.
Anyone know how to do this?

Thanks,

Joe Clark
joe.clark@NoSpam@adtran.com





Don't have the above config. But here is an idea that might work
I am assuming that both monitors get the same data in the begining
(which is a reasonable assumption)
Normally you've 4 virtual desktops(VD) (by default). For convenience,
call one of them "layout" and another "ciw"
move the layout window to "layout" VD. The CIW and the rest are left
in the "ciw" VD.

Now on the second monitor which is reserved for layout, click in
the "layout" VD.

Let me know if this works

 

[Me]

B <bekeur@fnal.gov> wrote in message news:<bfjegf$lqo$1@info4.fnal.gov>...

Me wrote:
Hi all,

We have designed a memory generator for a customer. But they have some
complaints. One of them is that we have given them pin names in the
style "dout_0", but they want the style "dout[0]". (Which is the
default naming convention for buses in Synopsys Liberty, although it
can be changed in Liberty).

So I went to my code to change the pin names, and found that ROD/SKILL
will not accept square brackets in net names:

\w *WARNING* rodCreatePath: ?netName: "[" characters in name not
allowed - "dout[0]"
\w *WARNING* rodCreatePath: ?netName: "]" characters in name not
allowed - "dout[0]"
\w *WARNING* rodCreatePath: ?termName: "[" characters in name not
allowed - "dout[0]"
\w *WARNING* rodCreatePath: ?termName: "]" characters in name not
allowed - "dout[0]"
\e *Error* rodCreatePath: command failed

So what do I do? Is there any way to get square brackets into the
names. (Backslashes didn't help).

Perhaps my problem is that I am using rodCreatePath to make my pins
(ROD does not have "pins" or "ports" as such). Is that wrong? How
should I be creating pins/ports in SKILL? The customer is using LEF
and Liberty and I think they will be using the memories in ASIC
designs being put together with Silicon Ensemble.

This has been my company's first attempt at using Cadence tools, so
perhaps we have gone about pins/ports in the wrong way. Any advice
appreciated.

Peter
One quicker way to do it is
1)name your busses using <> (instead of the [])
2)use perl (or whatever you know) to change the output file (from <> to []).
HTH

For internal use, such hacks are no problem (we do it all the time .
But when delivering code to an external customer, that approach would
be a last resort.

There must be a better solution!

Peter

 

[B]

selvakumar_in@hotmail.com wrote:

hai

i am new to cadence tool, i would like to know how one can write the
DRC file of thier own ? whether a foundry ascess is mandatory for
creating those DRC files, tech files etc relating to layout and
further process.

please give me advice on GDS formation and what is mean by tape out

needed your succour

regards

selvakumar

My answer here is based on some of you previous questions.
Writing a DRC file from scratch requires a certain expertise
which I am assuming you don't have it now. So, your best
bet is to ask for a kit (you chip will be fabbed anyway).
In the kit you have DRC files for different tools. Pick
the one you're interesd in and study it. Then go from there.
If you're in a university, you can get (thru your instructor)
these kits from MOSIS or CMP or EUROPRACTICE ...
HTH