cell libraries and place and route

Hi,

Maybe someone could clarify one more question in this thread, please.
Is there is any possibility to deal with two-dimensional arrays of
instances and wires?
I have a 2D array of cells, and so far I could not find a way to
instantiated it, rather than
creating an additional component X- which is 1D array, and than creating
an array of X's.

And correspondingly is there a way to index wire in a 2D manner.

Thank you.
Alex


Virtuoso Schematic Editor User Guide,
Section: Multiple-Bit Wire Connections
Section: Wire-to-Iterated Instance Connections
Section: Multiple-Bit Wire Naming Conventions


Bernd

JC wrote:
Hi,
Using the Cadence schematic tool, I have a cell instantiated 128 times,
Icell1<127:0>.
I want groups of 4 cells at the time to have the same input, so there
will be 32 signals, x<31:0> going to 128 cells.
I can label the bus to the input
etc., x<1>, x<1>, x<1>, x<1>, x<0>, x<0>, x<0>, x<0>
but it is a very long string.
What is the syntax to abbreviate it, such as
etc., ((x<1>) *4), ((x<0>) *4)
or something even shorter such as
bit=0; (((x<bit + 1>) *4) *32)
Thanks,
Joe
joe.clark@nospm@adtran.com




--
Alex
 
Does cadence's distributed processing support multiple processor
working on the same job? I have large transient simulations that take
ages to be completed when run on a single processor, can distributed
processing split the task to multiple processors getting them to
calculate the solution togehter reducing the time needed

Thanks!
 
On 11 Apr 2006 09:57:32 -0700, "lorak88ATgmail.com" <lorak88@gmail.com> wrote:

Does cadence's distributed processing support multiple processor
working on the same job? I have large transient simulations that take
ages to be completed when run on a single processor, can distributed
processing split the task to multiple processors getting them to
calculate the solution togehter reducing the time needed

Thanks!
Click to expand...
Well, spectre does have some (limited) multi-threading options - for example,
you can multi-thread the model equation evaluation for bsim3v3/bsim4 models -
see the options on the Setup->Options->Analog form to do with multi-threading.
You need to have at least 512 devices (256 per thread) for this to work though.

It can't do any time-based splitting of the simulation (would be hard, since
time tends to run sequentially in my experience, and it's hard to know what
should be happening at 1u, 2u, 3u if you've not seen the previous part of
the simulation!)

With things like monte-carlo, the distributed processing can split the jobs into
chunks - but you can't split it within a long transient, as you've suggested.

One other thing - the "flexible balance" mode for SpectreRF's PSS/QPSS
also allows multi-threading.

Regards,

Andrew.
 
"tech11" <tech11@sohu.com> Đ´ČëĎűϢĐÂÎĹ:eenqbj$cpm$1@news.cn99.com...
Hi,

I'm one layout engineer and diffusion layer connecting is prohibited in
my design. If one diffusion path connect to two different net at the same
time, the diff will run as one connecting line or one resistor(The blue
part in the attachment), in my design, such active connecting should be
checked out and correct them. But since diffusion layer is used so much,
How should I distinguish these diffusion? Thanks for your help!

Have a good day!

Regards,

Joffre



Does nobody know how to do it? Don't you check the connecting diffusion
Click to expand...
layer in drc or lvs verification? It's a bad news. I'm using dracula to do
it, who may give me some idea? Thanks for your help!

Have a good day!

Regards,

Joffre
 
On Thu, 21 Sep 2006 09:45:23 +0800, "tech11" <tech11@sohu.com> wrote:

"tech11" <tech11@sohu.com> Đ´ČëĎűϢĐÂÎĹ:eenqbj$cpm$1@news.cn99.com...
Hi,

I'm one layout engineer and diffusion layer connecting is prohibited in
my design. If one diffusion path connect to two different net at the same
time, the diff will run as one connecting line or one resistor(The blue
part in the attachment), in my design, such active connecting should be
checked out and correct them. But since diffusion layer is used so much,
How should I distinguish these diffusion? Thanks for your help!

Have a good day!

Regards,

Joffre



Does nobody know how to do it? Don't you check the connecting diffusion
layer in drc or lvs verification? It's a bad news. I'm using dracula to do
it, who may give me some idea? Thanks for your help!

Have a good day!

Regards,

Joffre
Click to expand...
If you were doing it with Diva, I would suggest using the soft clause in
geomConnect to declare diffusion as soft. That would get you an error
wherever you draw the situation you describe.

In Dracula, you might try stamping the connectivity to the diffusion
instead of connecting to it directly. Much like how a well is stamped.
 
"Edward Kalenda" <diva@cadence.com>
??????:m464h29062n6v0n1uutfvr3ihpj068vluh@4ax.com...
On Thu, 21 Sep 2006 09:45:23 +0800, "tech11" <tech11@sohu.com> wrote:


"tech11" <tech11@sohu.com> Đ´ČëĎűϢĐÂÎĹ:eenqbj$cpm$1@news.cn99.com...
Hi,

I'm one layout engineer and diffusion layer connecting is prohibited
in
my design. If one diffusion path connect to two different net at the
same
time, the diff will run as one connecting line or one resistor(The blue
part in the attachment), in my design, such active connecting should be
checked out and correct them. But since diffusion layer is used so much,
How should I distinguish these diffusion? Thanks for your help!

Have a good day!

Regards,

Joffre



Does nobody know how to do it? Don't you check the connecting diffusion
layer in drc or lvs verification? It's a bad news. I'm using dracula to do
it, who may give me some idea? Thanks for your help!

Have a good day!

Regards,

Joffre


If you were doing it with Diva, I would suggest using the soft clause in
geomConnect to declare diffusion as soft. That would get you an error
wherever you draw the situation you describe.

In Dracula, you might try stamping the connectivity to the diffusion
instead of connecting to it directly. Much like how a well is stamped.
Click to expand...
I'm not familiar with Diva and the same status with my colleagues. So it's
more proper to resolve it with Dracula. If I stamp active to connecting
layer, I'll have to modify every device's definition, which maybe lead out
more errors. Is there any way to check out the connecting active through
operation? I've tried soft-connecting, but it's not the just way.

Have a good day!

Regards,

Joffre
 
On Thu, 21 Sep 2006 14:01:09 +0800, "tech11" <tech11@sohu.com> wrote:

If you were doing it with Diva, I would suggest using the soft clause in
geomConnect to declare diffusion as soft. That would get you an error
wherever you draw the situation you describe.

In Dracula, you might try stamping the connectivity to the diffusion
instead of connecting to it directly. Much like how a well is stamped.

I'm not familiar with Diva and the same status with my colleagues. So it's
more proper to resolve it with Dracula. If I stamp active to connecting
layer, I'll have to modify every device's definition, which maybe lead out
more errors. Is there any way to check out the connecting active through
operation? I've tried soft-connecting, but it's not the just way.

Have a good day!

Regards,

Joffre
Click to expand...
In Dracula you'd use the SCONNECT command instead of the CONNECT
command. Although it sounds as if you've tried that. I don't think I understand
exactly what you're trying to do - perhaps you need to cut the diffusion
somehow. The previous post mentioned an attachment, which I've not seen.

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
 
"Andrew Beckett" <andrewb@DcEaLdEeTnEcTe.HcIoSm>
??????:gsr4h2p4j88otbve6ba914ldcrldaulbml@4ax.com...
On Thu, 21 Sep 2006 14:01:09 +0800, "tech11" <tech11@sohu.com> wrote:



If you were doing it with Diva, I would suggest using the soft clause in
geomConnect to declare diffusion as soft. That would get you an error
wherever you draw the situation you describe.

In Dracula, you might try stamping the connectivity to the diffusion
instead of connecting to it directly. Much like how a well is stamped.

I'm not familiar with Diva and the same status with my colleagues. So it's
more proper to resolve it with Dracula. If I stamp active to connecting
layer, I'll have to modify every device's definition, which maybe lead out
more errors. Is there any way to check out the connecting active through
operation? I've tried soft-connecting, but it's not the just way.

Have a good day!

Regards,

Joffre


In Dracula you'd use the SCONNECT command instead of the CONNECT
command. Although it sounds as if you've tried that. I don't think I
understand
exactly what you're trying to do - perhaps you need to cut the diffusion
somehow. The previous post mentioned an attachment, which I've not seen.

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
Click to expand...
Andrew,

If you wanna check sconnect, the layer must have no connecting, but since I
have no way to distinguish the connecting diffusion from NSD/PSD, and in
order to get one mos, you'll have to set up connecting for NSD/PSD, this is
one inconsistency between connecting diffusion's soft-connect check and
NSD/PSD's connecting definition. Do you have a way to distinguish them?
Either do you check connecting active in your PDK? How should you do it?

Thanks for your help!

B.R.

Joffre
 
Hi,

I am wondering if it is possible to access and plot the transient
voltage of a net within an extracted view via the VT("/<something")
method? I was able to save and plot the current transients (by using
the IT command) )within the extracted view, but for some reason s i
could not do it for the voltage.

Thanks!
 
I guess this is because your net gets broken up by
RC limbs and the original net name was not kept.

With Assura you can either probe the net in the schematic if
you have used the config view to simulate your
extracted view and do a so called 'out of context'
probing, then a X will be displayed in the schematic and
shows the closed limb to probe.

Or with Assura and Diva you can make the interconnect
layers with the purpose "net" valid and probe direct form your
extraced view.

Bernd

lorak88ATgmail.com wrote:
Hi,

I am wondering if it is possible to access and plot the transient
voltage of a net within an extracted view via the VT("/<something")
method? I was able to save and plot the current transients (by using
the IT command) )within the extracted view, but for some reason s i
could not do it for the voltage.

Thanks!
Click to expand...
 
On Mon, 25 Sep 2006 18:52:37 +0800, "tech11" <tech11@sohu.com> wrote:

Andrew,

If you wanna check sconnect, the layer must have no connecting, but since I
have no way to distinguish the connecting diffusion from NSD/PSD, and in
order to get one mos, you'll have to set up connecting for NSD/PSD, this is
one inconsistency between connecting diffusion's soft-connect check and
NSD/PSD's connecting definition. Do you have a way to distinguish them?
Either do you check connecting active in your PDK? How should you do it?

Thanks for your help!

B.R.

Joffre
Click to expand...
Normally it would be the connection from diffusion to well or substrate that
would be done with an sconnect in this case - or it could be from metal to
nsd/psd - assuming that you don't want to allow a connection down onto diffusion
and then through diffusion and back out onto metal (which was not connected to
the first metal).

I think you should be able to use an sconnected NSD/PSD for the mos terminals
(I'm a bit rusty with writing Dracula rules, and I'm writing this in a hotel in
the middle of nowhere, so can't check).

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
 
"Andrew Beckett" <andrewb@DcEaLdEeTnEcTe.HcIoSm>
??????:6j1hi2d9cmj37qc6893uqtr3jntkp9fclk@4ax.com...
On Mon, 25 Sep 2006 18:52:37 +0800, "tech11" <tech11@sohu.com> wrote:

Andrew,

If you wanna check sconnect, the layer must have no connecting, but since
I
have no way to distinguish the connecting diffusion from NSD/PSD, and in
order to get one mos, you'll have to set up connecting for NSD/PSD, this
is
one inconsistency between connecting diffusion's soft-connect check and
NSD/PSD's connecting definition. Do you have a way to distinguish them?
Either do you check connecting active in your PDK? How should you do it?

Thanks for your help!

B.R.

Joffre


Normally it would be the connection from diffusion to well or substrate
that
would be done with an sconnect in this case - or it could be from metal to
nsd/psd - assuming that you don't want to allow a connection down onto
diffusion
and then through diffusion and back out onto metal (which was not
connected to
the first metal).

I think you should be able to use an sconnected NSD/PSD for the mos
terminals
(I'm a bit rusty with writing Dracula rules, and I'm writing this in a
hotel in
the middle of nowhere, so can't check).

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
Click to expand...
Andrew,

Thanks for your answer. Because it's necessary to set up connect between
diffusion and well/substrate, I've writed one rule file to check out the
connecting diffusion layer alone, which cancel the connect defination of
diff. And the other rule file to run the normal lvs check which define diff
as one connect layer. Maybe it's fussy but it works well.

Have a good day!

B.R.

Joffre
 
On Wed, 01 Nov 2006 11:15:39 -0800, Edward Kalenda <diva@cadence.com> wrote:

On Wed, 01 Nov 2006 19:45:05 +0100, Thomas Ussmueller
ussmueller_wrong_email@gmx.de> wrote:

Hello all,

I have a problem with DIVA LVS and the lxRemoveDevice property. I have
included a parasitic inductor in my schematic. For LVS I want to remove
the device. Therefore I have set the lvsIgnore property to true and the
lxRemoveDevice property to (short(PLUS MINUS)).

The inductor is removed from the netlist, but the nets (net16 and
off_chip1) don't seem to be shorted. Therefore DIVA thinks that these
two nets are seperate nets and that's the reason why the netlists don't
match.

Does anybody know what I can do to fix this error?

Thanks
Thomas

Sounds like you're using Diva LVS in Analog mode. Try only setting the
lxRemoveDevice property. I think the lvsIgnore property is taking
precedence.
Click to expand...
Ed, does Diva know about lxRemoveDevice? If it does, perhaps it is only in
recent versions? lxRemoveDevice is for VirtuosoXL, but I didn't know that
Diva had been extended to support that too?

Anyway, the other way to do this is to use the removeDevice() command in your
LVS rules - this is the Diva way of shorting devices.

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
 
On Fri, 03 Nov 2006 11:23:22 +0000, Andrew Beckett
<andrewb@DcEaLdEeTnEcTe.HcIoSm> wrote:

On Wed, 01 Nov 2006 11:15:39 -0800, Edward Kalenda <diva@cadence.com> wrote:

On Wed, 01 Nov 2006 19:45:05 +0100, Thomas Ussmueller
ussmueller_wrong_email@gmx.de> wrote:

Hello all,

I have a problem with DIVA LVS and the lxRemoveDevice property. I have
included a parasitic inductor in my schematic. For LVS I want to remove
the device. Therefore I have set the lvsIgnore property to true and the
lxRemoveDevice property to (short(PLUS MINUS)).

The inductor is removed from the netlist, but the nets (net16 and
off_chip1) don't seem to be shorted. Therefore DIVA thinks that these
two nets are seperate nets and that's the reason why the netlists don't
match.

Does anybody know what I can do to fix this error?

Thanks
Thomas

Sounds like you're using Diva LVS in Analog mode. Try only setting the
lxRemoveDevice property. I think the lvsIgnore property is taking
precedence.

Ed, does Diva know about lxRemoveDevice? If it does, perhaps it is only in
recent versions? lxRemoveDevice is for VirtuosoXL, but I didn't know that
Diva had been extended to support that too?

Anyway, the other way to do this is to use the removeDevice() command in your
LVS rules - this is the Diva way of shorting devices.

Regards,

Andrew.
Click to expand...
In Analog Artist mode, several of the Diva operations are over-ridden by
Artist. Netlisting is one of these. There is a separate OSS netlisting
module for analog mode which does various modifications to the LVS
netlist before invoking the Diva LVS binary, then it massages the LVS
output files. The lxRemoveDevice property may, or may not, be understood
by Artist LVS netlisting. I know Diva LVS netlisting does not support
any of those properties, unless OSS itself supports them under the
covers.
 
On Fri, 03 Nov 2006 19:38:56 -0800, Edward Kalenda <diva@cadence.com> wrote:

On Fri, 03 Nov 2006 11:23:22 +0000, Andrew Beckett
andrewb@DcEaLdEeTnEcTe.HcIoSm> wrote:

On Wed, 01 Nov 2006 11:15:39 -0800, Edward Kalenda <diva@cadence.com> wrote:

On Wed, 01 Nov 2006 19:45:05 +0100, Thomas Ussmueller
ussmueller_wrong_email@gmx.de> wrote:

Hello all,

I have a problem with DIVA LVS and the lxRemoveDevice property. I have
included a parasitic inductor in my schematic. For LVS I want to remove
the device. Therefore I have set the lvsIgnore property to true and the
lxRemoveDevice property to (short(PLUS MINUS)).

The inductor is removed from the netlist, but the nets (net16 and
off_chip1) don't seem to be shorted. Therefore DIVA thinks that these
two nets are seperate nets and that's the reason why the netlists don't
match.

Does anybody know what I can do to fix this error?

Thanks
Thomas

Sounds like you're using Diva LVS in Analog mode. Try only setting the
lxRemoveDevice property. I think the lvsIgnore property is taking
precedence.

Ed, does Diva know about lxRemoveDevice? If it does, perhaps it is only in
recent versions? lxRemoveDevice is for VirtuosoXL, but I didn't know that
Diva had been extended to support that too?

Anyway, the other way to do this is to use the removeDevice() command in your
LVS rules - this is the Diva way of shorting devices.

Regards,

Andrew.

In Analog Artist mode, several of the Diva operations are over-ridden by
Artist. Netlisting is one of these. There is a separate OSS netlisting
module for analog mode which does various modifications to the LVS
netlist before invoking the Diva LVS binary, then it massages the LVS
output files. The lxRemoveDevice property may, or may not, be understood
by Artist LVS netlisting. I know Diva LVS netlisting does not support
any of those properties, unless OSS itself supports them under the
covers.
Click to expand...
Hi Ed,

I'm pretty certain the Artist netlisting doesn't support this. The parasitic
filtering stuff there (which predates Diva's removeDevice()) hasn't changed in
years, AFAIK.

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.
 
Forbidding Gated clocks kind of misses the point.

Proper simulation should pick up all race conditions.

When you Gate clocks, you are introducing an interesting situation that
can be very difficult to get right. Clocks, by their nature, typically
need
to have a minimum pulse width. If the gating is not sync'ed to the
clock properly
then you could violate the setup or hold requirements of the FF or
latch.

When you have a non-gated clock, you typically do not need to worry as
much
about the (unexpected ) width of an individual clock pulse width as all
will be close
to the same duty cycle. Once you add gating of clocks, this adds
another dimension
to the already tricky job of ensuring that the DATA to CLOCK setup and
hold times
are not violated.

Any well set up digital simulator can be set up to generate X states
whenever you are
violating the setup or hold requirements of the DATA relative to CLOCK.
You now have to
also ensure that artificially short CLOCK pulses are also properly
verified.

( Often simplistic setup & hold checking could miss narrow clock pulses
as this case
is not always tested )

YMMV

-- Gerry
 
Exactly what kind of ESD functionality do you want?

For example, an analog ESD circuit might have a diode from VDD to the
input, and another diode from the input to GND. Both diodes nominally
will be reverse-biased, and it is actually desirable that your output
voltage is equal to the input voltage (they are actually the same node
in this case). Ideally you don't want the presence of ESD diodes to
impact the performance of the signal during normal operation.



bhargavalluri@gmail.com wrote:
Hi,

I am trying to simulate a simple ESD ciruit( containing 2 diodes) using
cadence spectre, but my circuit is not functioning as expected.
Whatever voltage i give at the input is coming out to the output. Can
anyone tell me what can be the reason for this behavior and how i can
overcome it.

Thanks,
Alluri.
Click to expand...
 
In article <ej8tal$1eb$1@home.itg.ti.com> Suresh Jeevanandam <jm.suresh@/REMOVE/gmail.com> writes:
Edward,
There was a similar discussion on this forum:
http://groups.google.com/group/comp.cad.cadence/browse_frm/thread/66ffbd9ff4da2479?tvc=1

There is a private function hiiGetModifierList(), it returns a list, you
can take car(hiiGetModifierList()) to get the available modifiers.
Click to expand...
Starting in IC 6.1.0 you should use hiBindKeyModifiers(), which is a supported
public function.

Note, though, that starting in IC 6.1.0 Alt is by default dedicated to menu
shortcut access and is not available for "normal" key bindings unless menu
shortcuts are disabled (using the ui.enableMenuShortcuts .cdsenv variable).
Alt will continue to be legal for function keys and mouse buttons, though.

-Pete Z.

--
Suresh

Edward Dodge wrote:
I'm trying to modify my bindkey file so that it tests what kind of
system is loading it. Based on that, I'll write some extra code that
changes the ESC-key to "Meta" if it's on a Sun/Solaris and "Alt"
otherwise. Anyone know of such a function or have a nice, elegant way
to get around this?

Thanks in advacne,

Edward
Click to expand...
 
Let me explain the situation better, I have two diodes as you said, a
diode from vdd to input and another from input to gnd. my vdd is 1.8 v
, and my input voltage swings from 0v to 5v. When my input is at 5v the
diode which is connected to vdd should turn ON and my output should be
1.8 v,but i am getting same 5v at output. I have tried many things like
connecting a resistor at the output and taking output from that
resistor, but nothing seems to work.


linkin wrote:
Exactly what kind of ESD functionality do you want?

For example, an analog ESD circuit might have a diode from VDD to the
input, and another diode from the input to GND. Both diodes nominally
will be reverse-biased, and it is actually desirable that your output
voltage is equal to the input voltage (they are actually the same node
in this case). Ideally you don't want the presence of ESD diodes to
impact the performance of the signal during normal operation.



bhargavalluri@gmail.com wrote:
Hi,

I am trying to simulate a simple ESD ciruit( containing 2 diodes) using
cadence spectre, but my circuit is not functioning as expected.
Whatever voltage i give at the input is coming out to the output. Can
anyone tell me what can be the reason for this behavior and how i can
overcome it.

Thanks,
Alluri.
Click to expand...
 
13 Nov 2006 02:53:05 -0800 axalay <axalay@gmail.com> wrote:
| Why in Allegro PCB Editor I can plase via in pads (in all pads) ? Where
| this tick? I set in design rules via to pin constraint value is 0.15
| mm...
|


look in >setup>constraints>physical>set values>pad/pad direct connect

--
Vic
 
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