cell libraries and place and route

Hi Suresh,

Do you have access to Mentor's Support Site? They have an Application
Note # 0334 that shows you how to integrate Calibre into the Cadence
Design Environment.

Also Appnote #5102 will also explain how to do extraction and
simulation within the Cadence Environment if you are interested.

If not, I would just generate a gds file out of cadence (File -> Export
-> Stream) and then run calibre on the command line.

Tamara
 
Hi Suresh,

I presume you get the ST 90nm design-kit from CMP.
If this is the case, CMP is your support contact.
I have the solution to your problem.

Please use your professional E-mail address for any
support request done to CMP.

Regards,

======================
Kholdoun TORKI
Kholdoun.Torki@imag.fr
http://cmp.imag.fr
======================

suresh wrote:

Hello all

I am working on cadence virtouso for some layout. I am using ST 90nm
technology for this. after the layout I dont have Diva files to check
for the DRC so I am using mentors Calibre for the same.

Now for this i am converting the layout into .gui file and following
steps for the DRC ( Calibre) I always get errors no matter how small
my layout may be, I even tried to check for some already exiting ST
90nm files. to my wonder there are errors in this alos. Now I dont
wheter this is correct method to check for the errors using mentor
calibre for a cadence layout.

so can any one suggest me whther the method i am following for DRC is
correct else if there is some other method for design error check,
please let me know. Ur help will greatly appreciated .


thank u very much in advance

Suresh
Click to expand...
 
hello

Thank you very much for the response. I am afriad to say that we do not
get the design kit frm CPM rather we get it from ST.


Suresh
 
Hello


thanks a lot for the help, I shall try that way . Hope it will work .
BTW I am presently working as Research assis in a university , and can
I know abt u if u do not mind in telling.


best regards

Suresh
 
Hi Suresh,

I sent you an E-mail to the address appearing in your posts :
<singirikonda@gmail.com>
It contains basic settings to run Calibre interactively in Virtuoso.

Hope that this helps.

Regards,

======================
Kholdoun TORKI
Kholdoun.Torki@imag.fr
http://cmp.imag.fr
======================


-------- Original Message --------
Subject: Re: Cadence virtouso layout and Mentor calibre DRC
Date: 17 Feb 2006 02:50:45 -0800
From: suresh <singirikonda@gmail.com>
Organization: http://groups.google.com
Newsgroups: comp.cad.cadence

suresh wrote:
hello

Thank you very much for the response. I am afraid to say that we do not
get the design kit frm CMP rather we get it from ST.


Suresh
Click to expand...
 
On 21 Feb 2006 10:05:29 -0800, samanta.susovon@gmail.com wrote:

Dear all,

I have tried to run a spice netlist in a spectre simulator but it is
unable to read the "table" command in spice netlist. other problems are
also there.

can anybody plzz. help me in this regard

sammy
Click to expand...
Not enough detail. plzz (sic) provide some more. I'm afraid I'm missing the ESP
gene.

Andrew.
 
Below is some code I put together when I needed to convert 100+
schematics. This is just a subpart on how I handled getting the old
properties and then converting to the new ones. I would loop through
each instance on the schematic, based on type (cap, res, fet) I would
execute a sub procedure. The cap one is below. I would take all the
properties I wanted off the old symbol, sub it for the new symbol, and
then reset the properties accordingly. I am still trying to learn
skill and all the built in functions, so there might be a better
solution but perhaps this will help.

Tamara


procedure(TSSConvertCap(cellName inst objId)
; capture existing props
point=inst~>xy
foreach(prop cdfGetInstCDF(inst)~>parameters
propName=prop~>name
case( propName
("c" c=prop~>value)
("m" m=prop~>value)
) ; end case propName
) ; end foreach prop
; change the inst
masterid=dbOpenCellViewByType("techlibName" "newPdkCap" "symbol" ""
"r")
dbSetq(inst masterid master)
; new PDK cannot handle the value. Make a visable label so the
desiger knows
; that the value did not convert over and then they can make necessary
changes
if( (evalstring(c)>951.6e-15) then
schCreateNoteLabel(objId car(point):car(cdr(point)) "Old PDK C
value too high \nsetting to New Pdk Max" "centerCenter" "R0" "stick"
0.0625 "normalLabel")
) ; end if evalstring
geDeselectAllFig(objId)
geSelectFig(inst)
; taking advantage of the CDF callbacks so any other values out of
range
; will show up in the CIW and I can modify code as needed
; though to enable callbacks, values are set to a temp value
; and then to the final value
schHiObjectProperty()
schObjPropForm->calcParam->value = "C"
schObjPropForm->c->value="123f"
schObjPropForm->c->value=c
schObjPropForm->m->value="123"
schObjPropForm->m->value=m
hiFormApply(schObjPropForm)
hiFormCancel(schObjPropForm)
geDeselectFig(inst)
) ; end proc TSSConvertMim
 
Roland.Fontaine@gmail.com wrote:
I am calling a Perl script from within a Skill routine, I am using a
foreach loop to run this Perl scipt on multiple Layout cells, and I can
only run one cell at a time. After I start the foreach loop on the
cellList, how do I pause it until the Perl script completes, before
looping and moving on to the next cell in the list.
Click to expand...
I'd advise you to have a look at ipcWait() ;)

Stéphane
 
S. Badel wrote:

Roland.Fontaine@gmail.com wrote:

I am calling a Perl script from within a Skill routine, I am using a
foreach loop to run this Perl scipt on multiple Layout cells, and I can
only run one cell at a time. After I start the foreach loop on the
cellList, how do I pause it until the Perl script completes, before
looping and moving on to the next cell in the list.


I'd advise you to have a look at ipcWait() ;)

Stéphane
Click to expand...
or even sh()
....
 
Thanks!! Both the functions are very useful :)

Dominic DuVarney wrote:
dbGetMemName() only gives you 1 member of the expanded name so you still
need to go through some type of loop to get the whole expanded name.
dbGetNameNumBit() will give you the length of the expanded name. Im not
sure how long dbProduceMemName has been around but if Andrew says it's
been there for a long time then I quite sure it has. Thanks Andrew.
I've always cheated and used an undocumented function
(nliExpandTerminalName) but this topic forced me to find a documented
one. I'l be updating code to use this now.

Andrew Beckett wrote:

It's been possible to do this forever - I've always used dbGetMemName().
dbProduceMemName seems to have been there since at least 4.4.1 - but I
didn't
read the manual to find out the difference (I'm sure you can do that
;-> )

Andrew.

On Sun, 05 Mar 2006 15:50:53 GMT, Dominic DuVarney
srlayoutdesigner-NOSPAM@yahoo.com> wrote:


dbProduceMemName() will do the trick. This assumes you are using a
newer version.

Rajeswaran M wrote:

Is there any function which can give the list of nets from Bus.

For Eg.,

getAllSubNames("TEST<4:7>,A,B,C<1,2,6>,D<8>")
=> list("TEST<4>" "TEST<5>" "TEST<6>" "TEST<7>" "A" "B" "C<1>"
"C<2>" "C<6>" "D<8>")

Its possible to get it from member instance properties, if we need
to process instance properties. But a generic function is needed as
I need to process user input. A custom skill routine can be written.
But it will be great to use a supported function which would be
robust enough to match how schematic editor will read the bus data.
Click to expand...
 
Hrishikesh, if all your components have a 1 to one mapping in the new
library then a simple skill program is all that is needed. As long as
you know how to calculate the new parameters from the old,you can take
care of that as well in the code. If they don't map simply, then life
is more difficult: if you are lucky then there will only be a couple of
instances of the unusual primitives and you can just modify them by
hand...

David
 
hi Hrishikesh, VCAD (services group within cadence) has an extensive
flow for doing just that. converting designs between pdks. the flow
includes characterizing the two pdks, converting with respect to cell
name changes, symbol size changes, terminal adjustment or renaming, cdf
name, value, type, default changes and callback triggering.

If you'd like to find out more, please contact jens at cadence dot com
or manfred at cadence dot com and ask them about VSCH.

good luck to you in any case.
 
by the way the flow includes conversion from cadence to cadence pdks as
well as mentor to cadence pdks which is quite a bit more difficult but
quite interesting i must admit.
 
So it sounds to me like you need to decide if this is something you
will do often and between very different technologies and vendors or if
this is more of a one time thing where you are just going from say .18
to 90nm in the same foundry so hopefully the complicated stuff like
resizing symbols can be ignored.



David
 
Four Steps
1.Develop SKILL for retrieving source Cell's parameter
2.Develop SKILL for retrieving target Cell's parameter
3.Put source cell's parameter's value to target cell's corresponding
parameter
4.Develop callback trigger

I did the porting for schematic design and layout design base on different
PDK. It's not diffcult job.

Anderson
 
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