1ns max jitter oscillator, cheap - for fast 4 diode sampler

[John Larkin]

On Wed, 8 May 2019 11:27:00 -0400, bitrex <user@example.net> wrote:

On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:

On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en

A patent by Infinenon:

https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

Do any actual chips do this?

We're using the LMX2571 frequency synthesizer chip, which has
phenomenal jitter performance. Like other new-generation synth chips,
it has multiple VCO cores inside, LC oscillators probably. The math is
mind-boggling.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[George Herold]

On Wednesday, May 8, 2019 at 8:10:45 AM UTC-4, Chris Jones wrote:

On 08/05/2019 10:40, bitrex wrote:
On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really can't
beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles.   That means LC beats RC
circuitry (the resistors don't store energy, they just waste it).   A
rock
has the full momentum of the standing wave acoustics, so a crystal is
better
than LC.   Short of maser/resonant cavity  references, the
possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q,
Um do you know what Q is?
intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.
Which ones? I haven't seen it used on a chip.

Do they usually put inductors in ICsThey don't usually put inductors in chips if it is not necessary,
because they are big, which means the chips use more area on the wafer
and cost more money to make. They do use inductors on chips,
begrudgingly, when they want a low phase-noise oscillator, because LC
oscillators have better phase noise than RC oscillators, and because
people will pay enough more money for this good phase noise performance
that it justifies the increased cost of the silicon that is occupied by
the big inductor. I have designed the local oscillator of a cellphone
radio chip, and yes it used an LC oscillator, like all of our
competitors also did.

It is difficult to convince people about things like phase noise,
because most people lack the equipment to measure it easily, and because
LTSpice won't simulate it. You need something a bit more spendy, like
SpectreRF.

Can you see phase noise with a DSO by triggering on the oscillator and then
looking at the signal a long time later. And seeing how stable it is
wrt time.?

George H.

I also find it impossible to convince people that their mixer won't work
better with a low-distortion sine wave LO signal than it would with a
nice sharp square wave LO. Again, hard to simulate the noise performance
properly with anything cheap, and the people who know how to measure it
are not the ones who need convincing.

 

[bitrex]

On 5/8/19 11:54 AM, John Larkin wrote:

On Wed, 8 May 2019 11:27:00 -0400, bitrex <user@example.net> wrote:

On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:

On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en

A patent by Infinenon:

https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.


Do any actual chips do this?

We're using the LMX2571 frequency synthesizer chip, which has
phenomenal jitter performance. Like other new-generation synth chips,
it has multiple VCO cores inside, LC oscillators probably. The math is
mind-boggling.

Definitively? I cannot say for sure it's not like olden times where you
got a schematic with the data-sheet; IC mfgrs don't tell u SHIT without
an NDA not even the CPU core voltages of the new shit like in my post a
few moments ago.

I can only assume that if they patented it there's a decent chance it
will be or is being used for something. Not a guarantee sometimes they
just sit on them but it seems like a lot of work to pay a team for as
just a jerk-off exercise.

 

[Steve Wilson]

John Larkin <jjlarkin@highlandtechnology.com> wrote:

That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?

It's a weird digital PLL. A fast ADC is clocked based on the XO and
digitizes the triggered oscillator waveform. A mess of math in an FPGA
figures out the phase difference, does some PID control stuff, and
drives a DAC and a varicap to trim the LC oscillator. Lots of fun
signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.

Excellent. Thanks

 

[John Larkin]

On Wed, 08 May 2019 19:30:32 GMT, Steve Wilson <no@spam.com> wrote:

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:
Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

Any more information? All I get is Dr. Pepper and pepper spray.

It's referenced in the Wiki article, patent US4968907A. The patent is
hard to read, but basically he built a constant-current, linear analog
ramp delay generator to cover some modest time span, and suspended the
current for some integer number of XO clocks to add time. The async
suspensions add time but don't add clock jitter. Brilliant.

I had an understanding to license the patent, but decided to do the
triggered oscillator thing instead. It's better for long delays.




--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Steve Wilson]

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:

Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

Any more info? All I get is Dr. pepper and pepper spray

 

[Steve Wilson]

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:
Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

Any more information? All I get is Dr. Pepper and pepper spray.

 

[John Larkin]

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:

John Larkin <jjlarkin@highlandtechnology.com> wrote:

That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?

It's a weird digital PLL. A fast ADC is clocked based on the XO and
digitizes the triggered oscillator waveform. A mess of math in an FPGA
figures out the phase difference, does some PID control stuff, and
drives a DAC and a varicap to trim the LC oscillator. Lots of fun
signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.

Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[bitrex]

On 5/8/19 4:10 PM, bitrex wrote:

On 5/8/19 3:46 PM, klaus.kragelund@gmail.com wrote:
On Wednesday, 8 May 2019 17:27:05 UTC+2, bitrex  wrote:
On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:

On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really
can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles.   That means LC
beats RC
circuitry (the resistors don't store energy, they just waste
it).   A rock
has the full momentum of the standing wave acoustics, so a crystal
is better
than LC.   Short of maser/resonant cavity  references, the
possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against
it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en


A patent by Infinenon:

https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf


For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

Well, couldn't you add a PLL to boost the frequency to what is needed
(in my case 144MHz). If the PLL phase noise if good enough that is

Cheers

Klaus


Sounds like rapidly entering the territory of "not cheap." :-( but
higher-performance Wien bridges are a thing and might be interesting to
experiment with

The literature seems to indicate they can't easily hit the phase-noise
performance of LC or crystal, but can beat ring oscillators or RC
relaxation oscillators.

There are finally only so many fundamental oscillator topologies and
variations on a theme; the Wien bridge I think is a gyrator-type where
positive feedback is used to boost a low-Q resonator network into
simulating a high-Q one.

 

On Tuesday, 7 May 2019 22:50:59 UTC+2, John Larkin wrote:

On Tue, 7 May 2019 12:42:22 -0700 (PDT), klaus.kragelund@gmail.com
wrote:

On Tuesday, 7 May 2019 17:18:48 UTC+2, John Larkin wrote:
On Tue, 7 May 2019 07:14:33 -0700 (PDT), klaus.kragelund@gmail.com
wrote:

Hi

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)

So I need a pretty good oscillator, with low jitter

I have never needed a good oscillator before, so on this topic I am totally at square one

First I was thinking about an RC oscillator, and cleaning up the jitter. RC typically have 1us of jitter (found info on the web), and a crystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.

In order to not mess up my measurement and keep the averaging low (I could do many samples and average), I would guess I need jitter of 300ps (10%) of my 3ns reolution)

But jitter is not listed as a search parameter. So where to start? (with low price in mind)

Cheers

Klaus

Do you want a continuous running oscillator, namely a crystal
oscillator? That works if the measured event and the sampler timebase
can run off the same clock. Even cheap XOs have picosecond or
sub-picosecond jitter measured over short time spans. Longer spans are
trashed by low frequency phase noise, numbers in the nanoseconds per
second for cheap XOs, picoseconds per second for good OCXOs.

That is a very good point, great catch.

I will be using it in a TDR, so short pulse, and build up waveform for reflected pulse. Since I need up to 200m lenth, the maximum time from the emitted pulse to reflected is 3us. So if the jitter is slowly changing over time, it may be a lot less in only that time span.


The simplest timebase is a linear RC ramp and a comparator and a DAC,
no clock at all. RMS jitter of 1 part in 20,000 isn't difficult,
1:50000 is challenging. So 3 us/20000 would be 150 ps RMS jitter,
which is probably OK. The echo from 200m of coax will be very soft,
and you can average to reduce displayed jitter. Cheat a little.

In this case I need a fast comparator, sub ns response time. They cost over 2 USD which is a lot more expensive than a picosecond timing PWM microcontroller

Cheers

Klaus

 

On Wednesday, 8 May 2019 22:10:05 UTC+2, bitrex wrote:

On 5/8/19 3:46 PM, klaus.kragelund@gmail.com wrote:
On Wednesday, 8 May 2019 17:27:05 UTC+2, bitrex wrote:
On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:

On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en

A patent by Infinenon:

https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

Well, couldn't you add a PLL to boost the frequency to what is needed (in my case 144MHz). If the PLL phase noise if good enough that is

Cheers

Klaus


Sounds like rapidly entering the territory of "not cheap." :-( but
higher-performance Wien bridges are a thing and might be interesting to
experiment with

The PLL is the one onchip, inside the microcontroller

 

[George Herold]

On Wednesday, May 8, 2019 at 4:00:25 PM UTC-4, klaus.k...@gmail.com wrote:

On Wednesday, 8 May 2019 21:41:59 UTC+2, John Larkin wrote:
On Wed, 08 May 2019 19:30:32 GMT, Steve Wilson <no@spam.com> wrote:

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:
Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

Any more information? All I get is Dr. Pepper and pepper spray.

It's referenced in the Wiki article, patent US4968907A.

I wasn't able to find the Wiki. Searched it for your name, but nothing popped up.

Cheers

Klaus

This maybe,
https://en.wikipedia.org/wiki/Digital_delay_generator

GH

 

[Steve Wilson]

klaus.kragelund@gmail.com wrote:

In this case I need a fast comparator, sub ns response time. They cost
over 2 USD which is a lot more expensive than a picosecond timing PWM
microcontroller

Where do you get one? any model numbers?

Cheers

Klaus

 

[bitrex]

On 5/8/19 3:46 PM, klaus.kragelund@gmail.com wrote:

On Wednesday, 8 May 2019 17:27:05 UTC+2, bitrex wrote:
On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:

On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en

A patent by Infinenon:

https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

Well, couldn't you add a PLL to boost the frequency to what is needed (in my case 144MHz). If the PLL phase noise if good enough that is

Cheers

Klaus

Sounds like rapidly entering the territory of "not cheap." :-( but
higher-performance Wien bridges are a thing and might be interesting to
experiment with

 

On Wednesday, 8 May 2019 21:41:59 UTC+2, John Larkin wrote:

On Wed, 08 May 2019 19:30:32 GMT, Steve Wilson <no@spam.com> wrote:

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:
Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

Any more information? All I get is Dr. Pepper and pepper spray.

It's referenced in the Wiki article, patent US4968907A.

I wasn't able to find the Wiki. Searched it for your name, but nothing popped up.

Cheers

Klaus

 

On Wednesday, 8 May 2019 17:27:05 UTC+2, bitrex wrote:

On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:

On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:

I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]

I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.

The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.

World-class timing uses superconducting cavities, if that matters.


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf

https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en

A patent by Infinenon:

https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

Well, couldn't you add a PLL to boost the frequency to what is needed (in my case 144MHz). If the PLL phase noise if good enough that is

Cheers

Klaus

 

[Gerhard Hoffmann]

Am 08.05.19 um 17:27 schrieb bitrex:

On 5/8/19 11:15 AM, John Larkin wrote:
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:


There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.

Which ICs?


A good number of papers in the literature about design of on-chip low
phase noise Wien bridge clock oscillators:

https://core.ac.uk/download/pdf/34451869.pdf
.....

OK. The only one with hard numbers.

-73.7 dBc/Hz at 10 KHz offset from 5.something MHz carrier.

the cheapest 5 MHz XO I could find at Digikey in about 20 seconds:

-145 dBc / Hz at 10 KHz offset, or about 70 dB better.
This precision part costs 61.5 cents.

<
https://www.digikey.de/product-detail/de/ecs-inc/ECS-3225S33-050-EN-TR/ECS-3225S33-050-EN-TR-ND/6578872
>

< https://www.ecsxtal.com/store/pdf/ECS-3225S.pdf >

And into that 3.2 * 2.5 mm footprint they won't get much of a quality
crystal.

A 5MHz quality crystal would have a Q of > one million.
(or abt 100K @ 100 MHz; Q*f is abt. constant for comparable material.)



And the newfangled figure of merit: 172 dB for the Wien bridge oscillator.

For the current crop of Hittite, AD and TI synthesizers with on-chip
resonator I remember > 230 dB.

Forcing Wien bridges into the context of "accurate sampling clocks"
seems quite far-fetched.

For clocks in the 100s of kHz to several MHz range the topology seems to
have a lot of nice properties, since unless you want to use off-chip Ls
or crystals your options are rather limited.

What offchip Ls or crystals do you need for that 61.5 ct. thing?


regards,
Gerhard

 

On Wednesday, 8 May 2019 22:37:36 UTC+2, Steve Wilson wrote:

klaus.kragelund@gmail.com wrote:

In this case I need a fast comparator, sub ns response time. They cost
over 2 USD which is a lot more expensive than a picosecond timing PWM
microcontroller

Where do you get one? any model numbers?

https://www.st.com/resource/en/datasheet/stm32f334k6.pdf

 

[Steve Wilson]

klaus.kragelund@gmail.com wrote:

On Wednesday, 8 May 2019 22:37:36 UTC+2, Steve Wilson wrote:
klaus.kragelund@gmail.com wrote:

In this case I need a fast comparator, sub ns response time. They cost
over 2 USD which is a lot more expensive than a picosecond timing PWM
microcontroller

Where do you get one? any model numbers?

https://www.st.com/resource/en/datasheet/stm32f334k6.pdf

Thanks. And this thing sells for how much?

Do you have any information on the ultra fast comparators, such as risetime,
offset, delay time? There is nothing in the datasheet.

 

[Clifford Heath]

On 9/5/19 5:30 am, Steve Wilson wrote:

John Larkin <jjlarkin@highland_snip_technology.com> wrote:

On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:
Excellent. Thanks

The Pepper thing, where an analog ramp is suspended for some number of
XO clocks, is magnificent. EG&G used to sell a DDG based on that.
Theirs was a very bad implementation of a great idea, and the
interrupted ramp thing has drift problems for long delays.

Any more information? All I get is Dr. Pepper and pepper spray.

Found it on my second search. Use this in Google (the quotes are important):

"pepper" "digital delay generator"

Clifford heath.