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Here's a cheap semi-linear ramp delay:
https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
Making two ranges would't be hard. Switch the cap or the charging
current.
Here's a cheap semi-linear ramp delay:
https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
On 5/7/19 8:56 PM, Clifford Heath wrote:
On 8/5/19 10:21 am, bitrex wrote:
there's nothing intrinsically high phase noise about the Wien bridge
topology or injection locking. it all depends on the implementation....
Injection of phase adjustments doesn't cause phase noise?
Tell us another joke, please...
Are you hoping for -infinity dBc? No indeed you can't have that sorry
John Larkin <jjlarkin@highlandtechnology.com> wrote:
Here's a cheap semi-linear ramp delay:
https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
Why not use a current source|
On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
It is possible to build an instant-start LC oscillator, and phase-lock
it to a low phase noise XO, and preserve the original trigger timing
with picosecond precision, but I can't tell how.
Like this:
https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0
That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.
On Wed, 08 May 2019 03:28:25 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highlandtechnology.com> wrote:
Here's a cheap semi-linear ramp delay:
https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0
Why not use a current source|
Resistors are cheap and very wideband. Fast precision current sources
are a real pain.
The curvature is small, and a 2nd or 3rd order
polynomial onto the DAC data calibrates things nicely.
On 8/5/19 11:22 am, bitrex wrote:
On 5/7/19 8:56 PM, Clifford Heath wrote:
On 8/5/19 10:21 am, bitrex wrote:
there's nothing intrinsically high phase noise about the Wien bridge
topology or injection locking. it all depends on the implementation....
Injection of phase adjustments doesn't cause phase noise?
Tell us another joke, please...
Are you hoping for -infinity dBc? No indeed you can't have that sorry
Duh. But start with high Q (low phase noise, low resistance->Johnson
noise, LC not RC) and you need smaller kicks to injection lock. Varicap
tuning to reduce the frequency deviation would also allow smaller
injections - you could still use a phase detector to PLL the tuning.
On Wed, 08 May 2019 02:30:11 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
It is possible to build an instant-start LC oscillator, and
phase-lock it to a low phase noise XO, and preserve the original
trigger timing with picosecond precision, but I can't tell how.
"preserve the original trigger timing" <- compared to what?
Like this:
https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0
That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.
So you count cycles until you reach the desired time, then start a fast
ramp to set the vernier delay. How you measure the vernier delay time?
In our products, we compute a polynomial at factory cal time to
linearize the dac codes going into the ramp comparator. The poly terms
go into a cal table. That's why we can use an RC instead of a current
source.
We use a Keysight time interval counter to cal the ramps.
It takes a bit of care to avoid "stitching errors", little hickies
every time we add one digital count and jump the ramp back down.
On 5/7/19 11:00 PM, Clifford Heath wrote:
On 8/5/19 11:22 am, bitrex wrote:
On 5/7/19 8:56 PM, Clifford Heath wrote:
On 8/5/19 10:21 am, bitrex wrote:
there's nothing intrinsically high phase noise about the Wien
bridge topology or injection locking. it all depends on the
implementation....
Injection of phase adjustments doesn't cause phase noise?
Tell us another joke, please...
Are you hoping for -infinity dBc? No indeed you can't have that sorry
Duh. But start with high Q (low phase noise, low resistance->Johnson
noise, LC not RC) and you need smaller kicks to injection lock.
Varicap tuning to reduce the frequency deviation would also allow
smaller injections - you could still use a phase detector to PLL the
tuning.
I don't get where this idea come from that the Wien bridge topology is
intrinsically low Q. Is it because the open-loop RC network is?
The amplifier in the circuit is not just a power buffer to overcome loss
like e.g. a Colpitts oscillator or phase-shift oscillator. Look at which
terminal the frequency-selective network is connected to, y'all.
On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]
I know I'll appear a dinosaur by saying this, but you really can't
beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.
The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles.  That means LC beats RC
circuitry (the resistors don't store energy, they just waste it).  A
rock
has the full momentum of the standing wave acoustics, so a crystal is
better
than LC.  Short of maser/resonant cavity references, the
possibilities are good
for plain old wires as delay lines (distributed L, C) also.
World-class timing uses superconducting cavities, if that matters.
There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q,
Um do you know what Q is?
intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.
Which ones? I haven't seen it used on a chip.
John Larkin <jjlarkin@highlandtechnology.com> wrote:
On Wed, 08 May 2019 02:30:11 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
It is possible to build an instant-start LC oscillator, and
phase-lock it to a low phase noise XO, and preserve the original
trigger timing with picosecond precision, but I can't tell how.
"preserve the original trigger timing" <- compared to what?
Like this:
https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0
That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.
So you count cycles until you reach the desired time, then start a fast
ramp to set the vernier delay. How you measure the vernier delay time?
In our products, we compute a polynomial at factory cal time to
linearize the dac codes going into the ramp comparator. The poly terms
go into a cal table. That's why we can use an RC instead of a current
source.
We use a Keysight time interval counter to cal the ramps.
It takes a bit of care to avoid "stitching errors", little hickies
every time we add one digital count and jump the ramp back down.
That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?
Right, Q is a measure of energy storage. How much energy leaks outOn 5/7/19 11:00 PM, Clifford Heath wrote:
On 8/5/19 11:22 am, bitrex wrote:
On 5/7/19 8:56 PM, Clifford Heath wrote:
On 8/5/19 10:21 am, bitrex wrote:
there's nothing intrinsically high phase noise about the Wien bridge
topology or injection locking. it all depends on the implementation....
Injection of phase adjustments doesn't cause phase noise?
Tell us another joke, please...
Are you hoping for -infinity dBc? No indeed you can't have that sorry
Duh. But start with high Q (low phase noise, low resistance->Johnson
noise, LC not RC) and you need smaller kicks to injection lock. Varicap
tuning to reduce the frequency deviation would also allow smaller
injections - you could still use a phase detector to PLL the tuning.
I don't get where this idea come from that the Wien bridge topology is
intrinsically low Q. Is it because the open-loop RC network is?
The amplifier in the circuit is not just a power buffer to overcome loss
like e.g. a Colpitts oscillator or phase-shift oscillator. Look at which
terminal the frequency-selective network is connected to, y'all.
On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]
I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.
The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.
World-class timing uses superconducting cavities, if that matters.
There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q,
intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact. Do they usually put inductors in ICs?
Am 07.05.19 um 21:37 schrieb bitrex:
On 5/7/19 1:20 PM, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
Hi
I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.
In a rare moment of partial agreement with my arch-nemesis "Cursitor
Doom" an injecton-locked Wien bridge oscillator can provide a
near-perfect combination of very low phase noise and very low wideband
noise floor and distortion. And certainly meets the low-price requirement.
Alone the fact that you can easily injection lock a Wien bridge
oscillator is a sure sign that its frequency stability is not
of prime quality. And the absence of harmonics has nothing to do
with phase noise, as long as their amplitude is not that large
that it causes high order sideband mixdown to baseband. (noise present
around harmonics). You can have a square wave with excellent phase
noise.
Injection locking also does not solve any problem. If your injection
source is so good, why not use it directly, without all of this ado?
And if you look at the Leeson equation that defines the phase noise
of an oscillator, there is a division term of (2 * Q**2), so Q is one
of the most important parameters. In practical oscillators that can be
even stronger than **2, depending on offset. The Leeson formula is
somewhat simplified. Rohde, Rubiola and others have improved on that.
Remember that the phase slope of the loop gain is effective Q.
dphase/dfreq of a Wien bridge is, oh, ask LTspice. The wet sand bag.
Good is different. Oscillation frequency is where phase goes through 0,
so Q = dphase / dfreq at this frequency is that what counts.
Jitter is phase noise integrated over all frequencies of interest.
That works in the other direction, too, but there are more degrees
of freedom, i.e the noise distribution close to / far from the carrier.
And for telecom applications, the frequencies of interest do not
include anything below 12 KHz. That's how most stuff is specc'ed
because it gives better numbers. 1/f noise is ugly.
You probably cannot afford that luxury of neglecting 1/f because you
need absolute flight time, but if your laser link has GHz subcarriers,
then that's OK.
There is a German web site with a calculator: phase noise -- jitter
but here it's well after midnight, so I won't search it now.
Maybe tomorrow.
As I wrote more than once here: timenuts group at febo.com,
and www.rubiola.org
The HP 54750A scope contains a time stretcher (dual slope: charge fast,
discharge slowly). It has been described in HP Journal.
It is even 2-stage to get more traces per second.
I must admit that I love that scope. And everybody should have the
HP journals in their vault.
This dual slope procedure is not uncommon. I have done something similar
to compare a hydrogen maser and a cesium. 5 ps resolution with
somewhat worse accuracy have been reached at many places. That's
about what a Stanford 620 time interval counter delivers. Good instrument.
cheers, Gerhard
...and its a Wien bridge, not Wein. Also, it's not Seimens.
The creator of the bridge was Wien by name; he has his name
probably from the the town called Vienna abroad. Also the sausages are
not Weiners but Wieners, even if from Oscar Mayer; but methinks in
Vienna they call them Frankfurter.
I wished I was an Oscar Meyer Weiner, because if I was an Oscar Meyer
weiner, everybody would love me.
John Larkin <jjlarkin@highlandtechnology.com> wrote:
On Wed, 08 May 2019 02:30:11 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote:
John Larkin <jjlarkin@highland_snip_technology.com> wrote:
It is possible to build an instant-start LC oscillator, and
phase-lock it to a low phase noise XO, and preserve the original
trigger timing with picosecond precision, but I can't tell how.
"preserve the original trigger timing" <- compared to what?
Like this:
https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0
That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.
So you count cycles until you reach the desired time, then start a fast
ramp to set the vernier delay. How you measure the vernier delay time?
In our products, we compute a polynomial at factory cal time to
linearize the dac codes going into the ramp comparator. The poly terms
go into a cal table. That's why we can use an RC instead of a current
source.
We use a Keysight time interval counter to cal the ramps.
It takes a bit of care to avoid "stitching errors", little hickies
every time we add one digital count and jump the ramp back down.
That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?
That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.
So you count cycles until you reach the desired time, then start a fast
ramp to set the vernier delay. How you measure the vernier delay time?
In our products, we compute a polynomial at factory cal time to
linearize the dac codes going into the ramp comparator. The poly terms
go into a cal table. That's why we can use an RC instead of a current
source.
We use a Keysight time interval counter to cal the ramps.
It takes a bit of care to avoid "stitching errors", little hickies
every time we add one digital count and jump the ramp back down.
That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?
On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote:
On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]
I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.
The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.
World-class timing uses superconducting cavities, if that matters.
There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.
Which ICs?
On 08/05/2019 10:40, bitrex wrote:
On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]
I know I'll appear a dinosaur by saying this, but you really can't
beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.
The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles.  That means LC beats RC
circuitry (the resistors don't store energy, they just waste it).  A
rock
has the full momentum of the standing wave acoustics, so a crystal is
better
than LC.  Short of maser/resonant cavity references, the
possibilities are good
for plain old wires as delay lines (distributed L, C) also.
World-class timing uses superconducting cavities, if that matters.
There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q,
Um do you know what Q is?
 > intrinsically
high phase noise, or any of these scurrilous accusations against it!
And the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.
Which ones? I haven't seen it used on a chip.
Do they usually put inductors in ICsThey don't usually put inductors
in chips if it is not necessary,
because they are big, which means the chips use more area on the wafer
and cost more money to make. They do use inductors on chips,
begrudgingly, when they want a low phase-noise oscillator, because LC
oscillators have better phase noise than RC oscillators, and because
people will pay enough more money for this good phase noise performance
that it justifies the increased cost of the silicon that is occupied by
the big inductor. I have designed the local oscillator of a cellphone
radio chip, and yes it used an LC oscillator, like all of our
competitors also did.
It is difficult to convince people about things like phase noise,
because most people lack the equipment to measure it easily, and because
LTSpice won't simulate it. You need something a bit more spendy, like
SpectreRF.
I also find it impossible to convince people that their mixer won't work
better with a low-distortion sine wave LO signal than it would with a
nice sharp square wave LO. Again, hard to simulate the noise performance
properly with anything cheap, and the people who know how to measure it
are not the ones who need convincing.
On 5/7/19 5:16 PM, whit3rd wrote:
On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote:
On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote:
I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible)
[and want a low-jitter oscillator]
I know I'll appear a dinosaur by saying this, but you really can't beat a
good old fashioned Wien Bridge oscillator when it comes to spectral
purity and low phase noise. They certainly beat the crap out of any
digital synthesis technique IMV.
The best timing performance requires significant stored energy,
if only for Heisenberg uncertainty principles. That means LC beats RC
circuitry (the resistors don't store energy, they just waste it). A rock
has the full momentum of the standing wave acoustics, so a crystal is better
than LC. Short of maser/resonant cavity references, the possibilities are good
for plain old wires as delay lines (distributed L, C) also.
World-class timing uses superconducting cavities, if that matters.
There's nothing intrinsic about the poor, besmirched Wien bridge
oscillator topology that makes it intrinsically low Q, intrinsically
high phase noise, or any of these scurrilous accusations against it! And
the topology is already used in ICs to generate accurate sampling
clocks, as a matter-of-fact.
Steve Wilson <no@spam.com> wrote:
That oscillator starts instantly when an external trigger comes in,
but it's phase locked to a crystal oscillator. The XO is at some
random phase at trigger time. Injection locking would walk the
triggered oscillator into phase with the XO, which we don't want.
So you count cycles until you reach the desired time, then start a fast
ramp to set the vernier delay. How you measure the vernier delay time?
In our products, we compute a polynomial at factory cal time to
linearize the dac codes going into the ramp comparator. The poly terms
go into a cal table. That's why we can use an RC instead of a current
source.
We use a Keysight time interval counter to cal the ramps.
It takes a bit of care to avoid "stitching errors", little hickies
every time we add one digital count and jump the ramp back down.
That's not what I meant. When you start the LC oscillator, there is a
random phase between the trigger and the XO. How do you measure that?
That question is probably going to come too close to the area you don't
want to talk about. How about a different approach.
Instead of trying to lock a pll to an oscillator at random phase, we could
measure to time between an asychronous trigger and an XO clock:
1. start a fast ramp at the trigger
2. find the delay to the second clock pulse from the XO
3. store this in a sample/hold or adc
4. count to the target delay minus 1 clock
5. start a fast ramp to the same delay time as the original
You now have the target delay locked to the XO but shifted in time
6. add the desired vernier delay to fill in between clock periods
There is the nasty problem of the trigger hitting exactly on a clock
transition, but that will occur with any asynchronous system.
I am now
examining patents from Tektronix, LeCroy, HP/Agilent/Keysight to find out
how they handle the problem.