J
Jim Thompson
Guest
On 26 Mar 2005 09:38:32 -0800, Winfield Hill
<hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote:
nasty data ;-)
Back in the infancy of simulators I DID roll my own(*) BJT models from
lab data.
(*) With the assistance of oldest son, who was already studying
programming at U of A.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
<hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote:
I'm game. I just love this kind of puzzle... fit a nasty model toJim Thompson wrote...
Jim Thompson wrote:
[snip]
I was looking thru "pwrmos.lib" in the new OrCAD/PSpice release...
everything is STILL Level=3.
So I think the problem is the manufacturers don't care about
spending money on quality modeling.
It's literally been just shy of 20 years since I designed anything
with a power-FET, and _most_ of my I/C foundry CMOS models do seem to
work subthreshold (for small-signal analog).
Win, WHAT is important to you in power-FET modeling, subthreshold?
Maybe we can mutually determine the "fix" for the models?
OK, here's what I wrote early in the discussion, last December 31st,
Well, then surely you'll want viable Spice MOSFET models, because
you'll be using the FETs throughout their useful linear range, and
the output-stage crossover region is critical.
Sadly most standard Spice library VMOS models simply don't do the
subthreshold linear region. For example, see the 10-decade plots
on page 123 of our book. A jellybean 2n7000 is rather similar to
the VN01 that we show in figure 3.14, and certainly a proper Spice
model should be able to make that plot. But I'd be surprised if
your standard Spice libraries work properly below say 5 to 20mA,
which is not that far below the FET's maximum current. Keep in
mind that linear power FET circuitry always operates well below
the maximum rated FET switching current, to keep power dissipation
junction heating under control.
I since confirmed this with some 2n7000 Spice-model testing...
the SQRT-Id plot goes to zero at 2.4V (wrong answer), an abrupt
transition occurs at 9mA (wrong), and another at 2mA (gross), to
a 5-decade subthreshold exponential transconductance (correct) at
Vgs = 2.4V (wrong). Rather useless for linear-circuit modeling.
The bottom line is you'll have to start your FET-amplifier design
exercise by designing some decent FET models. Let us know what you
come up with.
With respect to the Id-vs-Vgs curves on page 123 of our book, and
the g_m plots on page 132, the spice models should be able to show
this performance. At subthreshold currents a FET acts very much
like a transistor with respect to transconductance, etc., and when
a power FET is used in linear audio amplifiers, e.g. in class AB,
it may go through this region during each cycle. So in using Spice
to determine distortion and evaluate various design configurations,
surely it's necessary for the FET model to smoothly simulate the
subthreshold region, and properly progress to the current-saturated
regions that are normally accurately modeled. I'm going to go in
to the lab and take some detailed 2n7000 measurements later today.
nasty data ;-)
Back in the infancy of simulators I DID roll my own(*) BJT models from
lab data.
(*) With the assistance of oldest son, who was already studying
programming at U of A.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.