need a cheap student edition FPGA

"Eric K." <usgog@yahoo.com> wrote in message
news:80d6ba74.0409292157.5edd2bbb@posting.google.com...
I am developing a program in Java to generate a boolean function by
using k-map with 4 variables. So from the 4-variable map with 16
cells, user can input 1 or 0 in each cell. Then the program will
generate the simplied boolean function according to the map.

Basically I don't know the algorithm on how to group the "1"s and then
how to simplify it. Please advise. Or let me know if you have/know any
such code that I can learn from.
Click to expand...
Have you checked out the Quine-McCluskey tabulation method? It is very
suitable for programming.
JD
 
In article <35824643.0409281311.5d0fa28a@posting.google.com>,
turbo18t <mkracer3@yahoo.com> wrote:
I need a small FPGA to use in a lab at school. It doesn't have to be
fast, have millions of gates or in any way be a high performance
model. It just has to work.
Click to expand...
You want a Charmed Labs xPort board and a second-hand Gameboy Advance,
I think. The Gameboy is a 20MHz ARM, about the equivalent of a 386 PC
-- you write things for it in C and use a cross-compiler hosted on a
Windows PC.

It has about 60 I/Os, brought out on a connector very like the one used
for floppy drives. Cost $140 plus a second-hand GBA.

Tom
 
Hi, I'm also having some problems implementing a simple testbench for the
easics generator. Anyone have any sort of test code? Thanks
 
"turbo18t" <mkracer3@yahoo.com> skrev i meddelandet
news:35824643.0409281311.5d0fa28a@posting.google.com...
I need a small FPGA to use in a lab at school. It doesn't have to be
fast, have millions of gates or in any way be a high performance
model. It just has to work. In the class we're designing relatively
small ALU's and I want to do it in Verilog and burn it. It has to be
a protoboard with I/O's and a PC interface. My friend suggested the
Xilinx Spartan series. Any help is appreciated. Thanks.
Click to expand...


The STK500 + STK594 FPSLIC will give you a cool tool since it also contains
an onchip AVR
The toolset will allow you to test the FPGA using the AVR.
It is much nicer to write testvectors in C, than in VHDL.
Also the display of simulation results is much nicer using AVR studio, than
the average waveform window.



--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.
 
"John_H" <johnhandwork@mail.com> writes:

The one thing in favor of keeping the `includes out of the design is
that the technique is prone to errors for archiving and moving the
full set of files. I often grep my synthesis project file to make
sure I copy over all the necessary files. I must always, however,
Click to expand...

I would suggest using CVS or a simular source code control system
rather than copying the files around.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
"Jal" <jalibahmed@hotmail.com> wrote in message
news:d8e046e.0410050036.3fbae8ee@posting.google.com...
Hi,

Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.
Click to expand...
[snip]

I don't have the experience with simvision, but I had a call in to the
Cadence folks about my 2-D wire troubles.

The array of nets construct

wire [7:0] MyWords [3:0];

is not supported in LDV51 or the current IUS53 release. The IUS54 release
due out sometime in November will provide the full support.

IUS53 - the first release after LDV51 - fixed my problems with conditional
generates and multi-dimensional part select (MyWords[1][1:0]) though bit
select (MyWords[1][2]) reportedly worked in LDV51.
 
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:873c0tog6j.fsf@parish.home.gustad.com...
"John_H" <johnhandwork@mail.com> writes:

The one thing in favor of keeping the `includes out of the design is
that the technique is prone to errors for archiving and moving the
full set of files. I often grep my synthesis project file to make
sure I copy over all the necessary files. I must always, however,


I would suggest using CVS or a simular source code control system
rather than copying the files around.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Click to expand...
A: Because my mail reader and composer are oriented for threaded
conversations and start at the top of each post; scrolling each post to the
bottom of a thread I already know is often not worth the effort when the
topic has become uninteresting.
Q: Why is bottom posting unnatural?

But then what happens when I have a file that's no longer in the project?

If I split the development off from the current track (a chip in a shipping
product) to start a new product, I can check out a fresh set of files but
I'd need to reimplement the version control in the new location anyway.
Perhaps there are nicer ways of keeping parallel developments going but this
is a one-designer chip.
 
"John_H" <johnhandwork@mail.com> writes:

But then what happens when I have a file that's no longer in the
project?
Click to expand...
You mean you want to delete it? In CVS you can do cvs remove.


If I split the development off from the current track (a chip in a
shipping product) to start a new product, I can check out a fresh
set of files but I'd need to reimplement the version control in the
new location anyway. Perhaps there are nicer ways of keeping
parallel developments going but this is a one-designer chip.
Click to expand...
If it's a shipping product you can use cvs tag to mark the versions of
all the files used to sign off the chip. You can then continue the
development, possibly bumping the verion numbers of all the files to
2.0 or similar.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
"John_H" <johnhandwork@mail.com> writes:

Maybe saying "Bad Engineer!" in a commanding voice will wear them
down after a while.
Click to expand...
Try this:

http://www.gustad.com/pics/badesign.gif

:)

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
Bassman59a@yahoo.com (Andy Peters) writes:

And yes, the parameters should be overriden in a script/via command
line, rather than `include-ing a "header" that overrides the
`defines. It's horrific! I know all this -- it's convincing others
of the errors of their ways.
Click to expand...
Sounds very frustrating. I think they might have to experience the
problem to understand it. It's a pain to clean up such a mess
afterwords. I found this message written by myself some time ago, most
likely after been through such a process:

http://tinyurl.com/4yyxm

Petter


--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
"Petter Gustad" <newsmailcomp5@gustad.com> wrote in message
news:m3llekguqn.fsf@scimul.dolphinics.no...
"John_H" <johnhandwork@mail.com> writes:

Maybe saying "Bad Engineer!" in a commanding voice will wear them
down after a while.

Try this:

http://www.gustad.com/pics/badesign.gif
Click to expand...
LOLOL !!
- Thanks.
 
"John_H" <johnhandwork@mail.com> wrote in message
news:Czd9d.20$Be6.2519@news-west.eli.net...
[snip]
If, on the other hand, you don't want to bother with the memory at all you
could figure out the digits through logic and do the binary to BCD and BCD
to 7-segment conversions in the chip. The binary-to-BCD is a bit tough
because it involves division through the three stages to get your digits.
[snip]
Click to expand...

I integrated the conversion into a divider-like structure. Getting the BCD
bits out directly is a few stages of add/subtract cascaded together.
Apologies to those who don't like to see lots of code. The file looks best
in fixed space font.

The "top" module is a quick testbench to show that everything works. The
resources and delays are a little excessive for the 8-bit binary to bcd
conversion but the result can be combinatorial. No clock required.

If there are questions about the code, feel free to ask but please don't
repost the whole code to be kind to others.

Thanks,
- John_H

module SevenSeg ( bin
, Seg7_2, Seg7_1, Seg7_0
);
input [7:0] bin;
output [6:0] Seg7_2;
output [6:0] Seg7_1;
output [6:0] Seg7_0;

wire [8:0] res200;
wire [7:0] res100;
wire [6:0] res80;
wire [5:0] res40;
wire [4:0] res20;
wire [3:0] res10;
wire [1:0] bcd2;
wire [3:0] bcd1;
wire [3:0] bcd0;
assign {bcd2[1],res200} = 9'd199 - bin; // 1 offset makes sign work
assign {bcd2[0],res100} = res200 + (bcd2[1] ? 9'd100 : 9'd100-9'd200);
assign {bcd1[3],res80 } = res100 + (bcd2[0] ? 8'd80 : 8'd80 -8'd100);
assign {bcd1[2],res40 } = res80 + (bcd1[3] ? 7'd40 : 7'd40 -7'd80 );
assign {bcd1[1],res20 } = res40 + (bcd1[2] ? 6'd20 : 6'd20 -6'd40 );
assign {bcd1[0],res10 } = res20 + (bcd1[1] ? 5'd10 : 5'd10 -5'd20 );
assign bcd0 = (bcd1[0] ? -4'd1 : 4'd9) - res10;
assign Seg7_2 = hex_to_7( bcd2 );
assign Seg7_1 = hex_to_7( bcd1 );
assign Seg7_0 = hex_to_7( bcd0 );

function [6:0] hex_to_7;
input [3:0] digit;
case(digit) // common anode: {t,rt,rb,b,lb,lt,m}
4'h0: hex_to_7 = 7'b0000001; // ---t---
4'h1: hex_to_7 = 7'b1001111; // | |
4'h2: hex_to_7 = 7'b0010010; // lt rt
4'h3: hex_to_7 = 7'b0000110; // | |
4'h4: hex_to_7 = 7'b1001100; // ---m---
4'h5: hex_to_7 = 7'b0100100; // | |
4'h6: hex_to_7 = 7'b0100000; // lb rb
4'h7: hex_to_7 = 7'b0001111; // | |
4'h8: hex_to_7 = 7'b0000000; // ---b---
4'h9: hex_to_7 = 7'b0001100;
4'hA: hex_to_7 = 7'b0001000;
4'hb: hex_to_7 = 7'b1100000;
4'hC: hex_to_7 = 7'b0110001;
4'hd: hex_to_7 = 7'b1000010;
4'hE: hex_to_7 = 7'b0110000;
4'hF: hex_to_7 = 7'b0111000;
endcase
endfunction

endmodule


module top();

integer i;
wire [6:0] Seg7_2, Seg7_1, Seg7_0;

initial
for( i=0; i<256; i=i+1 )
begin
#1 $display( " %c %c %c", Seg7_2[6] ? " " : "_"
, Seg7_1[6] ? " " : "_"
, Seg7_0[6] ? " " : "_"
);
$display( "%3d %c%c%c%c%c%c%c%c%c", i
, Seg7_2[1]? " ":"|", Seg7_2[0]? " ":"_", Seg7_2[5]? " ":"|"
, Seg7_1[1]? " ":"|", Seg7_1[0]? " ":"_", Seg7_1[5]? " ":"|"
, Seg7_0[1]? " ":"|", Seg7_0[0]? " ":"_", Seg7_0[5]? " ":"|"
);
$display( " %c%c%c%c%c%c%c%c%c"
, Seg7_2[2]? " ":"|", Seg7_2[3]? " ":"_", Seg7_2[4]? " ":"|"
, Seg7_1[2]? " ":"|", Seg7_1[3]? " ":"_", Seg7_1[4]? " ":"|"
, Seg7_0[2]? " ":"|", Seg7_0[3]? " ":"_", Seg7_0[4]? " ":"|"
);
end

SevenSeg Disp ( .bin(i)
, .Seg7_2(Seg7_2)
, .Seg7_1(Seg7_1)
, .Seg7_0(Seg7_0)
);

endmodule
 
weizbox wrote:

I was wondering if there is a way to easily change a bin number to a
bcd without a lookup table or anyhting else like that if the numbers
do not need to convert.
Click to expand...
For small numbers of digits, the amount of logic is
pretty small. It can easily be done in combinatorial
logic.

The work toward a decimal based floating point standard
uses 10 bits to store three digits. It is supposed to take
only a small amount of logic to convert between that and BCD.

Write out the Karnaugh maps and see how much logic it takes.

(There are also logic minimization programs around to do it.)

-- glen
 
"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410071256.2e0aafd8@posting.google.com...
Hello,

I was wondering if there is a way to easily change a bin number to a
bcd without a lookup table or anyhting else like that if the numbers
do not need to convert.

Example: I have a decimal value of 1234 in a 12-bit binary reg. I
would like to transfer those values to a 16-bit bcd. No conversions
needed, I still want 1234, just in bcd. Is there an easy way to do
this?

-Mark
Click to expand...
How about this for 4 digits: (some of the LSbits can be truncated - I just
haven't done an error analysis or testbench)
wire [22:0] res3;
wire [21:0] res2;
wire [20:0] res1;
wire [19:0] res2;
wore [3:0] bcd3, bcd2, bcd1, bcd0;
assign {bcd3,res3} = bin[12:0] * 14'h20c5; // 5 adds, 4 adders in a tree
assign {bcd2,res2} = res3 * 3'h5;
assign {bcd1,res1} = res2 * 3'h5;
assign {bcd0,res0} = res1 * 3'h5;

The idea here is use a fixed/flaoting-point hybrid. The first thing you'd
like is to "effectively" divide by 1000 which - though close at 131/131072
(131/2^17) provides better results at 8389/8388608 (8389/2^23). The first
BCD digit is the multiplied result shifted 23 bits. The fractional part is
effectively multiplied by 10 ("fractional" multiplied by 5 and shifted 1)
to get the next digit 22 bits out.

The implementation looks better in code and can be manipulated further for a
smaller implementation with the appropriate error analysis.

The idea is the same in software: find the first digit by dividing by 1000
(or 10000, whatever) then get successive digits from 10x the fractional
part.
 
Varun,
I have tried doing this in the past, while trying to write a strong
obfuscator for verilog.
I have a project on http://sourceforge.net/projects/hdlobf/ open source.
I plan to add
this in terms of obfuscation but you could probably extract this feature
from the parser.

Regards,
Vispi

"Varun Jindal" <varunjindal@yahoo.com> wrote in message
news:a132b4b3.0409140117.2e3a0824@posting.google.com...
hello,
i am looking for a tool, which can flatten my verilog design,

i dont require the various heiarchies in the design and want to
flatten it into single top module design.


is anybody aware of such options in any available tool !?

thanks in advance,
regards
Varun.
Click to expand...
 
In article <LOi9d.24$Be6.2620@news-west.eli.net>,
John_H <johnhandwork@mail.com> wrote:

How about this for 4 digits: (some of the LSbits can be truncated - I just
haven't done an error analysis or testbench)
wire [22:0] res3;
wire [21:0] res2;
wire [20:0] res1;
wire [19:0] res2;
wore [3:0] bcd3, bcd2, bcd1, bcd0;
assign {bcd3,res3} = bin[12:0] * 14'h20c5; // 5 adds, 4 adders in a tree
assign {bcd2,res2} = res3 * 3'h5;
assign {bcd1,res1} = res2 * 3'h5;
assign {bcd0,res0} = res1 * 3'h5;
Click to expand...
That's lovely, makes me realise I ought to study _Hacker's Delight_
(by Henry S Warren, for those unfortunates who haven't read it yet)
more. Its tricks no longer seem quite so relevant on CPUs with
two-cycle 64x64->128 multipliers, but they're going to be really handy
on FPGA.

Tom
 
In article <7b43bbda.0410072148.70f683d1@posting.google.com>,
S.Muralidharan <smuralidharan@gmail.com> wrote:
Hi all,

I am doing my M.Tech Degree in VLSI Design.
I have taken the task of implementing the REED SOLOMON DECODER in FPGA
as my project.
Click to expand...
Mr Muralidharan,

I'm wondering why you have chosen this project for a higher degree
when you seem slightly unsure as to what an RS decoder is *for*.

The descriptions for Reed-Solomon codes are in all the standard books
on coding theory, though I admit it's usually quite hard to find really
clear specifications for the decoder; the Berlekamp-Massey algorithm
is presented and you're supposed to take it from there.

Unless there's a particular application that excites you, I would
build a program that took the base field and the generator polynomial,
and outputted Verilog source code for a decoder over that field with
that generator -- the most general case. And then see if you can
find interesting optimisations for particular generator polynomials
used in particular applications.

Tom
 
"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410071256.2e0aafd8@posting.google.com...
Hello,

I was wondering if there is a way to easily change a bin number to a
bcd without a lookup table or anyhting else like that if the numbers
do not need to convert.

Example: I have a decimal value of 1234 in a 12-bit binary reg. I
would like to transfer those values to a 16-bit bcd. No conversions
needed, I still want 1234, just in bcd. Is there an easy way to do
this?

-Mark
Click to expand...
I just did a quick google - always nice to do *first* - and found
http://www.opencores.org/projects.cgi/web/binary_to_bcd/overview

Check it out for your needs. (it took me a moment to find the "Downloads"
in the top right corner).
 
Anthony Liu wrote:
Hi,

I'm trying to build Icarus Verilog 0.7 on a BSD machine and have
following problem when it is linking. Can someone give me a tip
on how to link it successfully? Thanks in advance! Any help is
appreciated.
Click to expand...
Try instead the latest snapshot. That is in fact a release candidate
for 0.8, which I may release this week.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
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