EDK : FSL macros defined by Xilinx are wrong

[Dave Garnett]

<aosik5@gmail.com> wrote in message
news:1112127765.083272.105280@z14g2000cwz.googlegroups.com...

hello, I'm about to layout a circuit for a pcb that includes the Xilinx
spartan II-e and external circuitry (simple interface elements), I was
wondering if anyone has laid out a PCB using the chip, because I know
there are a lot of capacitors and resistors and other elements that are
on the development board, and I am not sure what needs to be transfered
and what doesn't..

George

Firstly, re read your question. How do you expect a sensible answer with the
minute amount of detail you provide !

Anyway, it is better to understand what is going on than copy blindly. Lets
play 'twenty questions'.

Do you know what a ground plane is ?

Do you understand what is meant by decoupling - what are all those
capacitors and resistors for anyway ?

How many layers will your pcb have ?

What is your clock speed ?

How will your chosen clock speed affect your layout ?

Have you simulated your design - do you know whether it will meet your
timing constraints with the pinout you are about to commit to ?

What are you interfacing to - how long and what type of interconnects are
used ?

There are lots of articles and Application Notes on topics like these - read
and enjoy !

Dave




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[John_H]

I'm a Verilog guy and your question is for VHDL - it would be great if a
VHDL guy gould give the proper code snippets. The question is addressed in
general:

"genlock" <genlocks@gmail.com> wrote in message
news:1112131201.352597.22410@g14g2000cwa.googlegroups.com...

Yes the decimal number is a constant value.

For the example of division by 1.36, multiplying by (2^24/1.36) and taking
the 24 MSbits of the result, you get an "effective" division. If you
generate the "reciprical integer multiplier" from real literals and do a
type conversion to std_logic_vector, the multiply would follow as a simple
multiply. Then just shift or select the upper bits and you have your
result.

What do you mean by embedded multipliers?

The modern FPGAs tend to have multipliers as part of the logic fabric.
You're using ISE so my expectation is you're using a
Virtex(-E)Virtex-II(Pro), Virtex-4, Spartan-II(E), or Spartan-3/3L/3E.
These should all have multipliers if memory serves me right. Check the data
sheets.

Is there a VHDL code available for that or how do we go about coding
one.

I'd like to see someone on this newsgroup provide you a snippet to do
(roughly) what I suggest. If you wanted Verilog, it'd be something like
result[23:0] <= In[23:0] * ((1<<24)/1.36 + 0.5) >> 24;

but I haven't used real variables in my code much if at all. I think this
would synthesize.

I dont need a clock for this one.

Thankyou

 

[ann]

Hi, Thanks for the schematic. So do you have application notes on how to interface with this sram? Is there a module in your FPGA design that interface with this sram? Thanks, Ann

 

[Piotr Wyderski]

andpaoli wrote:

I'm new to math function on FPGA, but I need to calculate exp(-x) with
a Spartan3 in fixed point 16bit numbers. How can i do that?

Depends on what is the range of parameters. Your statement
"fixed point 16bit numbers" doesn't help much, because it doesn't
specify any particular encoding -- is it 8 bits for the integral part
and 8 bits for fractions or only 16 bits of fraction, which describe
a number in the range of (-1,1) or something else?

What's the best way?

As I said, it depends.

Best regards
Piotr Wyderski

 

[Christos]

Hi Piotr,

"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message
news:d24gh5$27f$1@news.dialog.net.pl...

Hello,

how do I extend buses in Quartus Schematic Editor?
Say, for instance, there is an input "phase_offset[23..0]"
and a component which expects a 32-bit wide vector.
I would like to map phase_offset to the upper 24 bits
of the vector and hardwire the remaining bits to 0.

Maybe this is not the best way.. but it works!!

Draw a bus line and give it a name, for example "a[7..0]". then connect this
bus to a GND.
Now on the input of the component which expects the 32bit vector you can
have a bus line named "phase_offset[23..0],a[7..0]"

Hope it works for you too, let me know if I wasn't clear enough.

Christos dot Zamantzas at CERN dot ch

 

[skherich]

I see two potential problems with what you are trying to do.
1. As mentioned before you can only drive one IBUF/IBUFG from a Pad.
2. Outputs of two DCMs from same reference clock can have a phase
offset. I am not
sure of your application but something that you need to be aware of if
you
are using Virtex2 devices.

samir
design wrote:

Hi everyone,
I am using a demo board from Memec whose clock source is given to one
of the input PINS of the FPGA.
I have to generate two clocks of different frequency from this input
clock source. I am using two DCM's for these.
When i give the input clock to both the DCMs there is an error during
implementing the design which says one input clock cannot drive two
DCM's or something like that.
So i tried giving the output of one of the DCM's to the input of
another DCM.
Even then it gives an error during the implementation stage. Both the
error cases are mentioned below.

This problem has been addressed before in this group without any
possible solution. But it has been a long time. So i was thinking
anyone has come up with an idea. I have also opened a webcase with
Xilinx.
The first case is when the input clock is given as an input to both
the
DCM's
The second case is when the output clock of the DCM is given as an
input to the second DCM.

case1
ERROR:LIT - IPAD symbol "clkin" is driving more than one loads. IPAD
can only drive a single IBUF or two IBUFDS.
If you are using a BUF instead of an IBUF, it may have been
simplified, please use an explicit IBUF instead.
Errors found during logical drc.

case2

ERROR:NgdBuild:455 - logical net 'CLK0_OUT' has multiple drivers. The
possible
drivers causing this are:
pin O on block dcm_33_CLK0_BUFG_INST with type BUFG,
pin PAD on block CLK0_OUT with type PAD
ERROR:NgdBuild:466 - input pad net 'CLK0_OUT' has illegal connection.
Possible
pins causing this are:
pin O on block dcm_33_CLK0_BUFG_INST with type BUFG
Thanks and regards

 

[Jim Wu]

There are two ways to synthesize a memory in an FPGA. One is to use
verilog's reg as you suggested, the other one is to use Vendor
Specific
Primitive. Using verilog's reg is the most portable one. It works
with
all FPGAs with little or no modification. But it takes valuable
space
in your FPGA logic that otherwise can be used for other purposes.

Most of the synthesis tools are able to infer dedicated RAM blocks.

With XST, how do I know that my code is synthesized to a RAM made from
the logic, or RAM made from the dedicated RAM blocks?

The synthesis report will tell you if the tool inferred RAM.

Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

[Jim Wu]

I may be able to help you if you can send me the pinout (ucf). (use my
private email below)

Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

<wpiman@aol.com> wrote in message
news:1112110943.504959.158890@o13g2000cwo.googlegroups.com...

Chipscope will be something we use after we verify clocks/reset and
what not. Right now I just want to print up a big sheet so the techs
can do some simple probing. I played with pace but didn't get anywhere.

 

[Matthias Alles]

Brad Smallridge schrieb:

Good to see another EAGLE user.

What are you doing with this board, may I ask?

I just wanted to gain experience in PCB designing with it. If you want
to know more detailed what I did with this board so far have a look at
http://www-user.rhrk.uni-kl.de/~alles/fpga/

Matthias

 

[Matthias Alles]

ann schrieb:

Hi, Thanks for the schematic. So do you have application notes on how to interface with this sram? Is there a module in your FPGA design that interface with this sram? Thanks, Ann

I don't have any application notes about it. When you use the EDK of
Xilinx you can use the generic SRAM core. But it's not very difficult to
write an own SRAM controller, you only need the data sheet of the SRAM..

Matthias

 

[pipjockey]

WP,
Oleda tech has the tool that you are looking for. www.oledatech.com

Our online tools will read your PAD output or UCF file and generate a
HTML based graphical representation of your footprint. Pins with
signal assignments are highlighted, plus you can point to a pin and see
the signal assignment.

It also lets you highlight groups of pins such as busses or pins with a
common IO standard, or all the signals that begin with PCI, etc. You
can save a 'live' copy on your computer or print out views of your
choosing.

You can contact me through the website, I'd be glad to set you up with
a trial license. It will save you a great deal of time!

John

 

[Philip Freidin]

On 30 Mar 2005 06:29:36 -0800, "lecroy7200@chek.com" <lecroy7200@chek.com> wrote:

Well, I have read all of your posts, and everyone elses too.
The problem is one of clarity of communications.

Good that you know that everyone read them all. I for sure could not
make that statement.

Well, this is still a clarity issue. I wrote "elses" but should have
probably written "else's", as in "I have read the articles by everybody
else".

You read "elses" and assumed I meant "else has" which is a contraction
I have never heard of

Philip
Philip Freidin
Fliptronics

 

[Ray Andraka]

andpaoli wrote:

I'm new to math function on FPGA, but I need to calculate exp(-x) with
a Spartan3 in fixed point 16bit numbers. How can i do that? What's the
best way? Can someone help
me?[size=24:ae1f1145a8][/size:ae1f1145a8]



I've posted on this subject before (search google using andraka and

exp) here is one such posting that is probably the closest to what you
want:
http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/47feb1a180f72f78/3cfe528ea11418b3?q=andraka+exp&rnum=5#3cfe528ea11418b3






--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Marc Randolph]

skherich wrote:

I see two potential problems with what you are trying to do.
1. As mentioned before you can only drive one IBUF/IBUFG from a Pad.
2. Outputs of two DCMs from same reference clock can have a phase
offset. I am not sure of your application but something that you need

to be aware of if you are using Virtex2 devices.

The V2Pro spec's a max of +/-140 ps (so I guess that's really 280 ps)
of phase offset between DCM's, which I wouldn't think would be a
problem for most designs running at reasonable clock rates. Although
it isn't stated, I believe this phase spec only applies when using
CLK0, CLK180, CLK90, CLK270, CLK2X, and CLK2X180. The phase of the
divided outputs (CLKDV OR CLKFX) can not be controlled.

Have fun,

Marc

 

[design]

Thanks for all the replies. I did finally manage to fix it. All i
needed to do was select the clock source as internal for one of the
DCM. Although i understood the part where I needed to use an explicit
IBUF or IBUFG i am not sure on how to do it. I tried instantiating the
IBUF or IBUFG module and using the output to drive the DCM's.

Regards

 

[Sam]

design wrote:

Thanks for all the replies. I did finally manage to fix it. All i
needed to do was select the clock source as internal for one of the
DCM. Although i understood the part where I needed to use an
explicit
IBUF or IBUFG i am not sure on how to do it. I tried instantiating
the
IBUF or IBUFG module and using the output to drive the DCM's.

Regards

It's pretty simple to instantiate the IBUFG's explicitly. The code
below drives two DCM's from a single IBUFG. You will have to include
the unisim.vcomponents package for ISE to recognise the DCM and IBUFG
primitives, but if you're using DCM's you've probably figured this out
already.

Sam

IBUFG1 : IBUFG
port map (O=>clk_ibufg,I=>pad_clkin);

DCM1 : DCM
port map(
CLKIN=>clk_ibufg,CLKFB=>internal_clk1,
DSSEN=>'0',PSINCDEC=>'0',PSEN=>'0',PSCLK=>'0',
RST=>'0',CLK0=>internal_clk1_bufg,
CLK90=>open,CLK180=>open,CLK270=>open,
CLK2X=>open,CLK2X180=>open,CLKDV=>open,
CLKFX=>open,CLKFX180=>open,
LOCKED=>open,PSDONE=>open,
STATUS=>open);

BUFG1 : BUFG
port map (O=>internal_clk1, I=>internal_clk1_bufg);

DCM2 : DCM
port map(
CLKIN=>clk_ibufg,CLKFB=>internal_clk2,
DSSEN=>'0',PSINCDEC=>'0',PSEN=>'0',PSCLK=>'0',
RST=>'0',CLK0=>internal_clk2_bufg,
CLK90=>open,CLK180=>open,CLK270=>open,
CLK2X=>open,CLK2X180=>open,CLKDV=>open,
CLKFX=>open,CLKFX180=>open,
LOCKED=>open,PSDONE=>open,
STATUS=>open);

BUFG2 : BUFG
port map (O=>internal_clk2, I=>internal_clk2_bufg);

 

[digi]

Hallo

I have solve this problem with instation of IBUFs and OBUFs and
connect them to the inputs and outputs of component.

But on the outputs of components i get still an Error in the EDK but
not in the ISE!

ERROR:NgdBuild:455 - logical net
'myasimon/myasimon/USER_LOGIC_I/dataout<0>' has
multiple drivers. The possible drivers causing this are:
pin dataout<0> on block
myasimon/myasimon/USER_LOGIC_I/Inst_test with type
test,
pin PAD on block myasimon/myasimon/USER_LOGIC_I/dataout<0>
with type PAD

Can any help there?

 

[lecroy7200@chek.com]

Thanks for the post Brian.

Proper internal oscillator startup would normally be guaranteed
by the monotonic VCC rise requirements for the part in question;
oscillator failure would be consistent the earlier speculation of
a hypothetical transient of some sort taking out the FPGA.

Based on this I tried several tests yesterday using different power
supply ramp rates. I went into the seconds. Watching the oscillator
with the spectrum analyzer I can see it sweep as it begins to start and
finally locks to the normal frequency. I tried manually adjusting the
supply by watching the oscillator to see if I could trick it that way
into not starting. From this I never saw any of the internal
oscillators fail to start after a day of tests.

It's almost like there was some undocumented test mode that the part
gets into. I doubt it has anything like this, but from all my tests
the part seems very robust.

An interesting thing I did note was that when the device is powered
down, the oscillators continue to run. Who would have guessed. They
must not wanted to deal with the time to lock. The data sheet talks
about the 3100A drawing 5mA in power down.

BTW, on a failed part, have you observed DOUT for activity under
the test conditions described in Philip's earlier posts?

No

Also, what value pullup/pulldown resistors are you using for the
mode and powerdown pins? I have another vague recollection that
that the internal pullups were "stiffer" in later 3xxx series parts,
and needed lower values for the external resistors.

M2 uses a 1K. M0,M1 and power down are tied directly to VCC.

At the risk of sounding repetitive, the method you seek is
called "master serial mode", which lets you directly observe
CCLK ( or a divided down version thereof ).

Yes, this requires changing another variable in your test setup,
which might affect your chances of observing something.

Agree, and don't think I had not thought of this. The specturm analyzer
and near field probe work fine. Not sure why Xilinx did not agree with
the technique.

However, it provides the benefit that you would now have a
signal that can be directly probed, and used to catch whatever
transient event is perturbing the FPGA: e.g., trigger a deep
memory scope on "loss of CCLK" while probing any likely suspects
(VCC, configuration pins, VEE, translator output pins, etc.) at
a high sample rate with plenty of pretrigger storage.

This is a very good idea. Had I been able to replicate the problem,
using this as a positive trigger would have been a good idea.

 

[Kolja Sulimma]

Ray Andraka wrote:

andpaoli wrote:

I'm new to math function on FPGA, but I need to calculate exp(-x) with
a Spartan3 in fixed point 16bit numbers. How can i do that? What's the
best way? Can someone help
me?[size=24:ae1f1145a8][/size:ae1f1145a8]



I've posted on this subject before (search google using andraka and
exp) here is one such posting that is probably the closest to what you
want:
http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/47feb1a180f72f78/3cfe528ea11418b3?q=andraka+exp&rnum=5#3cfe528ea11418b3

Most likely that's the way to do it. An alternative would be a
hyperbolic CORDIC, also explained by Ray:
http://www.andraka.com/files/crdcsrvy.pdf

Kolja Sulimma

 

[genlock]

What do u mean by an explicit number and how did you arrive at this
value?