EDK : FSL macros defined by Xilinx are wrong

[Tim Wescott]

On Mon, 16 Jun 2014 11:59:26 -0700, azimalimoll wrote:

On Saturday, February 18, 1995 9:26:05 AM UTC+5:30,
u801...@cc.nctu.edu.tw wrote:
Hello,

I would like to know something diffrent among them? I was always
cunfused by them all.

In my previous impression, they are:

PAL: programmable AND, fixed OR PLD: programmable AND, programmable OR
PLA: ???????????? AND, ???????????? OR GAL=PLD ??

Please correct the above, Thanks in advance!

Jason

Why are we bothering with a 20 year old revived thread?

This reminds me of an old 'B' horror movie that starts with a guy pulling
a stake out of the chest of a skeleton in a circus exhibit, and becoming
the vampire's first victim in a century.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[rickman]

On 6/18/2014 9:52 AM, colin wrote:

On Wednesday, June 18, 2014 8:55:58 AM UTC+1, Tom Gardner wrote:
On 18/06/14 00:34, rickman wrote:

So if you want to design a logic device into your system, don't worry with terms and abbreviations. Just decide what features you need and select a part that works for you.



That's sensible.



A rule of thumb when /starting/ to select a device is:

- CPLD: smaller, fewer flip flops, lower maxim clock

speed, but more predictable timing that doesn't

change much as when you vary the implemented function.

Toolsets might be significantly simpler.

- FPGA: larger, more flip flops and other functions,

higher maximum internal clock speed (but similar

external clock speed), but timing that can vary

significantly with apparently trivial changes to the

VHDL/Verilog.



but /completing/ selection of a device requires a detailed

understanding of its capabilities w.r.t. your application.



For beginners, I'd suggest starting with a CPLD unless

they require an FPGA's capabilities.

Also note that a CPLD tends to need one supply whilst an FPGA tends to need at least three.

That entirely depends on the FPGA. There are plenty of FPGAs with only
one power supply voltage.

--

Rick

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:

That entirely depends on the FPGA. There are plenty of FPGAs
with only one power supply voltage.

Well, many have separate I/O power pins, and you might be able to
run that at the same voltage as the core, but often the core voltage
is close to 1.0, and that is low for many I/O pins.

-- glen

 

[Brian Drummond]

On Tue, 24 Jun 2014 15:48:25 -0700, Thorsten Kiefer wrote:

Hi,
before downloading ISE webpack, I wanted to ask, if there is a free VHDL
simulator, which is easy to compile or stable ?

FreeHDL crashes on my machine, and ghdl -> I don't know how to compile.

ghdl : on most platforms you don't have to compile it, there are pre-
built packages of ghdl-0.31 available, see http://sourceforge.net/
projects/ghdl-updates/

If your OS isn't covered; what do you need?

If you meant you don't know how to compile your VHDL code...
http://sourceforge.net/p/ghdl-updates/wiki/Using%20ghdl/
and see the ghdl manual linked there.

- Brian

 

[Brian Drummond]

On Wed, 25 Jun 2014 22:08:34 -0700, Thorsten Kiefer wrote:

Am Mittwoch, 25. Juni 2014 22:50:55 UTC+2 schrieb mnentwig:
Hi,



BTW I use Lubuntu, and Lubuntu does not include ghdl.
I meant : I don't know how to compile ghdl.

Upstream of Lubuntu, there are problems or ambiguities licensing the IEEE
libraries under terms acceptable to Debian. Until these are resolved
somehow, official packages of ghdl are problematic.

But you shouldn't need to compile ghdl : the .deb packages at [1] ought
to install OK. If they don't, I'd be interested to know why not.

[1]
http://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.31/
Debian/

- Brian

 

[Brane2]

Dne sobota, 05. julij 2014 08:24:29 UTC je oseba MK napisala:

There's a "Request ECP5 support" form under ECP5 section on the website.



http://ww3.latticesemi.com/ECP5DiamondLicenseRequest.html

Great ! Thanks, you were faster than their support )

Looks to me as if they are just going to give you an add on but keeping

tabs on who gets it (while the ECP5 is still virtual ?

Hehe- good one. ECP5- "Breaking The Rules" - meet first VFPGA - Virtual FPGA.

First, you buy ECP3 as physical machine and then install ECP5 on top of it ;o)

Honestly, this licensing stuff is annoying.

I would understand it if I wanted some advenced sh** full of IP blocks etcetc.

But they are charging serious $$$ for utility that basically configures merchandise they plan to sell. It's kind of utility equipment.

Not to mention that for stuff I do, and at those densities, I'd be quite happy with lower level stuff.

If someone gave me something like PCB editor for FPGA, where I could access and set basic structures and manipulate them as one would elements on PCB, I'd probably toss verilog in a second.

 

[MK]

On 04/07/2014 17:23, rickman wrote:

On 7/4/2014 7:06 AM, Brane2 wrote:
BTW, I've got an anser that ECP is not covered by my current 1yr
subscription license file and that the'll check if I am entitled to
upgrade.

Bummer. First they silently deleted whole XO3-H part of the series and
now they want $$$ for a licence for ECP5 that is in absence of XO3-H
my next choice.

And there are no visible discounts this time- full price is EURO$1k. ;o/

I'm confused. I thought that was the point of the paid license, you get
the capability of supporting their full range of parts. If not, why
bother paying for a license? Just what are you buying over the free
edition of the tools?

There's a "Request ECP5 support" form under ECP5 section on the website.

http://ww3.latticesemi.com/ECP5DiamondLicenseRequest.html

Looks to me as if they are just going to give you an add on but keeping
tabs on who gets it (while the ECP5 is still virtual ?

Michael Kellett

 

[MK]

On 05/07/2014 12:28, Brane2 wrote:

I'd probably toss verilog in a second.

That's your problem - switch to VHDL and everything will be rosy !

For what it's worth I use Aldec HDL (paid for $$$ but worth it) and only
use the Lattice tools for some IP modules and synthesis. You get the
Aldec tool (cut down but still quite good) in with the Lattice toolset.

The stuff I do got way too big to want to think about gates a long while
ago - latest project uses some 96 and some 128 bit arithmetic - I
wouldn't fancy placing the flip-flops for that by hand !

Michael Kellett

 

[rickman]

On 7/5/2014 7:48 AM, MK wrote:

On 05/07/2014 12:28, Brane2 wrote:
I'd probably toss verilog in a second.


That's your problem - switch to VHDL and everything will be rosy !

For what it's worth I use Aldec HDL (paid for $$$ but worth it) and only
use the Lattice tools for some IP modules and synthesis. You get the
Aldec tool (cut down but still quite good) in with the Lattice toolset.

The stuff I do got way too big to want to think about gates a long while
ago - latest project uses some 96 and some 128 bit arithmetic - I
wouldn't fancy placing the flip-flops for that by hand !

I remember when the HDLs were still not mainstream with the FPGA users
and the FPGA vendors were pushing to get everyone converted. One of the
expert users Ray Andraka had a full set of schematic modules which he
could use hierarchically with place and route constraints which gave him
tons of control over the actual design, much like what Brane is asking
for. So Ray was a serious hold out for schematics.

Then the FPGA folks showed him how to apply the same constraints to VHDL
with the same hierarchy (I'm sure it works the same with Verilog) as
well as the advantages of text files for development and archival... he
was sold! I believe he never looked back.

Who am I to argue with Ray Andraka?

--

Rick

 

[Brane2]

Dne sobota, 05. julij 2014 18:24:20 UTC je oseba rickman napisala:

One of the

expert users Ray Andraka had a full set of schematic modules which he

could use hierarchically with place and route constraints which gave him

tons of control over the actual design, much like what Brane is asking

for. So Ray was a serious hold out for schematics.

1. AFAIK he was working for XIlinx. His focus might have been more toward high end of application spectrum.

2. I'm not arguing for schematics but for something much closer to pcb part..

Substantial difference is that PCB substrat by itself is homegenous- non patterned. So you need several step approach, first you choose elements and then wire them symbolically and in second step you map those symbols to "meat" ( element housings etc), place them and shape copper between them

With FPGA, you don't have those degrees of freedom. Everything is already pre patterned and placed on LEGO landscape and all you need to do is flip the right subset of switches on.

If i could click on PFU and enter simple equation and system would configure FLASH for its ROM table, that'd be great. Same with output flip-flop, gates etc tidbits. Seeing actual wires could also help with autorouting. I could plan in advance which wires to use for what etc.

Once I would complete say 4-bit counter, I could make a group, which could move around as a whole. Simple SW logic might take care of tidbits. Like if I move group somewhere that violates some wiring demands, that it would simply erase those wires and show me fresh ratsnest etc.

HDL for me is just another layer of obfuscation that fogs things and demands whole new learning curve etc.

After all, our brain evolved so that we have visual "accelerators", not relational ones. If visual data is presented right, brain can filter interesting patterns and edges out ouf vast array of pixels and details.

 

[KJ]

On Sunday, July 6, 2014 10:55:13 AM UTC-4, Brane2 wrote:

If i could click on PFU and enter simple equation and system would configure
FLASH for its ROM table, that'd be great. Same with output flip-flop, gates
etc tidbits. Seeing actual wires could also help with autorouting. I could
plan in advance which wires to use for what etc.

'Simple' is the keyword in all of that. You would only be able to create 'simple' designs, nothing complex, nothing that could be easily maintained. Good luck being productive, others will pass you right by. You would take forever to create a design...or be let go before you complete it.

Once I would complete say 4-bit counter, I could make a group, which could
move around as a whole. Simple SW logic might take care of tidbits. Like if I
move group somewhere that violates some wiring demands, that it would simply
erase those wires and show me fresh ratsnest etc.

But there is not much call for 4-bit counters. Move them around all you like and let us know if you can create a video coder/decoder or some other functionality that has usefulness. Even your statement "Once I would complete say 4-bit counter", shows the lack of being productive. Most anyone skilled in HDL would probably have trouble even quantifying the amount of time required to 'complete a 4-bit counter' it would be so small.

HDL for me is just another layer of obfuscation that fogs things and demands
whole new learning curve etc.

Maybe you should work your up way up the learning curve and see if that fogs clears up. For most, that is what happens.

Kevin Jennings

 

[Richard Damon]

On 7/6/14, 10:55 AM, Brane2 wrote:

Dne sobota, 05. julij 2014 18:24:20 UTC je oseba rickman napisala:
One of the

expert users Ray Andraka had a full set of schematic modules which
he

could use hierarchically with place and route constraints which
gave him

tons of control over the actual design, much like what Brane is
asking

for. So Ray was a serious hold out for schematics.


1. AFAIK he was working for XIlinx. His focus might have been more
toward high end of application spectrum.

2. I'm not arguing for schematics but for something much closer to
pcb part.

Substantial difference is that PCB substrat by itself is homegenous-
non patterned. So you need several step approach, first you choose
elements and then wire them symbolically and in second step you map
those symbols to "meat" ( element housings etc), place them and shape
copper between them

With FPGA, you don't have those degrees of freedom. Everything is
already pre patterned and placed on LEGO landscape and all you need
to do is flip the right subset of switches on.

If i could click on PFU and enter simple equation and system would
configure FLASH for its ROM table, that'd be great. Same with output
flip-flop, gates etc tidbits. Seeing actual wires could also help
with autorouting. I could plan in advance which wires to use for what
etc.

Once I would complete say 4-bit counter, I could make a group, which
could move around as a whole. Simple SW logic might take care of
tidbits. Like if I move group somewhere that violates some wiring
demands, that it would simply erase those wires and show me fresh
ratsnest etc.

HDL for me is just another layer of obfuscation that fogs things and
demands whole new learning curve etc.

After all, our brain evolved so that we have visual "accelerators",
not relational ones. If visual data is presented right, brain can
filter interesting patterns and edges out ouf vast array of pixels
and details.

I HAVE used tools like that, for parts much smaller than we have today.
One of the first PLD configuration tools I used had a mode which brought
up the full fuse map so you could configure your 16 FF PLD letting you
choose from the logic modes of the logic block and configure the routing
matrix for the and/or/xor input block. It was much preferable to enter
in the equations and let the compiler figure all this out. Looking at
the map might help if you were getting "too complex" errors to let you
see what was the problem. And by letting you try to do it yourself you
could actually convince yourself it was too complicated, or let you
figure out how to express it directly so the compiler could work it out
(This normally due to tweaking "don't care" conditions).

Later, when we had real FPGA's, the tools would have a mode where you
could see each of the individual LE as a little box that you could
assign your logic elements as defined by equations or schematic, and see
the "rats nest" of connections, and an indication of how stressed the
routing matrix was in that area. A printout of this sort of layout could
take a good part of a wall for a whole chip.

Sometimes, for a small complicated circuit, you could sit down and
pre-fit pieces to help the fitter. More often often you could help some
by assigning chunks of the design to regions of the device. The one spot
where this ability really helped was if you had to place pins to start
the board layout before you finished the FPGA design. You could enter
basic designs for the things driving the outputs and see what were
natural placements for them and what pins they could directly drive.

I am much happier not to need to get down to that level most of the
time. Being able to see things at the HDL level give a much better
understanding of the over all function. It would be somewhat like
deciding to work on a large software package by throwing out the
compiler and saying it obfuscates what really happens, you REALLY need
to design that system at low level assembly.

This doesn't say that in some special cases there won't be a need to dig
in and look at the raw results generated to solve a performance issues,
but that is the exception, and normally for just a small piece of the
system.

Note, that even though they are HDLs, there normally IS a way to force
low level effects, this signal WILL be the output of a logic element,
this signal WILL use the carry change, to allow you to define things
exactly as you want the compiler to generate the logic.

 

[Tim]

Interesting. Have they cancelled the XO3-H?

On 04/07/2014 12:06, Brane2 wrote:
<snip>

Bummer. First they silently deleted whole XO3-H part of the series
and now they want $$$ for a licence for ECP5 that is in absence of
XO3-H my next choice.

 

[rickman]

On 7/6/2014 10:55 AM, Brane2 wrote:

Dne sobota, 05. julij 2014 18:24:20 UTC je oseba rickman napisala:
One of the

expert users Ray Andraka had a full set of schematic modules which he

could use hierarchically with place and route constraints which gave him

tons of control over the actual design, much like what Brane is asking

for. So Ray was a serious hold out for schematics.


1. AFAIK he was working for XIlinx. His focus might have been more toward high end of application spectrum.

I believe Ray used Xilinx parts almost exclusively but he did not work
*for* Xilinx. I'm not sure he even worked at the "high end" per se. He
did utilize the parts to their maximum capabilities, both in speed and
density. He did a lot of work in the days when what you want would have
been practical in the way you picture it.

2. I'm not arguing for schematics but for something much closer to pcb part..

Substantial difference is that PCB substrat by itself is homegenous- non patterned. So you need several step approach, first you choose elements and then wire them symbolically and in second step you map those symbols to "meat" ( element housings etc), place them and shape copper between them

With FPGA, you don't have those degrees of freedom. Everything is already pre patterned and placed on LEGO landscape and all you need to do is flip the right subset of switches on.

If i could click on PFU and enter simple equation and system would configure FLASH for its ROM table, that'd be great. Same with output flip-flop, gates etc tidbits. Seeing actual wires could also help with autorouting. I could plan in advance which wires to use for what etc.

What you are talking about would be direct instantiation of hard
features in the FPGAs. I believe you can instantiate PFUs and then
assign logic to them from the HDL. It may not be portable across
vendors, but that's no surprise.

Once I would complete say 4-bit counter, I could make a group, which could move around as a whole. Simple SW logic might take care of tidbits. Like if I move group somewhere that violates some wiring demands, that it would simply erase those wires and show me fresh ratsnest etc.

HDL for me is just another layer of obfuscation that fogs things and demands whole new learning curve etc.

After all, our brain evolved so that we have visual "accelerators", not relational ones. If visual data is presented right, brain can filter interesting patterns and edges out ouf vast array of pixels and details.

Yes, we are more visual, but when using text based design entry we can
get the computer to do things for us more easily and some functions like
version control work better.

If you are willing to use an HDL you can do what you are talking about.
It is the graphical interface that is not going to happen.

--

Rick

 

[Brane2]

Dne nedelja, 06. julij 2014 20:56:01 UTC je oseba Tim napisala:

Interesting. Have they cancelled the XO3-H?

Look at their website. After all fanfares, they revealed XO3 that was functionally on paper nothing like what was promised.

Then, they hastily added in the XO3 family introduction that this is only low end of the family and that high end XO3H is yet to come.

And now that sentence has dissapeared. If you click on XO3 family intro on latticesemi.com, there is nothing about XO3H.
Crap.

 

[Brane2]

Dne nedelja, 06. julij 2014 19:03:56 UTC je oseba KJ napisala:

But there is not much call for 4-bit counters. Move them around all you like and let us know if you can create a video coder/decoder or some other functionality that has usefulness.

You are comparing apples to helicopters. I used 4-bit counter just as an simple example. Just as you can use symbollics to describe more complex structures in HDL, there is nothing preventing that in graphically oriented approach.



> Even your statement "Once I would complete say 4-bit counter", shows the >lack of being productive. Most anyone skilled in HDL would probably have >trouble even quantifying the amount of time required to 'complete a 4-bit >counter' it would be so small.

Really ? Examples around me say exactle the opposite. FPGA is relatively expensive. It's not a peanut like some ARM. And it carries quite a few additional considerations.

At least in my price and volume ranges, chip utilisation counts. My extra work less so.

And quite frequently I can find people trying to see through the "fog" and to aqueeze extra performance. Then all those symbolic levels start working against the designer.

But this is theme for another dilemme.

I'v got renewed license. It supports a couple of ECP5-U and ECP5-UM, probably those models that they have in productions already.

If anyone is inteerseted in details, as of this moment, I can select:

LFE5U, LFE5UM and LAE5UM in 25F,45F and 85F densities.

 

Honey Sue Elovitz..................my in class instructor in 1970 at University of Maryland Fortran V class!!!!!

 

[pini_kr]

Hi all,

I need to generate a part of my VHDL project as a VHDL gate level IP, in
the goal to protect my generic IP core.

In fact, I want to protect my own PCI core before delivering the complet
VHDL project.

My question:
Is this possible to do a VHDL gate level Netlist from XST.
Then to remap it in my VHDL project.
Then to do a concatenated VHDL file of by project .
Then do a new synthesis and P&R with webpack from my concatenate VHD
file.

If yes, how is the best way ?

Regards,
Larry
www.amontec.com

Yes,
I did it an IP stack (TCP/IP) free project:
"The following describes the synthesis of the VHDL IP stack, using xilin
XST.

The synthesis is done with the free xilinx tool: Release 10.1.03
xst.

The package was installed on a debian linux distribution running on
co-linux system..."


---------------------------------------
Posted through http://www.FPGARelated.com

 

[pini_kr]

Hi folks,

I'm getting tired of commenting large blocks of VHDL code by hand.

Anyone know of any Vim scripts that can comment/un-comment a VHDL
block?

A cursory Google search brings up either nothing or way too much stuff
to sift through depending on my search terms ("vhdl vim comment").

-- Pete

With VIM one can easily invoke a script from within vim on entire tex
%!perl my_scr.pl or :'a,'b!perl ...). In my site give many useful script
and how to use them.
http://bknpk.ddns.net/my_web/VIM/vim_title_bar_set.html

You find this interesting: "Run a perl script from vim on a block of text
to enumerate constants for a state machine...
http://bknpk.ddns.net/my_web/VIM/vim_enumerate_fsm_constants.html

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Guy Eschemann]

TÜV Rheinland has a workshop on functional safety for FPGAs: http://www.tuvasi.com/de/trainings-und-workshops/workshops/programmierbare-elektronik-asics-fpgas-cplds-in-der-sicherheitstechnik

Regards,
Guy Eschemann
guy@noasic.com