EDK : FSL macros defined by Xilinx are wrong

On 22/11/13 19:33, Jan Panteltje wrote:
Well you state 120 ns, I dunno,
but I can flip 10M Hz that makes 50 nS on 50 nS off on the Raspi,
without any FPGA, using GPIO.
Click to expand...

Small point: you're comparing frequency and conductance :)

More interesting question, assuming you were actually
talking about times, what's the typical and guaranteed
tolerance on those times?
 
Hi,

I agree, there isn't much papers and links on this subject.

I recently came across this:
http://www.clifford.at/yosys/files/yosys-austrochip2013.pdf

You can also search for relevant Xilinx/Altera/Tabula patents in Google Patents.

Thanks,
Evgeni
 
On 17/01/14 22:06, Jan Panteltje wrote:
On a sunny day (Fri, 17 Jan 2014 13:50:46 -0800) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
559jd9pie6ngd8l1ch1gp47von4771prtl@4ax.com>:

Rather than being cautious, I just plugged 24 volts into it, and the
Zed lit up and ran Linux.

What does 'Z' do that a Raspbery Pi cannot?

Integrate two 600 MHz ARM cores and a screaming-fast FPGA onto one
chip. And the Zed has Ethernet, flash, DRAM, USB, power supplies, all
that stuff done and tested. It's a great way to do gear that will be
built in fairly small quantities.

Well rapsi has that, but only one core.


This app will do a lot of signal processing in the FPGA at 48 M
samples/second.


http://www.bugblat.com/products/pif/
So all together with tools about 75 $; raspi + FPGA board.

2 rapsis ... makes...
3 rapsis makes...

any combination thereof.

But rapsi also has HD HDMI out, and audio out, etc...

That HDMI out is cool, as you can plug it into almost any modern monitor
and make nice user friendly presentations.
Something that is not so simple or needs extra hardware on other platforms.
My rapsi even plays HD movies...
Just imagine, when it starts up you can make it play the Highland background with cows grazing.
with greener grass...
Click to expand...

If my understanding is correct, the RPi's GPIO is particularly
weedy and slow. OTOH, the Zync has a high performance FPGA
tightly integrated with the CPU and memory. Hence if FPGA-CPU-DRAM
communication performance is important, the Zync would win hands down.
 
On 17/01/14 21:19, John Larkin wrote:
Just got this from production:

https://dl.dropboxusercontent.com/u/53724080/PCBs/ASP_SN1_top.jpg

from previously posted layout...

https://dl.dropboxusercontent.com/u/53724080/PCBs/P344_15.jpg


This is a pretty serious signal processor application, but dropping
the Zed on there makes it easy. We can plug a USB logic analyzer
directly onto that Mictor connector, which has 16 signals and a clock
from the uZed.

Rather than being cautious, I just plugged 24 volts into it, and the
Zed lit up and ran Linux.
Click to expand...

Which version of the Xilix toolset are you using?

Please let us know if you continue to find things easy, or
if you have had to workaround infelicities.
 
четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
Hi ,

I need to implement a mono-stable MVB inside an Altera PLD. Could anyone
help ??

LEE
Click to expand...

I need too!!!!
 
Brian Drummond <brian3@shapes.demon.co.uk> wrote:
On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:
On 13/02/14 14:52, hodunov07@gmail.com wrote:
??????????????, 8 ?????????????? 1996 ??., 10:00:00 UTC+3 ???????????????????????? thomas ??????????????:
(snip)
Click to expand...

> 8 August 1996 ... is this a record?

Or someone forgot to set the clock on the computer.

I believe my posting host will refuse posts that are even a little
off, but not all will.

The exact 10:00:00 looks suspicious.

-- glen
 
On 13/02/14 14:52, hodunov07@gmail.com wrote:
четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
Hi ,

I need to implement a mono-stable MVB inside an Altera PLD. Could anyone
help ??

LEE

I need too!!!!
Click to expand...

I doubt that your problem (whatever it is) can only be
solved by a monostable.

Define /what/ you want to achieve, not /how/ you want
to achieve it. Then it will become obvious how to use
a PLD.
 
On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:

On 13/02/14 14:52, hodunov07@gmail.com wrote:
четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
Hi ,

I need to implement a mono-stable MVB inside an Altera PLD. Could
anyone help ??

LEE

I need too!!!!


I doubt that your problem (whatever it is) can only be solved by a
monostable.
Click to expand...

8 August 1996 ... is this a record?

- Brian
 
On 13/02/14 16:13, Brian Drummond wrote:
On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:

On 13/02/14 14:52, hodunov07@gmail.com wrote:
четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
Hi ,

I need to implement a mono-stable MVB inside an Altera PLD. Could
anyone help ??

LEE

I need too!!!!


I doubt that your problem (whatever it is) can only be solved by a
monostable.

8 August 1996 ... is this a record?
Click to expand...

<Swear words> I doubt it.

I looked at the headers in the repeated posting,
but skipped over the cyrllic!
 
On Thu, 13 Feb 2014 06:52:15 -0800, hodunov07 wrote:

четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
Hi ,

I need to implement a mono-stable MVB inside an Altera PLD. Could
anyone help ??

LEE

I need too!!!!
Click to expand...

Is there a prize available for the oldest dredged-up newsgroup posting?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
 
Brian Drummond wrote:
On Thu, 13 Feb 2014 15:45:45 +0000, Tom Gardner wrote:

On 13/02/14 14:52, hodunov07@gmail.com wrote:
четверг, 8 августа 1996 г., 10:00:00 UTC+3 пользователь thomas написал:
Hi ,

I need to implement a mono-stable MVB inside an Altera PLD. Could
anyone help ??

LEE

I need too!!!!


I doubt that your problem (whatever it is) can only be solved by a
monostable.

8 August 1996 ... is this a record?

- Brian
Click to expand...

Google Froups has breached the time-space continuum.

--
Les Cargill
 
On Tuesday, April 3, 2012 2:07:07 PM UTC+5:30, Uwe Bonnes wrote:
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

Elam <elampooranan@gmail.com> wrote:



I understand that the price depends on the volume etc

but I would like to know the per unit price of Virtex 7 FPGA..



Any guesses..



Search for XC7V on www.findchips.com.



No online availability for now. Prices last time I checked was up to 50 k$...



Bye

--

Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de



Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt

--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Click to expand...

The prices indicated are for trays? How to identify a tray or single device from the part number ? And how do we know how many parts are there in one tray ?
 
jkrshnan.v@gmail.com wrote:
On Tuesday, April 3, 2012 2:07:07 PM UTC+5:30, Uwe Bonnes wrote:
....
No online availability for now. Prices last time I checked was up
to 50 k$.
Click to expand...

Now 5k is a starting point...

The prices indicated are for trays? How to identify a tray or single device
from the part number ? And how do we know how many parts are there in
one tray ?
Click to expand...

The prices are per part...
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Den tirsdag den 11. marts 2014 22.23.36 UTC+1 skrev Jon Elson:
GaborSzakacs wrote:







A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)

to $39,452.40 (XC7V2000T-G2FLG1925E). These won't end up in any of my

designs any time soon.



REALLY! 1900 balls, and all of them have to solder perfectly or the chip

has to come off and be re-balled! Arghhhh! I'd LOVE to know who is

actually USING chips that expensive. Must be the military in those

$500 Million airplanes.

Jon
Click to expand...

if it does the job of an asic that would require a million dollar NRE and
you only need 20 it's a bargain

-Lasse
 
Tom Gardner <spamjunk@blueyonder.co.uk> wrote:
(snip)

I suspect the financial community as well. They will pay extraordinary
money to shave milliseconds off transaction times. Yes, they do encode
financial algorithms into FPGA hardware.

One well known example of their ability to spend money is that one
company spent $300m laying a transatlantic cable to reduce the
RTT of 65ms by 6ms.
Click to expand...

Must not have read "Wait: the art and science of delay."

-- glen
 
Den tirsdag den 11. marts 2014 23.18.47 UTC+1 skrev glen herrmannsfeldt:
Tom Gardner <spamjunk@blueyonder.co.uk> wrote:

(snip)



I suspect the financial community as well. They will pay extraordinary

money to shave milliseconds off transaction times. Yes, they do encode

financial algorithms into FPGA hardware.



One well known example of their ability to spend money is that one

company spent $300m laying a transatlantic cable to reduce the

RTT of 65ms by 6ms.



Must not have read "Wait: the art and science of delay."
Click to expand...

but for some reason they say that them making billions manipulating
prices by moving numbers around milliseconds faster than everyone
else is an essential service to society

-Lasse
 
langwadt@fonz.dk wrote:

(snip, regarding financial timins)

Must not have read "Wait: the art and science of delay."

but for some reason they say that them making billions manipulating
prices by moving numbers around milliseconds faster than everyone
else is an essential service to society
Click to expand...

You should read the book for the full details, but there was a group
that moved the whole operation closer to New York, and then found
that faster isn't always better.

The whole story of the book is that faster isn't always better,
and you should know when it might not be better.

-- glen
 
Uwe Bonnes wrote:
jkrshnan.v@gmail.com wrote:
On Tuesday, April 3, 2012 2:07:07 PM UTC+5:30, Uwe Bonnes wrote:
...
No online availability for now. Prices last time I checked was up
to 50 k$.

Now 5k is a starting point...

The prices indicated are for trays? How to identify a tray or single device
from the part number ? And how do we know how many parts are there in
one tray ?

The prices are per part...
Click to expand...

A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
to $39,452.40 (XC7V2000T-G2FLG1925E). These won't end up in any of my
designs any time soon.

--
Gabor
 
GaborSzakacs wrote:


A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
to $39,452.40 (XC7V2000T-G2FLG1925E). These won't end up in any of my
designs any time soon.
Click to expand...
REALLY! 1900 balls, and all of them have to solder perfectly or the chip
has to come off and be re-balled! Arghhhh! I'd LOVE to know who is
actually USING chips that expensive. Must be the military in those
$500 Million airplanes.

Jon
 
On 11/03/14 21:23, Jon Elson wrote:
GaborSzakacs wrote:



A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
to $39,452.40 (XC7V2000T-G2FLG1925E). These won't end up in any of my
designs any time soon.

REALLY! 1900 balls, and all of them have to solder perfectly or the chip
has to come off and be re-balled! Arghhhh! I'd LOVE to know who is
actually USING chips that expensive. Must be the military in those
$500 Million airplanes.
Click to expand...

I suspect the financial community as well. They will pay extraordinary
money to shave milliseconds off transaction times. Yes, they do encode
financial algorithms into FPGA hardware.

One well known example of their ability to spend money is that one
company spent $300m laying a transatlantic cable to reduce the
RTT of 65ms by 6ms.
http://www.telegraph.co.uk/finance/newsbysector/mediatechnologyandtelecoms/8753784/The-300m-cable-that-will-save-traders-milliseconds.html
 
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