EDK : FSL macros defined by Xilinx are wrong

[Phil Hays]

fpga_toys@yahoo.com wrote:

on a $100 wafer with 100 parts,

Wafer costs for leading edge processes were way over $100 in the
1980's when I was working in the semiconductor manufacturing business.
A quick google gets me:

http://www.icknowledge.com/economics/WaferCosts2005.html

Making leading edge chips is not cheap.


--
Phil Hays

 

Phil Hays wrote:

fpga_toys@yahoo.com wrote:

on a $100 wafer with 100 parts,

Wafer costs for leading edge processes were way over $100 in the
1980's when I was working in the semiconductor manufacturing business.
A quick google gets me:

http://www.icknowledge.com/economics/WaferCosts2005.html

Making leading edge chips is not cheap.

We all know that ... I choose a nice round number to do math with ...
that's all ...

The whole point is that perfectly good FPGA's aren't cheap ... and to
dump them without testing them at 80% off, is dumping high value
product below it's full value.

 

John_H wrote:

When the incremental sales are significant for a small percentage of Xilinx
customers, this program should have a long, happy existence.

Oh, and your flawless understanding of market dynamics has convinced me that
Xilinx is a bad investment. Yeah.

The Emperor's New Clothes ... even without clothes, he's still the
Emperor.

I assume that last straw of a jab, means that you decided that an 80%
discount is actually below cost.

Can I take my Devils Advocate hat off now?

 

fpga_toys@yahoo.com wrote:

We've heard a lot of whining about dropping non-profitable support ...
how long is a program going to last that ships as many perfect parts as
very slightly flawed parts?

Conversely, what really happens to the devices not originally allocated
to easypath which have single errors. Are they crushed and returned to
the sandbox? Or do they get a second chance at proving their worth, on
the easypath tester?

 

[Austin Lesea]

John,

How much is Altera paying you?

Austin

 

Peter Alfke wrote:

This should be understandable to
anybody with a high-school education.
Peter Alfke

hmmm just like putting a yellow sticker on $10m of perfectly good
parts, and calling them lemons to justify a sale below cost?

I think anybody with a high school education can figure that one out
too.

It also seems like a perfectly good scam for your production department
to take perfectly good tested parts, and ship them under the easypath
program for a huge kickback. How can you montor employee fraud with
such a dual labeling program with 80% discounts?

 

[Peter Alfke]

Are we continuing this thread until John (aka Mr Toy) has made a
complete fool of himself ?
His ranting is neither coherent nor entertaining or amusing anymore.
Peter Alfke

 

[Austin Lesea]

OK,

I agree.

I'm off to doing more useful things.

Austin

Peter Alfke wrote:

Are we continuing this thread until John (aka Mr Toy) has made a
complete fool of himself ?
His ranting is neither coherent nor entertaining or amusing anymore.
Peter Alfke

 

[John_H]

<fpga_toys@yahoo.com> wrote in message
news:1142623881.479071.57680@j33g2000cwa.googlegroups.com...

Peter Alfke wrote:
This should be understandable to
anybody with a high-school education.
Peter Alfke

hmmm just like putting a yellow sticker on $10m of perfectly good
parts, and calling them lemons to justify a sale below cost?

I think anybody with a high school education can figure that one out
too.

<snip>

So go to college. Specifically, pursue engineering economics or general
economics coursework.

There is so much more out ther in life than ones own little world. Explore
it.

 

[John_H]

<fpga_toys@yahoo.com> wrote in message
news:1142622269.421494.270850@j33g2000cwa.googlegroups.com...
<snip>

I assume that last straw of a jab, means that you decided that an 80%
discount is actually below cost.

Hell no.

 

Peter Alfke wrote:

Are we continuing this thread until John (aka Mr Toy) has made a
complete fool of himself ?

Ahh Peter .... you always run away shouting insults just when it's
getting fun.

His ranting is neither coherent nor entertaining or amusing anymore.

You haven't explained yet why throwing millions of dollars into the
trash can provides your stock holders the best possible ROI for money
spent on usable silicon with a very viable secondardy market willing to
do defect management?

In every other industry that's faced valuable high defect product
decisions, the've tossed the zero defect bitots out, to push up the
bottom line. Hopefully even Xilinx will reach the point that the zero
defect incompetents are no longer supportable or promotable. Anything
that increases Xilinx's sales without additional costs, can only
improve the bottom line, and hopefully for customers lower the prices
on other products that have had to carry the burden of the zero defect
bigots waste.

 

John_H wrote:

fpga_toys@yahoo.com> wrote in message
news:1142622269.421494.270850@j33g2000cwa.googlegroups.com...
snip
I assume that last straw of a jab, means that you decided that an 80%
discount is actually below cost.

Hell no.

Gee Wiz .... I've got to see your version of the math This is really
going to be fun!!!

 

[Phil Hays]

fpga_toys@yahoo.com wrote:

As soon as the chip becomes "hard" with the routing frozen, that
quickly goes away as an option, so that customer test vectors must be
written based for full coverage of the design again (just as with
ASICs). And good coverage BIST becomes difficult again.

As a former semiconductor test engineer, the hard part of FPGA
production testing is fairly easy to see. It is the interconnect.
Everything else looks very easy. Note that the FPGA under test will
be reloaded with a different design many times during test.

It seems to me that testing by loading BIST designs still makes a lot
of sense. Using a BIST design, the RAMs, multipliers, LUTs and
registers can be tested quickly. This is the easy part of testing a
FPGA. There would be little gain in customizing these tests.

This seems to me that it increases testing complexity and NRE, not
reduce it. That it then requires expensive testers for all testing,
rather than using generic loadable BIST configurations which can be
managed by less expensive test interfaces.

Most of the test time and cost for a standard FPGA would be needed to
test interconnect. There would be a lot less (several orders of
magnitude less) interconnect test time for an EasyPath part, as
compared with a standard FPGA. It looks to this former semiconductor
test engineer that the test cost of an EasyPath part might be between
30% and 5% of the test cost of a standard FPGA, depend on size of FPGA
and lot of things that I know that I don't know.

Now add in the effect of yields. This bring me to the amusing
realization that Xilinx might well have the same profit margin
percentage on an EasyPath tested FPGA than on the same standard tested
FPGA selling for five times as much.

While this all seems reasonable to me, I've been out of semiconductor
test for more than 20 years. YYMV, SRA.


--
Phil Hays

 

Peter Alfke wrote:

Without EasyPath any production device with any known defect (that is
not covered by an errata note) goes into the garbage can.
That has been and will remain our policy, and I assume the policy of
any reputable IC manufacturer.

Dodging the question.

What happens to devices run through the full (general application) test
program, which turn out to have single errors?

Are they retested for easy path use? or are they destroyed?

 

Phil Hays wrote:

It seems to me that testing by loading BIST designs still makes a lot
of sense. Using a BIST design, the RAMs, multipliers, LUTs and
registers can be tested quickly. This is the easy part of testing a
FPGA. There would be little gain in customizing these tests.

I agree Phil. The twist is that the customer can not take and use a
standard set of tests built for a fully functional part, otherwise it
will find and report all the untested errors creating a nightmare for
the field techs to sort out false positives. For field testing, the
tests really need to live inside the same set of qualified good
resources, which means customizing the tests for each qualified
easypath design, to stop the test from reporting errors on logic
resources not used.

 

Austin Lesea wrote:

John,

How much is Altera paying you?

Gee ... I've found that playing Devils Advocate would get me paid ....
how much should I be asking?

 

Austin Lesea wrote:

John,

How much is Altera paying you?

Next time you are in Longmont drop me a note, and take me to lunch

Maybe some face to face time will allow the petty BS to fade away.

 

fpga_toys@yahoo.com wrote:

Austin Lesea wrote:
How much is Altera paying you?
Next time you are in Longmont drop me a note, and take me to lunch
Maybe some face to face time will allow the petty BS to fade away.

Be sure and bring a briefcase full (about 4K) of the reject XC4VLX200
parts so I can stay busy building the next version of my home
reconfigurable super computer That ought to keep me busy and off CAF
for several months, if not a year

It might even give Xilinx some usable marketing collateral when I'm
done, and we can talk about buying reject parts for profit afterward
too!!

 

[Eric Smith]

fpga_toys@yahoo.com writes:

hmmm just like putting a yellow sticker on $10m of perfectly good
parts, and calling them lemons to justify a sale below cost?

Where do you come up with this "below cost" idea? I don't see any
evidence that supports it.

It also seems like a perfectly good scam for your production department
to take perfectly good tested parts, and ship them under the easypath
program for a huge kickback.

A kickback? From whom?

How can you montor employee fraud with
such a dual labeling program with 80% discounts?

Presumably Xilinx employs standard manufacturing traceability
procedures. It is not obvious that there is any more potential for
employee theft or fraud with Easypath than with their standard products.

Why do you care? If there were some unscrupulous employees, presumably
Xilinx would find and fix the problem themselves, with support from the
authorities as necessary.

Why do you have an axe to grind about Easypath?

 

[John_H]

<fpga_toys@yahoo.com> wrote in message
news:1142635551.101974.25260@u72g2000cwu.googlegroups.com...
<snip>

Nope ... I don't even know an Altera person. I do know or have met
several Xilinx people who have always been great people to deal with.
Every time I've been against the wall, there's been a Xilinx FAE to
help. Field staff always seem to have great customer skills.

Did you rail on Xilinx and their trashing young developers when the FAE was
there to help? Did you declare their datasheets a piece of crap because
they don't provide what you believe to be "proper" power data? Did you call
their business methods a scam?

Geeze, man - listen to yourself. Ask the FAEs that have been so helpful to
look at your threads and see if they'll side with you or try to help educate
you in the other aspects of Xilinx that are there to benefit the customer
base.

The written word is often a poor way to communicate for those who don't have
a solid understanding of professional interaction. Often all it takes is a
good conversation - face to face - to help the understanding come through.
If you're a customer in need and you ask for help from a respectable
company, you get courteous assistance. On this newsgroup you haven't been a
customer in need, you've been an agitator - specifically in this tired
thread you've been an underinformed "devil's advocate."

You help noone.