EDK : FSL macros defined by Xilinx are wrong

Johnson Lee wrote:
Hi,
I am new to FPGA design.
I am now need to make a switch to control the signals from PC LPT to a
character LCD module.
Right now I am using Altera UP1 demo board for verfication which has
1 MAX CPLD and 1 FLEX fpga. And I write a simple code just like
D_out <= D_in
using VHDL, like a wiring from input signals to outputs.

I check the LPT signals by connecting to LCD module directly and it
shows all the information I want. But After I connecting the FPGA
interfance, it never works.
I checked the pins again and again, but no use. Then I changed the
device from MAX to FLEX, but it didn't work, neither....

I also have another code which is used to initial LCD module and
show some words, after I programed, both devices work fine.
I don't know what's wrong inside and I even change the code by using
schmatics, still not working.
Is there anything I can do to improve this ?
Click to expand...
To summarise :-

Test 1: PC LPT-->FPGA-->LCD. FAILS.
Test 2: PC LPT-->CPLD-->LCD. FAILS.
Test 3: PC LPT-->LCD. No CPLD. No FPGA. Works OK.
Test 4: CPLD-->LCD. No PC. Works OK
Test 5: FPGA-->LCD. No PC. Works OK.

Is this correct?
Did you check _all_ outputs using an oscilloscope in tests 1+2?
Was the LCD connected to the same outputs in 1+2 as it was in 4+5?
Are you using the Altera Quartus development environment?
Could you post sample Quartus archive (.QAR) files?
 
"markp" <map.nospam@f2s.com> wrote in message
news:2vn75sF2o7m4kU1@uni-berlin.de...
Hi All,

I need to implement a low pass digital filter on 12 bit ADC data in a
Spatan
IIE device, but I'd like it to be multiplier free - in other words just
use
adders and bit shifting for the coefficients. The sample rate is 12Mhz and
I
need a sharp cut-off at around 3MHz. Does anyone know of a simple design
(IIR?) to do this, or a website/tutorial to give me some pointers? I've
seen
several websites with coefficient calculators, there are always a few
coefficients that can't be easily calculated with bit shifting and adding.

Thanks!
Click to expand...
depending what you need, one solution is very simple "digital integrator"
its doable with only shift and add, there is some appnote or something at
xilinx web, I used that in digital carrier frequency amplifier, and it did
give actually very good filtering (for my application at least).

an example digital integrator source is appended
---------
--
-- 18 Bit Digital Integrator Feedback "multiplier"
-- constant 1 / 256 (fixed, no choices implemented)
-- Tested and working.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;

entity integrator_18bit is Port (
rst : in std_logic;
clk : in std_logic;
din : in std_logic_vector(17 downto 0); -- Input: 18 Bit Unsigned
INTEGER
k : in std_logic_vector(3 downto 0); -- multiplier select (not
implemented)
dout : out std_logic_vector(17 downto 0) -- Output: 18 Bit
Unsigned INTEGER
);
end integrator_18bit;

architecture Behavioral of integrator_18bit is

signal acc : std_logic_vector(25 downto 0);
signal vi_minus_vo : std_logic_vector(25 downto 0);
signal vi_minus_vo_sign_extended : std_logic_vector(7 downto 0);

begin
-- Microblaze "endian" conversion
dout(0) <= acc(25); dout(1) <= acc(24); dout(2) <= acc(23); dout(3) <=
acc(22);
dout(4) <= acc(21); dout(5) <= acc(20); dout(6) <= acc(19); dout(7) <=
acc(18);
dout(8) <= acc(17); dout(9) <= acc(16); dout(10) <= acc(15); dout(11)
<= acc(14);
dout(12) <= acc(13); dout(13) <= acc(12); dout(14) <= acc(11); dout(15)
<= acc(10);
dout(16) <= acc(9); dout(17) <= acc(8);

-- Error Value
vi_minus_vo <= (din & "00000000") - acc;
-- Sign Extension for Error Value
with vi_minus_vo(25) select vi_minus_vo_sign_extended(7 downto 0) <=
"00000000" when '0', "11111111" when others;

process (clk) begin
if (rst='1') then
acc <= "00000000000000000000000000";
else
if (clk'event and clk='1') then
-- Accumulate
acc <= acc + (vi_minus_vo_sign_extended(7 downto 0) & vi_minus_vo(25
downto 8));
end if;
end if;
end process;

end Behavioral;
 
Dear Mark,
Seems to be a half-band filter (half of the Nyquist freq of 6 MHz) so, when
you use a FIR filter you can leave out half of the taps. The Xilinx core
generator can generate a nice filter for you. For the tap values use some
FIR design tool, look at www.mediatronix.com/tools for a free one, it can
export to Xilinx .coe files.
Regards,
Henk van Kampen
www.mediatronix.com

"markp" <map.nospam@f2s.com> wrote in message
news:2vn75sF2o7m4kU1@uni-berlin.de...
Hi All,

I need to implement a low pass digital filter on 12 bit ADC data in a
Spatan
IIE device, but I'd like it to be multiplier free - in other words just
use
adders and bit shifting for the coefficients. The sample rate is 12Mhz and
I
need a sharp cut-off at around 3MHz. Does anyone know of a simple design
(IIR?) to do this, or a website/tutorial to give me some pointers? I've
seen
several websites with coefficient calculators, there are always a few
coefficients that can't be easily calculated with bit shifting and adding.

Thanks!

Mark.
Click to expand...
 
Thanks Henk, this seems a nice tool. I'll have a play!

Mark.

"mtx" <mtx@xs4all.nl> wrote in message
news:4198a8f9$0$176$e4fe514c@dreader4.news.xs4all.nl...
Dear Mark,
Seems to be a half-band filter (half of the Nyquist freq of 6 MHz) so,
when
you use a FIR filter you can leave out half of the taps. The Xilinx core
generator can generate a nice filter for you. For the tap values use some
FIR design tool, look at www.mediatronix.com/tools for a free one, it can
export to Xilinx .coe files.
Regards,
Henk van Kampen
www.mediatronix.com

"markp" <map.nospam@f2s.com> wrote in message
news:2vn75sF2o7m4kU1@uni-berlin.de...
Hi All,

I need to implement a low pass digital filter on 12 bit ADC data in a
Spatan
IIE device, but I'd like it to be multiplier free - in other words just
use
adders and bit shifting for the coefficients. The sample rate is 12Mhz
and
I
need a sharp cut-off at around 3MHz. Does anyone know of a simple design
(IIR?) to do this, or a website/tutorial to give me some pointers? I've
seen
several websites with coefficient calculators, there are always a few
coefficients that can't be easily calculated with bit shifting and
adding.

Thanks!

Mark.
Click to expand...
 
"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0411250721.5b1e7f98@posting.google.com...
"Fred" <Fred@nospam.com> wrote in message
news:<41a49114$0$1067$db0fefd9@news.zen.co.uk>...
I see that Micron SDRAMs are claimed to support Concurrent auto
precharge.
Is this a common feature amongst SDRAMs?

I'm using a sample of a ICSI SDRAM at present and this feature isn't
mentioned in the data sheet. Is it safe for me to presume it doesn't
support Concurrent auto precharge?

I am trying to write and read blocks of 4 words and don't really want to
extend the buffering to accommodate an 8 word burst!

Hi,

do you mean that you want to precharge for example bank A while
still accessing bank B ?

Rgds
André
Click to expand...
Sorry for the delay in replying but yes it is where I can have 2 banks
active and use auto precharge to close a bank. The select another row, in
the bank just closed, to give a near continuous data flow.
 
"Fred" <Fred@nospam.com> wrote in message
news:41ab5c09$0$1059$db0fefd9@news.zen.co.uk...
"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0411250721.5b1e7f98@posting.google.com...
"Fred" <Fred@nospam.com> wrote in message
news:<41a49114$0$1067$db0fefd9@news.zen.co.uk>...
I see that Micron SDRAMs are claimed to support Concurrent auto
precharge.
Is this a common feature amongst SDRAMs?

I'm using a sample of a ICSI SDRAM at present and this feature isn't
mentioned in the data sheet. Is it safe for me to presume it doesn't
support Concurrent auto precharge?

I am trying to write and read blocks of 4 words and don't really want
to
extend the buffering to accommodate an 8 word burst!

Hi,

do you mean that you want to precharge for example bank A while
still accessing bank B ?

Rgds
André

Sorry for the delay in replying but yes it is where I can have 2 banks
active and use auto precharge to close a bank. The select another row, in
the bank just closed, to give a near continuous data flow.
Click to expand...
ICSI have admitted that this device is from an old batch of silicon which
doesn't have this feature. I find it a bit annoying that there isn't a
revision code on the IC which could have had a corresponding datasheet.
Amazing lack of change control. Beware!
 
Dear mr nospam,

I agree as well, unfortunatly the same goes with other online media too,
like the www.egroups.com was good until yahoo did buy them, now it (yahoo
groups) is total crap, similarly many unmoderated mailing lists have very
high noise of people asking help for homework, etc..

In order to have better communication media I have always dreamed to have my
own news server, which is now finally setup - its not open for public as I
have not yet managed to complete the news server authorisation setup and
some other admin tasks, but I plan to announce it ASAP, for anyone
interested or having good advice please respond either to usenet or to
antti@openchip.org specially if somebody can help setting up the
readers.conf file would be great help for me. The news server is running on
my root-server under suse 9.1, I think the latest INN is installed as news
server.

Antti Lukats

"nospam" <nospam@nospam.invalid> wrote in message
news:g0s2t05dqijpkfhm8co7ijcvcd9vt5mh02@4ax.com...
vizziee@yahoo.com wrote:

Hi all,

I need some good primer books on Handel-C. Plz. send-in the titles.
Thanx in advance.

A typical post originating from Google groups:-

Hi
Solve my problem.
Thanx

Searching google reveals the poster has about a dozen posts, none of which
are outside threads he started and all bar one of which were started
asking 'usenet' to solve his problem.

Why should I (or anyone) be inclined to solve the problem of someone who
almost certainly will not even read let alone solve my problems?

Google provides a great usenet archive and search engine, their web based
posting facility is providing a bunch of information leeches which will
turn usenet into a wasteland of unanswered questions.

I wish I could killfile anyone posting from google, I suggest everyone
else
ignores them.
Click to expand...
 
* PERSONAL :

First name : SEYED AMIR HOSSEIN
Last name : SIAHPOSHHA
Birth Date : 20 February 1977
Birth Place : Qazvin, IRAN
Status : Male & Single
Health : Excellent
Address :
Iran, city:Qazvin, street:Khayam, alley:Qazal, No.:15
Zip-code : 3413798673
Phone : (0098)-281-3335405
E-mail : siahpoushha@yahoo.com

* OBJECTIVES :

Hello dear Professor.
I am planning to continue my graduate studies in the
field of computer engineering(software)to Ph.D.
degree.
I need your complete help for accept of scholarship
and enter to Ph.D. degree.
Please help and guide me, Professor.

Best regards,
Siahpousha.

* EDUCATION :

2000-2002 : M.Sc. student at Tehran Islamic Azad
University, Tehran, Iran.
Field of study : Computer Engineering (software),
Average (out of 20) : 17.53

1995-1999 : B.Sc. student at Qazvin Islamic Azad
University, Qazvin, Iran.
Field of study : Computer Engineering (software),
Average (out of 20) : 13.53

1991-1995: High School Diploma ,Pasdaran High School,
Qazvin, Iran.Field of study : Physics & mathematics.

* WORK EXPERIENCE :

I am teaching in Qazvin IAUniv. and other universities
for 3 years(2001-2004). I am teaching list of courses:
Data structures,Data load and store,Data base and SQL,
Operating systems,computer networks,systems Analise
and design,turbo C++ and Pascal programming languages.

* THESIS AND RESEARCH ( FIELD OF STUDY ) :


The thesis I presented at the end of my education
(Master of Science), was about Multimedia-Networking,
in which I presented a network transfer protocol
design to use extensively off-line multimedia data in
Data gram and wide area networks. My research was
about helpers and other network manageable elements
for management Data gram and wide area networks, and
optimizing networks resources usage.

ATM and MBone and other virtual circuit and wide area
networks that design for multimedia data can not
completely solve problem using extensively multimedia
data, because the size of multimedia data is very
large and video compression techniques are not enough.
Over Internet and other Data gram and wide area
networks that design for graphic and textual data,
this problem is very large. On-line multimedia data
(for example Internet TV, video conference and etc.)
use the optimum and minimum of the resources networks,
since Resource reservation protocol (RSVP) make a
multicast tree over network for giving service all of
users requests and also sever is serving one
multimedia stream for servicing to the users.
Multicast tree puts network major load over private
path and near by user, and also it puts network minor
load over shared path and near by server. Off-line
multimedia data (for example propaganda and news
reports, video-on-demand and etc.) are important
because of its usage but it has a lot of problems.
User asynchronous requests make network resources
usage neither minimum nor optimum, since network will
be over loaded for any multimedia data and server is
serving a multimedia stream for any user request.

Dynamic caching technique can not solve this problem
completely. User requests rate, server and network
load power predetermine the type and size of off-line
multimedia data in any server now. I use SOCCER2000
model from Bell-laboratories in my M.Sc. thesis.
Helper is element that helping to server for serving
multimedia stream, in this model. Helpers are caching
static and dynamic multimedia stream. SOCCER2000
presents cooperation between helpers. I found some
problem and error in this model, and I have completed
and corrected it. I also presented two simple design
for new type of helpers cooperation. I presented new
methods for static caching and multiple serving of RTP
packet by cooperating helpers that correct the noise
and error of multimedia stream, when serving from
helpers.

I insert dynamic framing technique to my models, too.
If multimedia data transmission over networks becomes
optimum then it is time to use large size packet. Big
packet simulates static routing and virtual circuit
networks. Band width allocates more to data transfer
because header number become fewer. If multimedia data
transmission was not optimized over network then we
use little size packet. Small packet is simulating
dynamic routing and Data gram networks. Band width
allocates more to data transfer because multiplexing
degree become more.

In the end I am wait hearing from you very soon.
Thank you very much, good luck, good bye.
 
In article <1105837359.911078.236150@z14g2000cwz.googlegroups.com>,
<tvnaidu@yahoo.com> wrote:
Hello, I have two questions about Electronic circuit board design.
These are the questions:

1st question:
What is the main difference between FPGA and ASIC, recently I went to
Click to expand...
Field Programable Gate Array: a bunch of logic cells that you can program
to do lots of different things. One of these things would may be the
thing you want done.

Application Specific Integrated Circuit: a chip designed to do a certain
job or a small group of jobs. If you want to do something else get a
different chip.


some exhibition, there I heard from somebody, he says "we are designing
a prototype handset based on FPGA, which was used between DSP chip and
main processor, later on we will go wityh ASIC", I didn't understand
quite well, what was the main difference, also whereever FPGA was used,
can that be replaced by ASIC?.
Click to expand...
Basically it like this:

You can make the prototype with very costly general purpose FPGAs, some
DSPs, and have a cable running off to a big battery. This version costs a
billion dollars each. Our target cost is 3 dollars so we will have to
spend 10 Million on making a custom chip and sell about 4 million units to
make it pay.

2nd question:
What are the main stepps involved in circuit board design?.
Click to expand...
1) Decide what the bourd should do.
2) Make a schematic that does that.
3) Decide the mounting issues.
4) Select the component packages.
5) Buy board layout software if you intend to do it yourself
6) Start placing the parts
7) Discover that they won't fit and loop back to 3
8) Finish placing
9) Start running the traces
10) Discover that you can't route as placed and loop back to 8
11) Finish routing
11) Check the proposed layout
12) Rip out large sections and loop back to 8
13) Check the improved version
14) Check it again
15) Make Gerber plots and an NC drill file
16) Check the Gerbers and drill file
17) Compose a README.TXT
18) Zip together the Gerber, NC drill and README.TXT
19) Get bids on making the board
20) Select a vendor and send off the files
21) Get a phone call from the vendor pointing out an error
22) Loop back to 11 and increase the ring on the vias etc
23) Get the boards from the FAB house.
24) Gather the parts needed
25) Discover that you can't get the MOSFET in a DPAK loop back to 4
26) Stuff the board
27) Apply power
28) Scrape the burning parts off your face
29) Replace the burned parts
30) Apply the right power the right way around this time
31) Begin debugging the board
32) Discover the errors that are not just part values
33) Loop back to 1
34) Prepair BOMs etc for the production build.
35) Fight off the accounting guy who wants to lower cost.
36) Make the pre-pre-production units
37) Correct the BOM and assembly drawings
38) Start testing the pre-pre-production units
39) Build the pre-production units
40) Do major testing
41) Discover that the specifications from marketing have changed
42) Loop back to 1


--
--
kensmith@rahul.net forging knowledge
 
On Sat, 15 Jan 2005 17:02:39 -0800, tvnaidu wrote:

Hello, I have two questions about Electronic circuit board design.
These are the questions:

1st question:
Click to expand...
[snip]

2nd question:
What are the main stepps involved in circuit board design?. Suppose if
I want some board to be designed, what are the steps I have to do (like
a fabless design), how can I contact the fab to get my prottype board
as well as production baord?.
Click to expand...
The first step should be a specification for the finished design. This
might include mechanical specifications as well as functional and power
consumption specifications. If UL and FCC (or similar) approvals are
required, that should be part of the specification, too.

Then I guess schematic capture would be the next step. Schematic capture
just means drawing the schematic with appropriate software. Around this
time you want to start making sure that you can get all the parts you are
using.

The next step would be layout. To do this, you have to decide how many
layers the board will be, where the parts will go on the board, where you
want to put fills and floods and so on. Any nets requiring special
treatment might best be done first. At this stage you want to have samples
of the parts on hand so you can compare the physical part with the layout
you are doing.

When layout is finished, you need to prepare the fabrication files and
send them off to the board house. They can then give you a quote for what
the raw boards will cost. Around this time you want to have all your parts
in stock in quantities sufficient for the number of boards you will build.

Once the boards come back, someone will need to solder all the parts to
the board, and do any required mechanical assembly. Sometimes the raw
boards are tested, either by the fabricator or by you.


Thanks in advance, appreciated.
Click to expand...
If you have limited personnel, you can contract out some or even all of
the design. Or you could write the specification, draw the schematic,
and write layout guidelines, then contract out the rest of the design
and fabrication. But layout can be absolutely critical for some designs,
so be careful!

In general, if the design involves one or more of the following,
layout might be critical: small analog (or RF) signals; fast digital
signals; high voltage, power or current.

I should re-iterate that if the finished product requires agency approvals
(FCC, UL, etc.) then you will need to take that into account from the
beginning.

--Mac
 
HAI
I AM VIVEK. CAN YOU PLEASE GUIDE ME IN DESIGNING MULTIPLIER BY
WALLACE TREE ARCHITECTURE IN VHDL/FPGA
 
HI,
I AM SYMON. I CAN USE GOOGLE. I SHOUTED WALLACE TREE MULTIPLIER INTO THE
SEARCH BOX AND IT GAVE ME 7980 HITS. NUMBER 5 WAS THIS ONE
http://www.andraka.com/multipli.htm
Syms.
<VIVEKEDU2003@YAHOO.CO.IN> wrote in message
news:1105991360.684965.235960@f14g2000cwb.googlegroups.com...
HAI
I AM VIVEK. CAN YOU PLEASE GUIDE ME IN DESIGNING MULTIPLIER BY
WALLACE TREE ARCHITECTURE IN VHDL/FPGA
Click to expand...
 
On Sun, 16 Jan 2005 11:51:37 -0500, Mark Jones wrote:
Ken Smith wrote: (answering "What are the main stepps involved in circuit board design")


1) Decide what the bourd should do.
....
42) Loop back to 1



This is good! We should put this in a F.A.Q. ;)
Click to expand...
Done:
http://www.fpga-faq.com/FAQ_Pages/0043_Steps_to_make_a_Printed_Circuit_Board.htm



===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM
 
On Mon, 17 Jan 2005 06:07:15 GMT, Rich Grise <richgrise@example.net> wrote:
On Sun, 16 Jan 2005 11:51:37 -0500, Mark Jones wrote:

Where's the FAQ?

Thanks,
Rich
Click to expand...
The FPGA FAQ is at: http://www.fpga-faq.com


===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM
 
"Weddick" <weddick@comcast.net> wrote in message
news:ZZOdnWsnGoUBzGHcRVn-gw@comcast.com...
I am just starting with VHDL and have been doing software for the last 20
years. My project that I am trying to get working is part of a memory
controller which will allow different processes to request access to the
memory.

The portion of the code that I posted works great when I do the Behavioral
Model Simulation. When I do the post-Place & Route VHDL Model Simulation
the first write cycle does not work. You can see that it processes
through the states but the data out and address lines don't change as
expected.

I would appreciate any help with this problem. Hopefully it's just
something stupid. That always makes me feel better.

Joel
Click to expand...
Joel,
When I compiled the source to gates, and ran the simulation, I got a lot
of timing violations.

In the testbench, how do you control the set up and hold of the inputs to
the uut with respect to clk? (especially data_valid, rst, ack) Do you
constrain tbe implementation with timing constraints from a UCF file?

-Newman
 
Weddick wrote:

The only thing that I had put in the UCF file was the clock period. I
will
admit I don't know much about this file and what should be set. I
attached
the UCF file and help in additional settings would be appreciated.
Actually
the UCF file that I created was for the higher level project. So maybe
the settings never got flowed down?
Click to expand...
Your problem is that the inputs(rst, data_valid, ack) are not synchronized.
Also I don't understand why "write" should be 'Z' some times. Also you'd
better synchronize your outputs too.

vax, 9000
 
Joel,
I added the ucf file and added offset in of 4 ns for grins. When I went
into the dreaded gate level simulation debug. I noticed that
write_device_tb/uut/current_state_ffd2_94/rst
write_device_tb/uut/current_state_ffd2_94/srst
did not have the same delay values. I increased the testbench delay rst
value to 125 ns, and it appeared to help.
There may be some active reset minimum in the gate level simulation for
some type of reset on configuration thingy.

-Newman

"Weddick" <weddick@comcast.net> wrote in message
news:IaOdnWe-DuutgGDcRVn-ig@comcast.com...
The only thing that I had put in the UCF file was the clock period. I
will admit I don't know much about this file and what should be set. I
attached the UCF file and help in additional settings would be
appreciated. Actually the UCF file that I created was for the higher
level project. So maybe the settings never got flowed down?

Joel


"newman5382" <newman5382@yahoo.com> wrote in message
news:rE%Kd.8455$JO2.6607@tornado.tampabay.rr.com...

"Weddick" <weddick@comcast.net> wrote in message
news:ZZOdnWsnGoUBzGHcRVn-gw@comcast.com...
I am just starting with VHDL and have been doing software for the last 20
years. My project that I am trying to get working is part of a memory
controller which will allow different processes to request access to the
memory.

The portion of the code that I posted works great when I do the
Behavioral
Model Simulation. When I do the post-Place & Route VHDL Model
Simulation
the first write cycle does not work. You can see that it processes
through the states but the data out and address lines don't change as
expected.

I would appreciate any help with this problem. Hopefully it's just
something stupid. That always makes me feel better.

Joel



Joel,
When I compiled the source to gates, and ran the simulation, I got a lot
of timing violations.

In the testbench, how do you control the set up and hold of the inputs
to
the uut with respect to clk? (especially data_valid, rst, ack) Do you
constrain tbe implementation with timing constraints from a UCF file?

-Newman
Click to expand...
 
muthusnv@rediffmail.com wrote:
Hi,
There chips with the mixture of Active HIGH and Active LOW signals. Is
there any pros and cons of each levels? OR it simply choice of
designers / manufacturers?

Thanks in advance.

Regards,
Muthu
Click to expand...
Unconnected TTL inputs are interpreted as logic high. Hence it is more
convenient to define the active level of control signals as logic low
and allow the designers to simply not connect the pins carrying those
signals if they don't need them. Also, if a cable is unplugged from a
board the inputs read high (not active) and the board does not attempt
to do anything unexpected.

Active low is also commonly used for signals with multiple drivers,
e.g., interrupt request lines. In this case there is a pull-up resistor
and open-collector or open-drain drivers that pull the singnal low.

My 2c.
-- Georgi
 
Thanks Newman,
I made that change also and it seemed to help. At least it runs.

Joel

"newman5382" <newman5382@yahoo.com> wrote in message
news:vKbLd.9279$JO2.713@tornado.tampabay.rr.com...
Joel,
I added the ucf file and added offset in of 4 ns for grins. When I went
into the dreaded gate level simulation debug. I noticed that
write_device_tb/uut/current_state_ffd2_94/rst
write_device_tb/uut/current_state_ffd2_94/srst
did not have the same delay values. I increased the testbench delay rst
value to 125 ns, and it appeared to help.
There may be some active reset minimum in the gate level simulation for
some type of reset on configuration thingy.

-Newman

"Weddick" <weddick@comcast.net> wrote in message
news:IaOdnWe-DuutgGDcRVn-ig@comcast.com...
The only thing that I had put in the UCF file was the clock period. I
will admit I don't know much about this file and what should be set. I
attached the UCF file and help in additional settings would be
appreciated. Actually the UCF file that I created was for the higher
level project. So maybe the settings never got flowed down?

Joel


"newman5382" <newman5382@yahoo.com> wrote in message
news:rE%Kd.8455$JO2.6607@tornado.tampabay.rr.com...

"Weddick" <weddick@comcast.net> wrote in message
news:ZZOdnWsnGoUBzGHcRVn-gw@comcast.com...
I am just starting with VHDL and have been doing software for the last
20
years. My project that I am trying to get working is part of a memory
controller which will allow different processes to request access to the
memory.

The portion of the code that I posted works great when I do the
Behavioral
Model Simulation. When I do the post-Place & Route VHDL Model
Simulation
the first write cycle does not work. You can see that it processes
through the states but the data out and address lines don't change as
expected.

I would appreciate any help with this problem. Hopefully it's just
something stupid. That always makes me feel better.

Joel



Joel,
When I compiled the source to gates, and ran the simulation, I got a
lot
of timing violations.

In the testbench, how do you control the set up and hold of the inputs
to
the uut with respect to clk? (especially data_valid, rst, ack) Do you
constrain tbe implementation with timing constraints from a UCF file?

-Newman
Click to expand...
 
I guess I don't understand what your getting at. How should they be
synchronized? (Example?)
Is there a better way that I should be coding this so everything is
synchronized?

Thanks,
Joel


"vax, 9000" <vax9000@gmail.com> wrote in message
news:ctjfao$prv$1@charm.magnus.acs.ohio-state.edu...
Weddick wrote:

The only thing that I had put in the UCF file was the clock period. I
will
admit I don't know much about this file and what should be set. I
attached
the UCF file and help in additional settings would be appreciated.
Actually
the UCF file that I created was for the higher level project. So maybe
the settings never got flowed down?

Your problem is that the inputs(rst, data_valid, ack) are not
synchronized.
Also I don't understand why "write" should be 'Z' some times. Also you'd
better synchronize your outputs too.

vax, 9000
Click to expand...
 
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