EDK : FSL macros defined by Xilinx are wrong

[Doug Miller]

If you are using ISE 6.1, also check the "Clock Information:" section of
your SYR (Synthesis) file. In some cases, it (erroneously) generates
additional clocks from combinatorial logic. From some of my own experience,
I've noticed this sometimes this can be cured by making sure that all
possible states are defined in your combinatorial logic.

Example - Extra clocks will be generated if the two commented lines below
are left commented, but will not be generated if they are uncommented.

if (currentState = IDLE) then
if (someTrigger = '1') then
nextState <= SOME_OTHER_STATE;
-- else
-- nextState <= IDLE;
end if;
end if;


"Jerker Hammarberg (DST)" <jerkerNO@SPAMdst.se> wrote in message
news:40ec3825_4@read01.nntp.se.dataphone.net...

Hi all! I'd like to once again bring up the subject of state machines
running into illegal states (illegal in the sense that the state vector
does
not correspond to any of the states defined in the VHDL code), because
despite having spent half a day googling and reading related threads, I'm
still left with a couple of questions:

1. Most discussions cover how to recover from illegal states, but few
cover
how it actually happens. What are the (I presume) electrical reasons to
that
a state machine runs into an illegal state in the first place? Is there
anything one can do to reduce the risk? Assume all FSM inputs connected to
I/O pins are synchronized with one FF each, and the whole design is
synchronous. Does anyone know of a good tutorial on this issue? I could
add
that in my case, the transition into an illegal state almost always happen
immediately upon startup of the system, if it happens.

2. How can I force Xilinx XST (6.2 SP3) to produce a safe FSM that
recovers
from an illegal state? A "when others => state <= IDLE;" clause doesn't
seem
to help (which I think is stupid, isn't this problem so well known that
they
should make XST recognize it instead of optimizing it away?). I realize
that
changing coding style to "Binary" will reduce the number of illegal state
and thus the risk for it to happen, but it's not completely safe, unless
the
number of states is a power of two. What's more, binary coding style seems
to increase slice utilization for the whole design by up to 10%.

Thanks in advance!

/Jerker

 

[rickman]

Mike Treseler wrote:

rickman wrote:


I am writing some code to help me simplify simulation data display and I
want to have some SLV constants in an array. These constants relate to
defined states of a combination of signals and have names associated
with them. To get the names to show up in the simulation, I want to use
an enumerated type which then corresponds to the index of the constant
array.
Can I directly use this enumerated type as the index?

yes

I am still a day
or so from having some code to try. Am I barking up the wrong tree with
this?

No, it's a good idea.

Should I convert my enum variable to an int and use that as the
array index?
subtype ALUSLV is SLV07;
subtype ALUTyp is (AD, ADC, SU, SUC, CM, CMC, AN, LOR, LXR, SR, SC,AER);

type ALUstyles is array (ALUTyp) of ALUSLV := (
"00100XX", ...

I see. Maybe like this:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity alu_test is
end alu_test;
-------------------------------------------------------------------------------
architecture sim of alu_test is
subtype ALUSLV is std_logic_vector(7 downto 0);
type ALUTyp is (AD, ADC, SU, SUC, CM, CMC, AN, LOR, LXR, SR, SC, AER);
type ALUstyles is array (ALUTyp'left to ALUTyp'right) of ALUSLV;
constant init : ALUstyles := (AD => x"42", ADC => x"ff", others => x"00");
begin
-- sim processes
end architecture sim;

Thanks. Shortly ago, I got word back from a friend who had borrowed my
one book that actually talked about this. But your example shows me I
was mixing my type def with my constant declaration.

I am unusually tired tonight and am packing it in. I see I am making
more errors than I am fixing I will hate to see what errors the
simulator gives me when I try to compile tomorrow.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[David]

Maybe, we can add it to the 'Downloads' section at FPGAworld.com??

 

[Martin Schoeberl]

I have added a section about the LEGO motor driver on the website
(http://www.jopdesign.com/lego/index.jsp).

You can find mesurements of the PWM output from the original LEGO RCX, a
simple schemantic
with an L283D driver and sigma-delta ADCs for back-EMF measurements.

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

 

[Mikeandmax]

manygates asked:

GAL,PAL,PLD, CPLD,FPGA, (what else...?)

GAL : Generic Logic Array
PAL : Programmable Array Logic
PLD : Programmable Logic Device
CPLD : Complex Programmable Logic Device
FPGA : Field Programmable Gate Array

Can someone explain with comparison what is the difference between all these
GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units?

Can all these units can be programmable with VHDL ?

This could take awhile

The most basic thing all of these have in common is the ability to create
unique circuit configurations on a standard device, and with most, the ability
to erase these configurations, and create new ones. If we had a time machine
to go back - way back, we would find only devices with fixed architecture
elements, e.g. SSI devices(small scale integration) andgates(7408)
nandgates(7400), or gates (7432) inverters (7404) and then a big jump to MSI
(medium scale integration) like 7474(d flipflop with set/reset) counters (74161
- 4bit counter) , and the industry continues into LSI, VLSI, ASICs,
uprocessors, memories, etc....

then this idea of PLD - programmable logic device
by using fuses in an array, speicific configurations can be accomplished- by
connecting traces in the metal layers on a device, making the gates connected
to them form new circuits - unfortunately, fuses only work once - testing by
the manufacturer was limited - after all, how do we test a fuse?

PAL programmable array logic
early PALS were in preset configurations - where fuses could acitivate some
customization - the pal16l2, the pal16r4, had and/or gate structures, or
limited registers to certain points -
somewhere along the way - UVerasable arrived, displacing one time programmable
fuses - with a nice quartz window, so you could flood the connections with UV
to reset the programming cell - and use a nice paper label to cover it up when
programmed - and with UV, testing by the manufaturer improved, as a pattern
could be built, then removed, although with 30-60minute erase times, it was
still limited -

GALs - neat concept - all possible PAL configurations could be
accomplished,e.g., 16v8 - Variable function, as the 'macrocell' for each output
pad had both combinatorial and registered capability, and even better, these
werre electrically erasable(EECMOS) and could easily be tested and erased in
milliseconds

Along came FPGA and CPLD

I know I am leaving out a bunch of detail - the various vendors do a superb job
of describing in detail in their literature -


CPLD - Complex Programmable Logic Device
early CPLD structures were closely related to the GAL/PAL idea, and created an
array of PALs ( think LAB, or GLB, or PALblock, or functionblock) in various
sizes and what not -
CPLDs at their most basic are this A COMPLEX LOGIC BLOCK - with anywhere from
36 to 68 inputs available per block, with a range of PTERMS(and gate) from 1 to
160, available to drive each macrocell - combinatorial or registered.
Mostly NONVOLATILE devices(EECMOS) with some newer devices also incorporating
SRAM as part of the architecture, decent clock structures, high performance for
large, single logic level functions - think statemachines, decoders, counters
etc -
Routing and interconnect is typically a single large central routing array - so
interconnecting logic has little penalty in routing - and within the LOGIC
BLOCK - there is full interconnect for the various elements

FPGA Field programmable Gate Array -
FPGAs are devices which can achieve significantly larger logic gate counts,
with each logic element TYPICALLY being built with a 4input LUT(look up table -
which allows pretty much any combination of 4 inputs ) with a combinatorial
and/or registered output available per logic element - each vendor has thier
own 'tweek' on this with additinal logic for muxes, carrychainsfor arithmetic/
counting functions, etc -I'm sure others will jump in here) - nad since the
logic element is small, a lot more fit on a device!. To interconnect these
logic cells requires significant routing, or interconnect, resources, to build
a larger function out of the many small functions. Much magic is required
here, by the silicon designers to balance resource requirements, and the SW
designers, to implement algorithms which efficiently connect the elements
together.
FPGAs generally offer additional elements, e.g. RAM BLOCKS, so that more
complex system functions can be implemented within the single device. As
technology has moved forward, many different elements have found their way into
FPGA - processors, SERDES, DSPBLOCKS etc.

MOSTLY based on SRAM processes, they offer rapid reconfigurability as well,
with the burden of storage somewhere in the system for the datastreams required
to configure the device. There are Vendors with NONVOLATILE FPGAs as well,
running form FUSE BASED(one time programmable) to Flash and eecmos based
devices which incorporate flash and eecmos memory to carry the datastream for
configuration on chip.

I hope this was a good start - Peter, Paul, Austin, Jim, Rick, Ray, Uwe, any
others out there want to expand on these points?

Mike Thomas
Lattice SFAE NY/NJ

 

Dear Mikeandmax

THANK YOU VERY MUCH for your very valuable posting.
I've enjoyed reading it and learnt alot in few paragraphs.

Regards,

"Mikeandmax" <mikeandmax@aol.com> wrote in message
news:20040820105045.12055.00004128@mb-m01.aol.com...

manygates asked:
GAL,PAL,PLD, CPLD,FPGA, (what else...?)

GAL : Generic Logic Array
PAL : Programmable Array Logic
PLD : Programmable Logic Device
CPLD : Complex Programmable Logic Device
FPGA : Field Programmable Gate Array

Can someone explain with comparison what is the difference between all
these
GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units?

Can all these units can be programmable with VHDL ?

This could take awhile

The most basic thing all of these have in common is the ability to create
unique circuit configurations on a standard device, and with most, the
ability
to erase these configurations, and create new ones. If we had a time
machine
to go back - way back, we would find only devices with fixed architecture
elements, e.g. SSI devices(small scale integration) andgates(7408)
nandgates(7400), or gates (7432) inverters (7404) and then a big jump to
MSI
(medium scale integration) like 7474(d flipflop with set/reset) counters
(74161
- 4bit counter) , and the industry continues into LSI, VLSI, ASICs,
uprocessors, memories, etc....

then this idea of PLD - programmable logic device
by using fuses in an array, speicific configurations can be accomplished-
by
connecting traces in the metal layers on a device, making the gates
connected
to them form new circuits - unfortunately, fuses only work once -
testing by
the manufacturer was limited - after all, how do we test a fuse?

PAL programmable array logic
early PALS were in preset configurations - where fuses could acitivate
some
customization - the pal16l2, the pal16r4, had and/or gate structures, or
limited registers to certain points -
somewhere along the way - UVerasable arrived, displacing one time
programmable
fuses - with a nice quartz window, so you could flood the connections with
UV
to reset the programming cell - and use a nice paper label to cover it up
when
programmed - and with UV, testing by the manufaturer improved, as a
pattern
could be built, then removed, although with 30-60minute erase times, it
was
still limited -

GALs - neat concept - all possible PAL configurations could be
accomplished,e.g., 16v8 - Variable function, as the 'macrocell' for each
output
pad had both combinatorial and registered capability, and even better,
these
werre electrically erasable(EECMOS) and could easily be tested and erased
in
milliseconds

Along came FPGA and CPLD

I know I am leaving out a bunch of detail - the various vendors do a
superb job
of describing in detail in their literature -


CPLD - Complex Programmable Logic Device
early CPLD structures were closely related to the GAL/PAL idea, and
created an
array of PALs ( think LAB, or GLB, or PALblock, or functionblock) in
various
sizes and what not -
CPLDs at their most basic are this A COMPLEX LOGIC BLOCK - with anywhere
from
36 to 68 inputs available per block, with a range of PTERMS(and gate) from
1 to
160, available to drive each macrocell - combinatorial or registered.
Mostly NONVOLATILE devices(EECMOS) with some newer devices also
incorporating
SRAM as part of the architecture, decent clock structures, high
performance for
large, single logic level functions - think statemachines, decoders,
counters
etc -
Routing and interconnect is typically a single large central routing
array - so
interconnecting logic has little penalty in routing - and within the LOGIC
BLOCK - there is full interconnect for the various elements

FPGA Field programmable Gate Array -
FPGAs are devices which can achieve significantly larger logic gate
counts,
with each logic element TYPICALLY being built with a 4input LUT(look up
table -
which allows pretty much any combination of 4 inputs ) with a
combinatorial
and/or registered output available per logic element - each vendor has
thier
own 'tweek' on this with additinal logic for muxes, carrychainsfor
arithmetic/
counting functions, etc -I'm sure others will jump in here) - nad since
the
logic element is small, a lot more fit on a device!. To interconnect
these
logic cells requires significant routing, or interconnect, resources, to
build
a larger function out of the many small functions. Much magic is required
here, by the silicon designers to balance resource requirements, and the
SW
designers, to implement algorithms which efficiently connect the elements
together.
FPGAs generally offer additional elements, e.g. RAM BLOCKS, so that more
complex system functions can be implemented within the single device. As
technology has moved forward, many different elements have found their way
into
FPGA - processors, SERDES, DSPBLOCKS etc.

MOSTLY based on SRAM processes, they offer rapid reconfigurability as
well,
with the burden of storage somewhere in the system for the datastreams
required
to configure the device. There are Vendors with NONVOLATILE FPGAs as
well,
running form FUSE BASED(one time programmable) to Flash and eecmos based
devices which incorporate flash and eecmos memory to carry the datastream
for
configuration on chip.

I hope this was a good start - Peter, Paul, Austin, Jim, Rick, Ray, Uwe,
any
others out there want to expand on these points?

Mike Thomas
Lattice SFAE NY/NJ

 

[Rune Christensen]

"Ian"
<${send-direct-email-to-news1021-at-jusme-dot-com-if-you-must}@jusme.com>
skrev i en meddelelse news:Q0qZc.555637$6p.104886@news.easynews.com...

On Wed, 1 Sep 2004 12:36:04 +0200, Rune Christensen
rune.christensen@adslhome.dk> wrote:

Does anyone know if it's possible to build a VGA to ethernet converter? A
device that converts a VGA signal to a digital videostream.
I want to be able to operate a computer from a remote position also when
the
computer boots. So I will be able to change bios settings, starting mode
of
Windows, etc.

Some "server management" cards do just this. Needs to either snoop the bus
for VGA
accesses or fully emulate a VGA adapter (i.e. they /are/ the VGA adapter
for the
machine). Quite expensive to buy, quite hard to make...


--
Ian

'Milk below!'

I think that this must the easiest solution to the problem. Create a VGA
card that transfer the screen to ethernet instead of a screen. Maybe a PCI
FPGA card could be used to do this.

To the people on comp.arch.fpga have anyone tried to create a VGA card on a
PCI FPGA card?

Thanks
Rune Christensen



---
Outgoing mail is certified Virus Free.
Checked by AVG anti-virus system (http://www.grisoft.com).
Version: 6.0.746 / Virus Database: 498 - Release Date: 31-08-2004

 

[INS122595]

We done similar projects, the critical point is if many VGA standard need be
supported

Walter


"Rune Christensen" <rune.christensen@adslhome.dk> a écrit dans le message de
news:41384139$0$195$edfadb0f@dread12.news.tele.dk...

"Ian"
${send-direct-email-to-news1021-at-jusme-dot-com-if-you-must}@jusme.com
skrev i en meddelelse news:Q0qZc.555637$6p.104886@news.easynews.com...
On Wed, 1 Sep 2004 12:36:04 +0200, Rune Christensen
rune.christensen@adslhome.dk> wrote:

Does anyone know if it's possible to build a VGA to ethernet converter?
A
device that converts a VGA signal to a digital videostream.
I want to be able to operate a computer from a remote position also
when
the
computer boots. So I will be able to change bios settings, starting
mode
of
Windows, etc.

Some "server management" cards do just this. Needs to either snoop the
bus
for VGA
accesses or fully emulate a VGA adapter (i.e. they /are/ the VGA adapter
for the
machine). Quite expensive to buy, quite hard to make...


--
Ian

'Milk below!'

I think that this must the easiest solution to the problem. Create a VGA
card that transfer the screen to ethernet instead of a screen. Maybe a PCI
FPGA card could be used to do this.

To the people on comp.arch.fpga have anyone tried to create a VGA card on
a
PCI FPGA card?

Thanks
Rune Christensen



---
Outgoing mail is certified Virus Free.
Checked by AVG anti-virus system (http://www.grisoft.com).
Version: 6.0.746 / Virus Database: 498 - Release Date: 31-08-2004

 

[Andrew Dyer]

On Fri, 03 Sep 2004 12:02:36 +0200, Rune Christensen wrote:

Does anyone know if it's possible to build a VGA to ethernet converter? A
device that converts a VGA signal to a digital videostream.
I want to be able to operate a computer from a remote position also when
the
computer boots. So I will be able to change bios settings, starting mode
of
Windows, etc.

some 'server' type computers have a BIOS that will allow you to do
the basics over a serial port. After the computer comes up you
can run something like windows' RDP or VNC for a remote desktop.

Some "server management" cards do just this. Needs to either snoop the bus
for VGA
accesses or fully emulate a VGA adapter (i.e. they /are/ the VGA adapter
for the
machine). Quite expensive to buy, quite hard to make...


--
Ian

'Milk below!'

I think that this must the easiest solution to the problem. Create a VGA
card that transfer the screen to ethernet instead of a screen. Maybe a PCI
FPGA card could be used to do this.

To the people on comp.arch.fpga have anyone tried to create a VGA card on a
PCI FPGA card?

This isn't all that simple - assume your video stream is
800x600x8bits per pixel x 60 hz (~230 mbits/sec). To make it
work, you'll have to run gigabit ethernet, drop bits or frames,
compress or some mixture of these.

Next problem is how to get at the screen data - you could implement a
whole vga subsystem (don't forget BIOS and drivers), snoop the PCI bus
(need to track the state of a real vga chip which can be tricky), get a
digital copy of the VGA output data (not all vga chips have digital out)
or recapture the data from an analog copy (probably don't have access to
the pixel clock, so you need PLLs to recapture the data).

 

[H. Peter Anvin]

Rune Christensen wrote:

I think that this must the easiest solution to the problem. Create a VGA
card that transfer the screen to ethernet instead of a screen. Maybe a PCI
FPGA card could be used to do this.

To the people on comp.arch.fpga have anyone tried to create a VGA card on a
PCI FPGA card?

There are VGA capturing solutions, but it's probably easier to do with DVI.

Doing a VGA card is pretty difficult; VGA is a pretty complex thing. It
is probably easier to have a standard video chip which outputs DVI or
some kind of LCD interface, and then capture it and send out the
Ethernet in whatever protocol you wish.

-hpa

 

[Luc]

Look at Lattice's XPLD. They have in each XPLD 2 PLL's that you can
use at will, and you don't consume logic to build the DLL.

Regards

On 16 Sep 2004 08:46:23 -0700, sch@elpro.at (Kriki) wrote:

I need to program a digital PLL in a CPLD.

I tryed to use an external Clock Generator @ 24.576 MHZ, but the data
signal is not exactly that frequency.

So can anyone help me with that problem ???

 

[Prasanth Kumar]

On Sun, 2004-09-19 at 18:04 +0000, Andre Bonin wrote:

cristian wrote:

Andre,

I do agree with Symon, specially if you have a software background. Be
careful when trying to synthesize (HARDWARE) your software.

The goal of the project is ADPCM encoding and a 10x10 integer matrix
multiplication, i think that could be done within the FPGA. it would be
*nice* to be able to implement any C algo within hardware but i do
accept their are limitations. Though for some odd reason VHDL seems
more apt and less 'picky' about these kinds of loops. Or am i being
deceived?

Anyway, below is an example of how to implement a while_loop in VHDL.
I added some comments reagarding the conditions under which the
whil_loop is implemented;

Thank you for this piece of code, it helps me get started and play
around with VHDL. VHDL seems more 'higher level' then verilog. For
this type of task, do you reccomend VHDL or Verilog? VHDL is an older
standard but my work with verilog gives me the hint that its lower level.
snip

There is always Handel-C which supports most of the C constructs
(for, while, arrays, pointers, functions, etc) in FPGA hardware.

 

[matt parker]

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[H. Peter Anvin]

Followup to: <5c1de958.0306261459.7fe34c7d@posting.google.com>
By author: gregs@altera.com (Greg Steinke)
In newsgroup: comp.arch.fpga

For either device, you do not need to compute the PLL values - if you
tell Quartus the requirements it will compute the PLL settings for
you.

I've had problems with Quartus II 4.1 (Web Edition SP0-2) and getting
the PLL values to make sense. In particular, if I feed it:

fin = 50 MHz
c0 = 4/1 = 200 MHz
c1 = 1/4 = 12.5 MHz

.... it says it cannot make the desired PLL. 2.x and 3.x both did this
correctly, and if I lie and specify fin = 75 MHz it builds the correct
PLL and it works correctly with a 50 MHz input. The timing analyzer
spits out a message that the input frequency has been overridden (by
specifying clkin = 50 MHz as a timing constraint) and does the right
thing.

This is for a Cyclone EP1C20F400C7 device.

-hpa

 

[Subroto Datta]

"H. Peter Anvin" <hpa@terminus.zytor.com> wrote in message
news:cjcq0b$8g4$1@terminus.zytor.com...

For either device, you do not need to compute the PLL values - if you
tell Quartus the requirements it will compute the PLL settings for
you.


I've had problems with Quartus II 4.1 (Web Edition SP0-2) and getting
the PLL values to make sense. In particular, if I feed it:

fin = 50 MHz
c0 = 4/1 = 200 MHz
c1 = 1/4 = 12.5 MHz

... it says it cannot make the desired PLL. 2.x and 3.x both did this
correctly, and if I lie and specify fin = 75 MHz it builds the correct
PLL and it works correctly with a 50 MHz input. The timing analyzer
spits out a message that the input frequency has been overridden (by
specifying clkin = 50 MHz as a timing constraint) and does the right
thing.

This is for a Cyclone EP1C20F400C7 device.

-hpa

Hello Peter,

Quartus configures PLLs that satisfy all the device constraints (e.g.
VCO range, PFD range, etc), which is why it cannot build the specific
configuration you suggested for a Cyclone device (though it can be built
in Stratix/StratixGX/StratixII devices).

In Cyclone devices, the VCO frequency must be between 490 Mhz and 1000
Mhz. For the example you gave, the resulting PLL's VCO frequency for a
75 Mhz input would be 600 Mhz (since the M counter is 8, and N counter
is 1). But if you manually bypass this safeguard and feed in a
frequency of 50 Mhz, the PLL's VCO frequency would be 400 Mhz, which is
outside the supported range for Cyclone PLLs.

In the situation described above (75 Mhz input selected, but
50Mhz actual) the PLL is operating outside the specified range, so
jitter performance and static phase shift may be adversely affected.
This limit was set in Quartus II 3.0 SP2 for the first time, as a result
of characterization of the Cyclone devices. Previously, in Quartus II
3.0, the limit was 300 Mhz, based on preliminary simulation results.

Hope this helps.
- Subroto Datta
Altera Corp.

 

[john jakson]

sruthi <sruthi.teja@rediffmail.com> wrote in message news:<ee893ae.-1@webx.sUN8CHnE>...

I would like to implement Cache memory in to
FPGA / CPLD. I would like to use LRU replacement policy for that.
SO could any one suggest me whiich cache placement policy is best suited
for that, whether the fully associative or 2- way set assosiative.

Is it possible to implement LRU fully assosiative
cache in to any FPGA or CPLD device family.

Using LRU for 2 way only means 1 bit toggle per set line, but 4 way
requires 4.3.2 states more trouble than its worth. Given all the
states involved, it is indeed possible but the simpler schemes will
give almost as good a result. Intel used a 3b (1,1,1) toggle hierarchy
with almost as good a result called pseudo LRU for 1 of their 4way
designs.

If you are starting out in cache design in FPGA you should probably do
a direct mapped (1 way) with random replacement. From there on
onwards, it gets more complex for each extra feature.

Fully associative cache is really out of the question for both FPGA &
ASIC as the assoc row decode adds dearly to access times. But the
various 2,4,8 way mapped schemes work almost as well.

I have a Cache book by Jim Handy which goes from very light reading to
quite deep once it gets into the more interesting issues but it never
addresses the special issues regarding FPGA design, being written for
TTL to ASIC readers.

There is a way to get fully associative without requiring complex fast
HW but it involves a more SW like approach ie hashing addresses into a
somewhat empty table. The access time will be a faster cycle * some
factor between 1-inf with an avg that can be close to 1.5 cycles for a
50% full ram. You trade 1 problem for varying acceess times and must
keep memory table atleast 30% empty. This has been used for Inverse
Page Table MMUs by IBM too. I am using it too since varying cycles
don't bother me much. In more complex typical cache designs for
multiple cpus trying to maintain cache coherancy, they already must
get into varying timings depending on snoop, bus interference as well.



regards

johnjakson_usa_com

 

[Martin Schoeberl]

If you are starting out in cache design in FPGA you should probably do
a direct mapped (1 way) with random replacement. From there on
onwards, it gets more complex for each extra feature.

What do you mean with random replacement in a direct mapped cache? With

direct mapped you don't have a decision which block gets replaced. The
block is determined by the address. That's one reason why direct mapped
is simpler and a suitable choice for FPGAs.

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

 

[Prasanth Kumar]

On Wed, 2004-10-20 at 18:41 -0400, Jason Berringer wrote:

Hello all,

I have a general question regarding asynchronous and synchronous resets.
Does an async. reset slow down the speed of a circuit? Is it better to use a
synchronous reset, or if possible no reset at all to speed up a design? I'm
just curious as I have a larger project which has a single async reset to a
lot of different blocks using the typical:

if (reset = '0') then
...
elsif (rising_edge(clk)) then
...
else
...
end if;

Not all block require the reset since they are downstream of earlier ones
with a reset and their state isn't critical, I have just always included
them. That being said I want to speed up the design, and in one block I took
out the reset and it seemed to boost the performance slightly.

Any comments would be appreciated.

Jason

If you are using Xilinx FPGAs then they have a nice techxclusives
article about just this.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?
sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_smart_reset

 

[Prasanth Kumar]

On Thu, 2004-10-21 at 04:01 -0700, Srinivas wrote:

Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA.
Srinivas

It would depend on your operating system. If it is Windows, then there
are a couple helpful documents in Microsoft's MDSN site. Search for
"Serial Communications C" or something like that. It will probably take
2 to 3 pages of code to setup the serial channel.

 

[thangkho]

Coding serial communication for DOS is simple since you can control the port registers directly, however it's not easy task in windows unless you familiar with C/C++, win32 API, MFC...if you own a VSC++ develope studio, there's some good examples, check for the project TTY