EDK : FSL macros defined by Xilinx are wrong

choices
* Pico(Paco)Blaze
* AVR
* C16 from opencores
* aeMB is not fully compliant as MicroBlaze i have tested with assembly
programs but some commands are wrong, so its not ready for c compiler

if you have S400 or larger than you can use some 32 bit cores, in S200
it is getting very tight with 32 bit processors (commercial MicroBlaze
is ok in S200)

if you are looking to have full normal GCC support the there are no so
many options :(
LEON3 smallest system fits s400

Antti
 
The gr16/32 CPUs are very old and designed in Verilog, but you might
still find them useful.

I think Jan Gray ported LCC to the architecture and also had a complete
SoC example with UART and everything.



Speaking of aaMB, did they actaully looked if it FITS into an apa150
when they wrote the docs??
 
<burn.sir@gmail.com> schrieb im Newsbeitrag
news:1144579508.239684.10820@e56g2000cwe.googlegroups.com...
The gr16/32 CPUs are very old and designed in Verilog, but you might
still find them useful.

I think Jan Gray ported LCC to the architecture and also had a complete
SoC example with UART and everything.



Speaking of aaMB, did they actaully looked if it FITS into an apa150
when they wrote the docs??

you mean "aeMB" ?
Click to expand...
the original author did very little testing and the core is not full,
it does do lots of instructions ok, but I think it messes up with delay
slots and link register
I think it should fit into APA150 but I havent run that synthesis

but just out curiosity i peeked into my trashbox and did run synthesis of
NIOS-II clone for Lattice XP3:
605 slices - 39% :)
hum maybe I should continue the work on that

Antti
 
"Peter Winkler" <idontwant@totell.com> schrieb im Newsbeitrag
news:1ndi32lhgriblsukneeh81cifdf8gnqac2@4ax.com...
Thanks for your suggestions ! I think I will have a look at these two:

* Pico(Paco)Blaze
* AVR

I very much like AVR controllers, so maybe it is a good idea to
look at this core. And there is also WinAVR. I hope I can get
it to run on my XC3S200.

Don't you think it is somewhat strange, that there are so few
options for a soft prozessor for hobby stuff ? Is it so much work
to design a soft core ? Not sure, but looking at the AVR core
from opencores, it seems development was stopped in 2003
and only a limited number of I/O lines are available. However,
I am very glad that it exists at all ... ;)

P.
Click to expand...
it does exist and does work
I have done some work with it
1) I think i had made verilog version of it
2) tried to use better io peripheral bus system that would be configurable
3) one time had it integrated into Xilinx EDK !
4) I have a special toplevel that works as Atmel appnote AVR910 compatible
programmer

in the opencores version there is base address of one port wrong
and yes the development is pretty much stopped

an no its not hard to write a processor ip-core not at all
but having full infra-structure, peripheral bus and compiler support, and
debuf support
is what makes it more complex task

Antti
 
On 8 Apr 2006 16:10:26 -0700, "Isaac Bosompem" <x86asm@gmail.com>
wrote:

Maybe an OpenRISC?

They have a GCC port for the chip on freecores.org, though the simplest
config on my XC3S200 would use up ~75% of it!

-Isaac
Click to expand...
That may be a little bit too large for me :)
 
Another point regarding the latency of the dynamic phase shifting - the
data sheet states:

"The phase adjustment may require as many as 100 CLKIN cycles plus
three PSCLK cycles to take effect, at which point the output PSDONE
goes High for one PSCLK cycle."

In reality, what does "may require" mean?

Is there anything that can be done (eg. through CLKIN or PSCLK
frequency selection say) to reduce this 100 CLKIN cycles?

Does this "100 CLKIN cycles" vary between devices, with Vcc, temp?

I would like to avoid experiments with actual devices during my design
phase.
 
burn.sir@gmail.com wrote:
Having seen way too much spam on this newsgroup lately, I have come
with a possible solution that just might work.

Add a section to FPGA FAQ where the known names on the newsgroup will
list the companies they recommend (plus some explanation). Next time
someone spams the list about "high quality PCB", or what the hell it
is, we post a polite response saying that no one should support spammer
companies and we suggest you choose another manufacture from the list
below (link to FPGA-FAQ follows).Given that spammers only care about
money, seeing they are loosing customers might stop them from spamming
the list.
Click to expand...
You're assuming that they actually read any responses :) Still, not a
bad plan.

Jeremy
 
Prakash wrote:
Hi,
Iam trying to download opensource processor in xilinx dev. board
XUPV2P. I'm not using any of the features like (Power PC/ controllers)
which are inbuilt / xilinx prop.
Now I've a doubt If suppose I configure my bit file thro' USB Jtag
interface, should my logic (to be downloaded) contain the JTAG
controller also, or the controller is hard coded in the chip.

I get a warning while generating programming file in ISE,
WARNING:Bitgen:244 - The IEEE1532 option implies that JTAG
configuration will be
used. Using a StartupClk setting other than JtagClk could prevent
proper
device startup.
Please help esp. the second part of warning,
Prakash
Click to expand...
when you generate the bitstream for JTAG programming, you need to check
an option startupclk=jtagclk, otherwise (slave serial, or other non JTAG
config) you need to have startupclk=cclk or startupclk=userclk)
what this means? after configuration (and during configuration) a state
machine will take care of the start-up of your design, ie. releasing the
global reset, releasing the global tristate for the IOs, assertin DONE
pin etc. This option in the bitstream generation will "tell" to the fpga
the source of clk for this state machine (this information is embedded
into the bitstream file) when impact will program the fpga, impact knows
the interface you choose and is checking against the bistream do see is
the startup-clk option makes sense for the chosen programing interface.

Aurash
 
Hi Prav,

"prav" <praveen.kantharajapura@gmail.com> wrote in message
news:1144660513.037870.46910@z34g2000cwc.googlegroups.com...
Hi all,
I wanted to know how many CLB's does a 8:1 mux implementation take in
a ALTERA and a XILINX device. I wanetd the details of the internal
implementation also(like how many LUT's )are used.
Click to expand...
This depends very much on exactly what family you are talking about.
Different device families have different capabilities, and also different
numbers of slices per CLB. You should look at the datasheets for details.

In all Xilinx FPGAs since Spartan-II & Virtex, there are dedicated
multiplexor resources that make 4:1 and larger muxes quite efficient. A
1-bit 8:1 mux will require 4 LUTs to implement the four first-stage 2:1
muxes. Then there are two second-stage 2:1 muxes, which can use an "F5" mux,
and a single final-stage 2:1 mux which can be an "F6".

So the total is 2 slices (the Fx muxes are "free" within the slice). In
older parts that equates to 1 CLB; in anything newer than Virtex-II, that is
0.5 CLB. In any case, this will be a very fast function since the routing to
and from the Fx multiplexors is dedicated.

One more doubt i had if the depth of the multiplexer increases can the
LUT' s be shared.
Click to expand...
I'm not sure what you mean by that. I *think* the answer is no.

Cheers,

-Ben-
 
Thanks, I think that , since Iam trying to program by USB Jtag, the
warning I got is harmless and in my case its correctly assigned
(startupclk=jtagclk).
I didnt get an answer for, whether I need to integrate JTAG controller
in logic, assign the TMS, TCK...pins or controller is hard coded, and
no need to concern in my logic (probably second is right).

Prakash
 
Ben Jones schrieb:
One more doubt i had if the depth of the multiplexer increases can the
LUT' s be shared.


I'm not sure what you mean by that. I *think* the answer is no.
Click to expand...
Maybe he means the width. There are indeed some optimizations that you
can do for wider muxes.
If you have an N-Bit wide M-to-1 Mux, there is a certain N for each M at
which it becomes benefitial to use first stage that outputs 0 or the
input value depending on the select value and that reduce these with an
OR-tree or the carry chain. Muxes reduce at a rate of 2-to-1 per LUT
while OR reduces at a rate of 4-to-1.

Also note that a multiplier or a BRAM can implement a MUX.

Kolja Sulimma
 
For anyone facing the same problem, here is a nice document to clear up
a little of the confusion. The file psf_rm.pdf which describes MPD,
MHS, MSS etc.... syntax and usage guide can be found in this
directory: %XILINX_EDK%\doc directory.
 
Prakash wrote:
Thanks, I think that , since Iam trying to program by USB Jtag, the
warning I got is harmless and in my case its correctly assigned
(startupclk=jtagclk).
I didnt get an answer for, whether I need to integrate JTAG controller
in logic, assign the TMS, TCK...pins or controller is hard coded, and
no need to concern in my logic (probably second is right).
yes, it's a hard block, for configuration you dont't have to do anything
Click to expand...
it will be there for you,
however you can hook it to your design, if you wish, to
triger/debug/scan different parts of your logic.

Aurash
Prakash
Click to expand...
 
You have 20 different addresses for the 20 replications, correct?
Which FPGA family are you using?

"mikel" <mikel262@gmail.com> wrote in message
news:1144679157.026889.187140@t31g2000cwb.googlegroups.com...
Hello

How to implement on-chip ROM memory resource sharing in FPGA? I
implemented discrete cosine transform core using parallel distributed
arithmetic approach, in which hardware multipliers are substituted by
precomputed MAC results stored in LUT/ROM. Single ROM instance is 64x14
bits. Problem is that the ROM must be replicated many times to enable
high throughput (replicated 9 times for first DCT stage and replicated
11 times for 2nd stage after transposition). This ends up having more
than 25kbits of ROM memory in the core, which is pretty big. I know
there are dual port memories with dual read port capability, but this
will 'only' halve resources needed. Any better ideas?

Michal
Click to expand...
 
The only thing special about the locations of the DCMs is what clock input
pins they are near or what partial or global clock buffers they drive. Your
design will often have physical constraints for pin placement which, in
turn, drives where the logic will typically be placed. The ins and outs of
the DCMs in your design are best physically associated with the input pin
and driven logic. The device has a specific number of resources with
explicit XY locations; you can leave it to the tool to find a decent
solution (no LOC constraints) or make the decision based on your knowledge
of the design.

Sometimes it's helpful to run the design without DCM LOC constraints, see if
the results are acceptable, then copy the DCM locations for that place &
route run into your constraints.

"Prakash" <prakash.na@gmail.com> wrote in message
news:1144678847.133938.255900@i40g2000cwc.googlegroups.com...
In one of the ucf file I could see these. I could understand the logic
element dll0 is constrained to be placed at DCM_X2Y1. I could see there
are more such DCM_X#Y#. How can I associate for my chip, means how can
I select the # for my chip. Also here dll0/1 is constrained two times.
Is it to make absolute/relative paths of them so that approprite
software can take.

INST "clkgen0_v_dll0" LOC = DCM_X2Y1;
INST "clkgen0_v_dll1" LOC = DCM_X1Y1;
INST "clkgen0/xc2v.v/dll0" LOC = DCM_X2Y1;
INST "clkgen0/xc2v.v/sd0.dll1" LOC = DCM_X1Y1;

Prakash
Click to expand...
 
"Peter Winkler" <idontwant@totell.com> skrev i meddelandet
news:1ndi32lhgriblsukneeh81cifdf8gnqac2@4ax.com...
Thanks for your suggestions ! I think I will have a look at these two:

* Pico(Paco)Blaze
* AVR

I very much like AVR controllers, so maybe it is a good idea to
look at this core. And there is also WinAVR. I hope I can get
it to run on my XC3S200.

Don't you think it is somewhat strange, that there are so few
options for a soft prozessor for hobby stuff ? Is it so much work
to design a soft core ? Not sure, but looking at the AVR core
from opencores, it seems development was stopped in 2003
and only a limited number of I/O lines are available. However,
I am very glad that it exists at all ... ;)

P
Click to expand...

You may want to check Atmels Patent portfolio.
Have heard claims that it is impossible to replicate the core without
violating some patents.
Don't know if anyone would bother about hobbyist use of the OpenCore
version.
You can still download the core which is a positive sign, but I really do
not know.

--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB
..
 
If you use both clock edges, any path between the two clock domains has
less than half a clock period available ( since it also must accomodate
any duty-cycle difference from 50%.)
That's not a smart design decision, if you want to achieve high
performance.
Peter Alfke
 
John,

Actually, the LUT/ROM is replicated twice as much as I said before (18
times 1st stage, 22 times 2nd stage). Synthesis tool was smart enough
to reduce size of ROMs memory bits from 35840 bits to 25600 bits (there
are few identical values inside every ROM, synthesis tool placed
additional decoding logic for input address to reduce memory size). But
this is still too much.

You have 20 different addresses for the 20 replications, correct?
Click to expand...
yes, I have different address for every ROM access, and I need to
access all ROMs at the same clock cycle for performance.

Which FPGA family are you using?
Click to expand...
I want design to be generic, though I ordered Virtex 2Pro board from
Digilent so this will be my target.

Michal K
 
Thanks for all your input.

I think it makes most sense for me to have a closer look
at PicoBlaze.

Is there a good place for PicoBlaze designs apart from the
Xilinx PicoBlaze home ? I mean some kind of community like
avrfreaks or the piclist ? A place to ask stupid newbie
questions, you know ;)

P.
 
Peter Winkler wrote:
Thanks for all your input.

I think it makes most sense for me to have a closer look
at PicoBlaze.

Is there a good place for PicoBlaze designs apart from the
Xilinx PicoBlaze home ? I mean some kind of community like
avrfreaks or the piclist ? A place to ask stupid newbie
questions, you know ;)
Click to expand...
You should also look at the extended variant :

http://bleyer.org/pacoblaze/

plus rhere are good links on this page.

-jg
 
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