EDK : FSL macros defined by Xilinx are wrong

[John_H]

"Nitesh" <nitesh.guinde@gmail.com> wrote in message
news:1138228419.957001.253480@z14g2000cwz.googlegroups.com...

Let me rephrase my question.
I have a fpga pci card with a dual pci bridge between the virtex II pro
and the pci bus of the host computer to which this card is connected.
The processor bus connects fpga with the bridge.
The dual pci bridge from tundra is dma capable. I have changed a core
(A processor bus master/slave) in the fpga to provide this dma
functionality. My aim is to transfer data from the fpga to the host
memory. I can provide the source address which is an address of a
location inside the fpga. Now my problem is that what should be the
destination address ? I have to send the data to the host RAM. Since
this address has to be pre decided before a transaction can begin how
can I get this value in the fpga so that I can program this from the
fpga.

As stated before, the software on the host computer side needs to allocate
memory space for the DMA destination. If the address and size can be fixed,
your task is simple. It's more likely that the memory allocation will be
dynamic and the host system has to communicate the FPGA in some fashion what
the address range is for the DMA. Then and only then should the FPGA do its
DMA. You can't move data to the host memory, after all, if the host is
executing out of the memory you're writing to. If the host allocates it,
the memory won't be used by the operating system or other devices.

 

[Ed McGettigan]

fpga_toys@yahoo.com wrote:

I should probably note that Xilinx leaches a hell of a lot of value off
open source by using Linux as a host platform for it's tools, GCC as
the main production compiler for PPC core software, GNU for the
libraries for PPC, and Linux in several forms as host operating systems
for it's product offerings.

It's probably worth writing Austin, Peter, and the other regular usenet
posters from Xilinx and making it clear just how much Xilinx benefits
from open source, the Xilinx market created by open source, and the
developers which frequently volunteer their time supporting Xilinx open
source use.

I take umbrage to your assertion that Xilinx is a leach and doesn't
contribute back to the open source communities. Xilinx has been a
contributing Corporate Patron of Free Software Foundation for many
years now https://www.fsf.org/donate/patron/index_html funding many
open source projects through the FSF with our donations.

In addition we funded, supported and developed the Virtex-II Pro and
Virtex-4 PowerPC405 ports that are the parent post of this thread and
then push for their release into the official Linux 2.4.x and 2.6.x
PowerPC trees so that everyone will have access to them easily.

Ed McGettigan
--
Xilinx Inc.

 

[Kevin Morris]

So, I have a question regarding the assertion that the datasheet LUT
count is "important information."

Why? What is the real-world utility of that number? Do some people
know up-front how many LUTs their design is gonna use, and then they
just need an accurate LUT count to pick the best FPGA?

The problem with programmable logic datasheets is that it's almost
impossible to put any real, relevant information on them. A FEW things
- number of SerDes transceivers, maybe user pin count, marginally
available block RAM... are kinda useful, but for everything else,
don't you really need to just do the design and see what device the
tools tell you to use?

I've written a couple of articles on/around this topic. My favorite
was:
http://www.fpgajournal.com/articles/20040706_tango.htm

and people also seem to like:
http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm

Kevin

 

[Paul Marciano]

John Adair wrote:

You might want to have a look at our product Raggedstone1. It has the much
larger XC3S400-4FG456C part fitted. Programming cable is included and card
can be used in a PCI slot or stand-alone with the optional PCI I/O Header.
Details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html.

As a learner and experimenter I like the look of that board, but how
much does the Xilinx PCI core for the Spartan 3 cost?

Paul.

 

[austin]

Kevin,

If I have learned anything from this thread, it is that there are folks
for which the "actual number" is a religious matter.

Once the "actual number" is revealed in its glory, there are even a
further class of folks who still doubt: there is still some nefarious
untruth, or hidden secret that is intentionally not being revealed by
the evil FPGA vendor. The Da Vinci Bit Code, if you will.

They weave a web of untruths and half whispers with convenient
coincidences to explain their troubles.

Alas, all I can do is deal with those whose questions I can actually answer.

Peter and I have decided that having the actual numbers is good, so we
go to battle to do just that.

No need to thank us.

Thanks for your support,

Austin

 

[yyqonline]

I have found that there is "clock high time violation" while timing
verification using Altera QuartusII, with device "flex10K". I wonder
whether this is caused by the pulse width, depending on gate delay, not
long enough for driving FSM.
Best Regards,
YuQing, Youth

 

[JJ]

That should have been split

http://www.huffcrimeblog.com/

http://www.embeddednt.com.
A purveyer of FPGA, DSP, FPU cores etc?


transputer guy

 

[Jim Granville]

yyqonline wrote:

I have found that there is "clock high time violation" while timing
verification using Altera QuartusII, with device "flex10K". I wonder
whether this is caused by the pulse width, depending on gate delay, not
long enough for driving FSM.
Best Regards,
YuQing, Youth

Yes, see my earlier comment about CLK_min, that meant not FREQ,
but the HI and LOW minimum times that all clocks have.
Such a circuit will generate needle pulse clocks, so you will
need to watch the Min pulse widths.

-jg

 

[Peter Alfke]

If you really need to clock a flip-flop on both clock edges, the
circuit described in the recent posting by Bob Perlman (and apparently
originated by Gabor, whom I have contacted and congratulated) is really
much better and cleaner than my frequency doubler. Maybe a bit more
expensive, but flip-flops and XORs are cheap, and headaches are
expensive.
Peter Alfke, from home

 

Ed McGettigan wrote:

I take umbrage to your assertion that Xilinx is a leach and doesn't
contribute back to the open source communities. Xilinx has been a
contributing Corporate Patron of Free Software Foundation for many
years now https://www.fsf.org/donate/patron/index_html funding many
open source projects through the FSF with our donations.

First, if Xilinx had not been so heavy handed with the JHDLBits
project,
trashing the efforts of a half dozen young engineers, your umbrage
might
be half way valid. But the reality is that the economic value of gcc,
GNU,
and Linux is significantly more than $10M-30M NRE and $1m-3m/yr as
the UNIX licenses and royalities would have cost you more. The real
value
of GPL tools that you ship, if the company had developed GPL free
version
is an order of magnitude or two more than that.

*IF* your contributions to open software are a significant fraction of
the
equivalent UNIX license fees, then sure, Xilinx is paying it's way.

In addition we funded, supported and developed the Virtex-II Pro and
Virtex-4 PowerPC405 ports that are the parent post of this thread and
then push for their release into the official Linux 2.4.x and 2.6.x
PowerPC trees so that everyone will have access to them easily.

That is completely self serving to generate revenues from the hardware
sales. the PPC port existed long before Xilinx started shipping the IBM
core in Pro's.

 

[David Brown]

yyqonline wrote:

Thanks!
I use the circuit posted by Bob Perlman to construct a FSM just now and
the performance of timing verification via QuartusII seems to be good.
I think this may be a solution, but I whether I made the best choice to
construct the module.
Requirement:
*the work freq is 640Khz
*the expected datarate is 640K, 320K, 160K
*since this chip will be passive (without battery), power consumption
is very important
*when datarate is 640K, either higher freq (at the cost of higher power
consumption) or det(at the cost of larger area) have to be introduced;
while datarate is lower than 640K, neither is needed.
Then, I have three ways to choose from:
*a whole module using det-FSM
advantage: only one Fsm
disadvantage: extra control part, to decide whether negedge of clk is
active
*a module consisting of a det-FSM part and a set-FSM
(single-edge-trigged FSM) part
advantage: easy to realize
disadvantage: two groups of state registers
*a module using higher freq, esp. 1.28Mhz
advantage: small area
disadvantage: higher power consumption
I am now making a module consisting of a det and a set FSM, but I am
not sure whether I am making the best choice.
Every advice would be highly appreciated.
Best Regards,
Yuqing Youth

What is your design actually doing? And is an FPGA actually the correct
solution? When you are talking about relatively low frequencies, and
very low power requirements, you might be better off using a
microcontroller - depending of course on what the data is, and what you
are trying to do with it.

 

int19h wrote:

Flip-flop count,
I/O count (including required standards including bidirectional LVDS,)
gigabit serial I/O.
on-chip memory (width and depth),
multipliers/accumulators,
potential need for an on-chip microcontroller.

That seems like a very reasonable approach. Thanks Peter.

yep, a reasonable approach to writing your proposal to be X vendor
locked.

Your customer may not be high enough up the food chain to get delivery
of
the product in a shortage, and doing a design specifically including
sole
sourced technology that goes on allocation is called Chapter 7.

First, consider each of these functions carefully, are they a MUST HAVE
for
the product, and if so are there two vendors with parts that fit the
bill. If they
are MUST HAVE, do they need to be on chip ... would a multi-device
design
be safer for the product. Is the talent to actually complete the
project inhouse
already, or is it a specialized field that you may not be able to hire
to meet
schedule.

The basic question about FPGA's, is there enough LUT/FF's to realize
the
design. Everything past that, needs to be carefully considered in
regards
to multi-source availablity should there be high demand and allocation
for
the parts.

 

[hutzelbutz]

Back to the problem:

I think I forgot to mention that I am running the tools on dual-core
machines, which seems to be part of the problem.
When I watch the _pn processes while starting in "top", I see that with
one call of ise, there are two _pn started on the same CPU. One has a
bit of CPU usage for a short time, the splash screen shows and then
they both stand with 0.1 % CPU. After 4 Minutes, one _pn is moved to
the other CPU and this process then takes 1% CPU. 10 seconds later the
GUI is there. Still both processes take exactly the same amount of
memory and live happily ever after.

I don't know enough about multi-processor load distribution in Linux,
but this behavior is reproducable. Could it be that those 4 minutes
come from the time, the OS needs to find out that one process should be
switched to the other CPU???

I would be curious to hear the experts about this topic!

Cheers,
Joachim

 

[yyqonline]

Thanks!
At the end we will implement our design to a chip by asic tech, and now
we are designing and verifying via Fpga.
That is why the freq and power are always on our list.
Best Regards,
YuQing Youth

 

[Jim Granville]

Kevin Morris wrote:

I'm finishing up an FPGA Journal article called "Stop. Go. Yield. -
Dude! Where's my Chip?"

Hmm.. Not a title that travels internationally very well...
-jg

 

[GEO]

I got a reply back from Xilinx, it turns out that they are making a
DVD available soon ( from the download page ). But no hope on getting
a splitted download!

I juest happened to visit QuickWorks (Quicklogic) download page, they
nicely put a install.bat, p1,p2,p3,p4 (77MB x 4files).

 

[Philip Freidin]

On Wed, 25 Jan 2006 12:38:18 +1100, "int19h" <tirath@replacethispartwithmynickname.com> wrote:

Hi all,

I need some advice on how to treat the "equivalent gate count" issue. I have
to make a presentation on something soon, where FPGAs are the initial
foundation of the project, and I anticipate having to provide some
correlation between "slices" and "gates" as an estimate to the capacity of
current-generation FPGAs.

Ideally I would provide a slice and logic area estimate for the specific
design, but the design is not nearly complete enough to provide such
reliable estimates. For now, I have to arm-wave it. I don't need it to be
vendor-neutral though, I can be Xilinx specific. Any suggestions anyone?

-int

Since you don't mind being Xilinx specific, the following link:

http://www.fpga-faq.org/compare/build_form.cgi

may be of some help, as it allows comparisons of different devices,
and different product families, it does not have the insane Xilinx
logic cell inflation factor, it gives the formulas for converting
from LUTs/FFs to vendor neutral "Dog Gates" (sort of like Dog Years .


Philip



===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG

 

[Ron Huizen]

Austin,

Sorry if I didn't make it clear - the board already exists and provides a
2.5V supply to the XO, so while LVDS is LVDS, it does matter to us what the
supply voltage is. We could hack up the board to change the supply voltage,
but would rather not. That's why we want a drop in replacement for the
Epson.

The first issue is finding one with extended temperature (we can do that)
but the problem we have is figuring out in advance if the XO performance
will be good enough for the V2Pro's MGTs. Do you have any performance
requirement specs for the XO used for the MGTs that we could use in this
search?

My reason for coming to the group was to find a part others have used with
success

---
Ron


"Austin Lesea" <austin@xilinx.com> wrote in message
news:dr8j0r$igb6@xco-news.xilinx.com...

Ron,

Look for an LVDS output oscillator.

Then the matter of supply voltage does not matter.

LVDS is LVDS: does not matter if it runs off of 2.5V, or 3.3V.

Austin

Ron Huizen wrote:

Does anyone have experience using any oscillators for the MGTs on the
V2Pro other than the two listed in Xilinx's app note (Epson and
Pletronics)?

We've always used the Epson part (100, 125, or 156.25 MHz) in the past
but now need an extended temp version which they don't have, and
unfortunately the Pletronics part, which does have an extended temp
version, has a 3.3V supply instead of the 2.5 supply like the Epson.

Ideally, we want a drop in for the Epson, which is a 6 pin 5x7 package,
pin 1 enable, 2.5V supply. Issues or concern are termination and jitter.

------------
Ron Huizen
BittWare

 

[Brian Drummond]

On 25 Jan 2006 17:32:26 -0800, "Paul Marciano" <pm940@yahoo.com> wrote:

John Adair wrote:
You might want to have a look at our product Raggedstone1. It has the much
larger XC3S400-4FG456C part fitted. Programming cable is included and card
can be used in a PCI slot or stand-alone with the optional PCI I/O Header.
Details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html.

As a learner and experimenter I like the look of that board, but how
much does the Xilinx PCI core for the Spartan 3 cost?

The Xilinx core ... a lot ($1995 for a single project license)
But keep watch for an announcement from John A. in the near future...

- Brian

 

[rickman]

fpga_toys@yahoo.com wrote:

austin wrote:
They weave a web of untruths and half whispers with convenient
coincidences to explain their troubles.

Xilinx's ommissions and the quest for that data is not a cultish
movement.
....snip...
This is not a regligous debate ... this is real engineering up front
for worst
case loads, not tinking in the lab with missguided retrofit cooling.

If I were you, I wouldn't worry too much about Austin. He is pretty
knowledgeable techincally even if his work with the customer leaves
something to be desired. I will say that with some of the stuff that
Austin posts, you would think he was a conspiracy theorist.

You have posted your concerns and have gotten some responses. The
resonse from X seems to be a lot like the way they responded to the
data sheet LC count issue in the past. You are not likely to get
anything further out of them at this point. As you post more you just
feed the trolls (or become one).