EDK : FSL macros defined by Xilinx are wrong

[hutzelbutz]

sure, I know about all those scripting and makefile advantages, there
have been enough wars on that. However, I _do_ like graphical user
interfaces and once everything is set up, I can press one button to run
the complete designflow over and over again... Some people like one,
some the other, no worries, everybody is free.
So thanks for your suggestion but I am not looking for a workaround but
a real fix of the ISE GUI.

 

[Anonymous]

Doesn't the ml403 come with a Linux distribution? Why would you need to port
anything?

"ramesh" <ramesh@embeyond.com> wrote in message
news:1138173378.715130.86900@g43g2000cwa.googlegroups.com...

Hi All,
Iam new to xilinx platfrom.

I was trying to port open source linux on Ml403 board. i tried to
follow the instructions in the below link.
http://www.klingauf.de/v2p/index.phtml
i was getting errors when i was running bZimage. the .elf file was not
getting created.

Is there an alternative way of acheiving my goal.
Kindly suggest.
Thanks in advance.

Ramesh

 

[Anonymous]

Try a google search on scatter gather dma.

I don't know the details but I know you have to allocate blocks of memory in
the pc space, program their locations and sizes to the pci, and then monitor
the transfers and swap out buffers to disk before their overwritten.

"Nitesh" <nitesh.guinde@gmail.com> wrote in message
news:1138169559.651307.267740@o13g2000cwo.googlegroups.com...

I changed the front end core given by amirix for dma functionality.
For a dma transfer what is the destination address that I should
specify? How can I get this address.
I am sending data from the card to the host memory.
Nitesh

 

[Ray Andraka]

Jim Granville wrote:

Peter Alfke wrote:

The circuit is reliable, although the generated pulse width is
determined by gate delays. But it is self-compensating, since the clock
pulse will not end until the flip-flop has toggled.

This circuit really shouldn't be advocated for FPGA use. It is an
asynchronous hack. It would not get through a serious design review
except in extenuating circumstances. Generally speaking, depending on
gate delays for circuit operation is bad practice. This particular
circuit has potential problems with pulse width and is dependent on the
clock duty cycle for proper operation. (Yes, I can remember using it a
long long time ago with some TTL designs, but then those designs also
had one-shots in them). Another problem with it, is the static timing
analyzer and timing driven place and route do not consider the
asynchronous behavior of this circuit.

 

[Antti Lukats]

<Chris.Gammell@gmail.com> schrieb im Newsbeitrag
news:1138199130.162720.321920@g44g2000cwa.googlegroups.com...

Hey All,

Just wondering if anyone has tried out the Spartan-3 starter board
offered on Xilinx's website (the 99 dollar one). I am a student
developing a project on an FPGA and that seemed like the most cost
effective option for me. Has anyone tried it? If so, how is the
speed/capacity for your needs? How about the simplified JTAG interface,
does that perform OK? Thanks in advance and I look forward to hearing
from you.

Chris

its ok,

but if you can wait then the Spartan3e kit $149 USD includes also on board
Platform USB Cable (sold standalone for $149!) as free bonus


--
Antti Lukats
http://www.xilant.com

 

[yyqonline]

\quote
Ray Andraka wrote
This circuit really shouldn't be advocated for FPGA use.
\quote
Thanks for help.
I am not sure how to realize the same function (double the frequence of
the clk)?
Maybe some of the FPGA's architecture support this.
Then I would like to know how this circuit perform as far as asic is
concerned?

 

[Eli Hughes]

Antti Lukats wrote:

Chris.Gammell@gmail.com> schrieb im Newsbeitrag
news:1138199130.162720.321920@g44g2000cwa.googlegroups.com...

Hey All,

Just wondering if anyone has tried out the Spartan-3 starter board
offered on Xilinx's website (the 99 dollar one). I am a student
developing a project on an FPGA and that seemed like the most cost
effective option for me. Has anyone tried it? If so, how is the
speed/capacity for your needs? How about the simplified JTAG interface,
does that perform OK? Thanks in advance and I look forward to hearing
from you.

Chris


its ok,
but if you can wait then the Spartan3e kit $149 USD includes also on board
Platform USB Cable (sold standalone for $149!) as free bonus

If you are a student you may be able to get Xilinx to donate a couple to
your Lab at School!

-Eli

 

[John Adair]

Chris

You might want to have a look at our product Raggedstone1. It has the much
larger XC3S400-4FG456C part fitted. Programming cable is included and card
can be used in a PCI slot or stand-alone with the optional PCI I/O Header.
Details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development
Board.
http://www.enterpoint.co.uk

<Chris.Gammell@gmail.com> wrote in message
news:1138199130.162720.321920@g44g2000cwa.googlegroups.com...

Hey All,

Just wondering if anyone has tried out the Spartan-3 starter board
offered on Xilinx's website (the 99 dollar one). I am a student
developing a project on an FPGA and that seemed like the most cost
effective option for me. Has anyone tried it? If so, how is the
speed/capacity for your needs? How about the simplified JTAG interface,
does that perform OK? Thanks in advance and I look forward to hearing
from you.

Chris

 

[Ray Andraka]

fpga_toys@yahoo.com wrote:

you are not the only one that is suggesting that derating Xilinx parts
50% is the minimum rational target for an RTL based RC system on
those platforms. I don't think this is acceptable long term, and very
hard to justify. That Xilinx actively prevents alternative P&R and bit
stream tools to improve an this, simply means they are not interested
in better fit for their product line ... IE go away, we don't care
about
that market.

Thanks for clearly expressing this.

Why is it so hard to justify. One could argue that you can't use 100%
of a microprocessor either. Any given instruction leaves part of the
microprocessor idle: it is impossible to use all of the features all of
the time. Why should you have different expectations of an FPGA? As I
pointed out before, you can get to the high utilization and high
performance corner, but you are not likely to get there while also
pushing the fast to compile and easy to use buttons. FPGA design, at
the core is digital logic design no matter how many fancy tools you
throw at it.

The fact of the matter is that FPGAs offer many more degrees of freedom
in the design than what is offered by a conventional computer. The
added degrees of freedom make them very powerful for efficient
processing, but it also means that the design space has more things to
trade-off to get to a particular corner of the design space (not to
mention more ways to approach a particular problem which makes it harder
for automated construction). Getting into the density and performance
corners requires more design effort. No amount of wishing is going to
change that fact. Designing to hit the high performance and high density
corners is possible, but it isn't likely to happen when trying to also
stay in the minimal effort and fast time to compile corners.

If you want to call that de-rating the FPGA, that's your perogative. I
don't see it as de-rating the FPGA, as the FPGA can and does meet the
performance and density you are seeking, but at the price of design
effort. That is not de-rating, that is weighing the design trade-offs.
If you want to play in a particular corner, you need to make the
concessions to get you there. You can't cover all the corners at once,
and that certainly isn't unique to FPGA design. Which do you want more:
fast compile times, ease of use, performance, density? You can
reasonably get two of these, any more than that is not going to get you
into the corner.

 

Andy Peters wrote:

I fail to understand how, as an FPGA application, "reconfigurable
computing" is somehow different (more resource intensive, more "high
performance," whatever) from an "application-specific" FPGA design.

After all, every FPGA engineer wants the best of everything:
lowest-cost part (which implies smallest/least amount of logic/best use
of resources), lowest power dissipation and of course the least amount
of engineering effort to meet those goals!

In two ways ... it will be one to three orders of magnitude larger than
a hand written hardware design, and as such will not benefit normally
from low level optimization, placement, packing, routing enhancements
that a typical hardware design will get. It WILL depend on the tools
to do a better than average fit automatically.

Second the life of an RC design will frequently be very short, and will
evolve. Hardware designs tend to live "forever" from a typical software
perspective ... as such hardware designs have a very strong incentive
to invest manual labor up front to get the best fit to hardware for
cost management .... that labor cost will then be amortized over the
life of many units. A typical RC program will have a total life span a
fraction of that, and is not likely to be frozen in time with large
scale hardware shipments so there is no large incentive to invest
effort toward optimizing a particular RC applicaion on hardware. There
is EVERY incentive to optimize tools to do a better job at hardware
fit, as those tools will have a long life and the effort amortizedf
over MANY RC applications.

The same argument, in analogy, is very few people invest the effort to
hand optimize assembly language fit for applications ... but it is
worth putting effort into optimizing the tool chain ... compilers, etc
until diminishing returns is reached.

Other than that, gates are gates.

 

[Austin Lesea]

Ron,

Look for an LVDS output oscillator.

Then the matter of supply voltage does not matter.

LVDS is LVDS: does not matter if it runs off of 2.5V, or 3.3V.

Austin

Ron Huizen wrote:

Does anyone have experience using any oscillators for the MGTs on the V2Pro
other than the two listed in Xilinx's app note (Epson and Pletronics)?

We've always used the Epson part (100, 125, or 156.25 MHz) in the past but
now need an extended temp version which they don't have, and unfortunately
the Pletronics part, which does have an extended temp version, has a 3.3V
supply instead of the 2.5 supply like the Epson.

Ideally, we want a drop in for the Epson, which is a 6 pin 5x7 package, pin
1 enable, 2.5V supply. Issues or concern are termination and jitter.

------------
Ron Huizen
BittWare

 

[Bob Perlman]

Hi -

I kind of like a DDR FF emulation circuit that Gabor described in a
post last May; see the drawing below (please view with fixed-width
fonts). You use two D FFs and three XORs to create the function of a
FF that clocks on both edges. The extra gates at the inputs and
outputs mean that the setup time and CP-to-Q delays suffer somewhat,
but the Q output is glitch-free.



-----------------------.
| |
| __ |
'-\\ \ .--o--. |
|| |------|D S Q'-o-)--.
.--//_/ | | | | |
| .----|> | | | |
| | | R Q| | | |
| | '--o--' | | | __
DIN ------o | | | '--\\ \
| | | | || |- Q
CLK ------)--------o | | ---//_/
| __ | | | |
'--\\ \ | .--o--. | | |
|| |-)----|D S Q'-)-o--'
-//_/ | | | |
| '---o|> | |
| | R Q| |
| '--o--' |
| |
'--------------------'

Me, if my circuit were operating at low speed, I'd probably just use a
2X clock. And I agree with Symon that gating the clock line is
something you do only if you have no other choice, and then only if
you understand the implications (I'm sure Peter understands them, but
those new to design may not).

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com
and
http://www.sonic.net/~bobperl/blogger/2006/01/clock-gating-just-say-no.html

 

[Eric Smith]

hutzelbutz wrote:

However, I _do_ like graphical user
interfaces and once everything is set up, I can press one button to run
the complete designflow over and over again... Some people like one,
some the other, no worries, everybody is free.

I agree.

For my own part, I like the commadn line interface. Once everything is
set up, I can type "make", press return, and run the complete designflow
over and over again. I find it faster and more convenient to type
"make" than to mouse to a button. But that's a matter of personal taste.

 

[Jeff]

Hi John,

I guess it's a matter of tradeoffs: $9 cheaper, but the S3 board has
more switches, a VGA output, a serial output, and an PS/2 port.

And shipping Raggedstone1 to the US is $45.

-Jeff

 

[Eric Smith]

yyqonline wrote:

I am not sure how to realize the same function (double the frequence of
the clk)?
Maybe some of the FPGA's architecture support this.
Then I would like to know how this circuit perform as far as asic is
concerned?

That's exactly where I'd expect to run into problems. It's not too
difficult to characterize it in a particular FPGA, but the performance in
the FPGA tells you almost nothing about what to expect in an ASIC.

Using asynchronous logic in an FPGA leads to trouble, and doing it then
expecting it to work the same in an ASIC could lead to a disaster.

As others have suggested, unless your transition rate is extremely fast,
you're much better off using a clock at a higher rate, a synchronizer
(two chained FFs), another FF, and an XOR between the D and Q of that
last FF. That will get you a pulse with a width of one clock cycle
every time the input transistions.

 

[Eric Smith]

Chris.Gammell@gmail.com writes:

Just wondering if anyone has tried out the Spartan-3 starter board
offered on Xilinx's website (the 99 dollar one).

Yes. It's quite a good value.

If so, how is the speed/capacity for your needs?

For my needs, it was fast enough, and the size of the part was sufficient
for a lot of the things I do. I ended up buying the same board with a
larger chip (XC3S1000) from Digilent for $150 in order to fit a few of
my largest projects.

How about the simplified JTAG interface, does that perform OK?

I'm not sure what's "simplified" about it, but the supplied cable
(equivalent to a Xilinx Parallel Cable III) works just fine.

Eric

 

[John Adair]

I'll admit shipping is an issue and we have brought it down a lot based on
the numbers we are moving we now have much better rates to us from our
courier. That shipping is usually next day if we get an order early in the
UK day. We may be able to extend the low cost ship that we use in Europe to
US but as yet we don't know what issues we might have in customs clearance.
But if guys in the US buy more well it might get a lot better. After all the
large players in distribution like DIGI-KEY ship to us for free on orders
over $180. A bit ironic as we end up shipping a lot of the parts back on a
board to the US more often than not.

Out interest what does a typical US distributor charge for carriage?

The functionality bits differences are now mainly covered by our add-on
modules. We are putting together a competative bundles of modules that will
be announced soon. They will be extra but you still get better value in my
opinion with our bundles. Website photos of the first modules to be released
have been done and should appear on our website in the next couple of days.
Some pricing too.

Another thing worth mentioning is that if a group of students, or college,
get together they can buy a UAP pack of 5,10,20 etc boards at discount of
any of our products including the Raggedstone1. The Raggedstone1 specials
(XC3S1000,XC3S1500, XC3S2000) will also be made available under this program
too TBA. They won't be released otherwise than in bulk buys from strategic
customer or in our forthcoming competitions. Also carriage on group buys
drops the unit carriage effectively by a lot when spread over say 5 units
which is about US$70-80 from my rusty memory so worth doing. We are
considering having a US distributor, or division, to handle the level of
sales we have in your area but that is probably a while off yet.

John Adair
Enterpoint Ltd. - Home of UAP - University Access Program.
http://www.enterpoint.co.uk


"Jeff" <jeff.ward@gmail.com> wrote in message
news:1138219349.466762.179790@g14g2000cwa.googlegroups.com...

Hi John,

I guess it's a matter of tradeoffs: $9 cheaper, but the S3 board has
more switches, a VGA output, a serial output, and an PS/2 port.

And shipping Raggedstone1 to the US is $45.

-Jeff

 

[Steve Knapp (Xilinx Spart]

I won't comment on the usefulness of the board, as I'm highly biased.


Just FYI, the Spartan-3 Starter Kit is now bundled with the CPLD Design
Kit for $99.
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3-CPLD-DK

IMHO, for new FPGA or CPLD users or those new to digital design, this
bundle is fairly easy to use. The FPGA board includes easy-to-use
asynchronous SRAM.

There is a more advanced board, the Spartan-3E Starter Kit Board, for
$149 that includes DDR SDRAM, parallel Flash, SPI serial Flash, etc.
However, it is also more difficult to use for new users. This board is
primarily targetted to more advanced designs and to embedded processor
(i.e. MicroBlaze) applications.
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US

There are also a variety of Spartan-3/-3E boards provided by
third-party companies. Depending on your application needs or
interests, one of these boards may include other interfaces or
capabilities that you want. Take a look also at the following list,
although I'm sure that it does not include all the various vendors.
http://www.xilinx.com/xlnx/xebiz/productview.jsp?category=-21488

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

 

[Mike Harrison]

On 25 Jan 2006 12:02:29 -0800, "Jeff" <jeff.ward@gmail.com> wrote:

Hi John,

I guess it's a matter of tradeoffs: $9 cheaper, but the S3 board has
more switches, a VGA output, a serial output, and an PS/2 port.

On a recent project I found the 8 big (i.e. not DIP) switches on the S3 starter board REALLY useful,
for selecting 1 of n different sets of debug outputs to a set of pins connected to the scope, and
also to select one of n signals to display on the seven-seg display. Saves a lot of recompiles to
add debug functions to look at different internal states if you can have them all available at the
flick of a switch...!

 

[Ed McGettigan]

fpga_toys@yahoo.com wrote:

I should probably note that Xilinx leaches a hell of a lot of value off
open source by using Linux as a host platform for it's tools, GCC as
the main production compiler for PPC core software, GNU for the
libraries for PPC, and Linux in several forms as host operating systems
for it's product offerings.

It's probably worth writing Austin, Peter, and the other regular usenet
posters from Xilinx and making it clear just how much Xilinx benefits
from open source, the Xilinx market created by open source, and the
developers which frequently volunteer their time supporting Xilinx open
source use.

I take umbrage to your assertion that Xilinx is a leach and doesn't
contribute back to the open source communities. Xilinx has been a
contributing Corporate Patron of Free Software Foundation for many
years now https://www.fsf.org/donate/patron/index_html funding many
open source projects through the FSF with our donations.

In addition we funded, supported and developed the Virtex-II Pro and
Virtex-4 PowerPC405 ports that are the parent post of this thread and
then push for their release into the official Linux 2.4.x and 2.6.x
PowerPC trees so that everyone will have access to them easily.

Ed McGettigan
--
Xilinx Inc.