EDK : FSL macros defined by Xilinx are wrong

On a sunny day (Tue, 25 Oct 2005 20:54:32 -0500) it happened "Steven J. Hill"
<sjhill@realitydiluted.com> wrote in <435EE1D8.5080205@realitydiluted.com>:

Eric Smith wrote:
Thirty hour and several hundred dollars later, it's working great. Details in my
blog entry:
http://whats.all.this.brouhaha.com/?p=149

The only thing I did not see you try, which I am going to try next is
using Wine on my dual Opteron system to see if things will work.
There is a new Wine-0.9 now on www.winehq.com
Click to expand...
Have downloaded source, but had no time to play with it yet.

_________________________________________
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I have little bit of experience..let me know what exactly do u need...

--
Parag Beeraka
 
Have you ever looked at implementing the state machine in a ROM =
BlockRAM?
You can have hundreds of states and still run at several hundred MHz.
Pick a ROM size, feed part of the outputs directly back as inputs
(remember, theBlockRAM is synchronous!) and add the condition inputs to
the addresses.
For exmple: 1K x 16 with 7 outputs fed back gives you 128 states with 3
additional inputs that can encode the jump condition at each state. You
can conditionally (8-way) jump from anywhere to anywhere, without any
restrictions. And you still have 9 freely assignable outputs for each
state. Runs at 200 MHz+.
Peter Alfke, Xilinx Applications
 
Ashwin, I suppose English is not your native language. Otherwise you
would know that "request" is a very strong word, kind of like
"command", used only by a superior (or an unfriendly institution).
Adding "would" and "please" does not eliminate the air of arrogance...
Of course, you did it out of lack of knowledge.
Peter
 
Ashwin, I suppose English is not your native language. Otherwise you
would know that "request" is a very strong word, kind of like
"command", used only by a superior (or an unfriendly institution).
Adding "would" and "please" does not eliminate the air of arrogance...
Of course, you did it out of lack of knowledge.
Peter
 
"Kunal" <kunal.shenoy@gmail.com> schrieb im Newsbeitrag
news:1130392414.325117.45550@g49g2000cwa.googlegroups.com...
Both Xilinx and Altera has options to move to ASIC-like implementations
from FPGA designs. These chips have a lower unit cost.

Xilinx calls it EasyPath Solution :
http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm
.
Altera calls it Hardcopy
http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp
Click to expand...
Xilinx has NO ASIC solutions. The Easypath is an normal FPGA with less
testing at the fab. may be atually partially faulty. its only tested to
customer bitstream. But the silicon is 1:1 the same as the normal FPGA

antti
 
Hi David
Th
is is for an RGB LED demo display application.

1. There will be mixing of colours done at say 3ms intervals for each colour
to stay ithin the 10ms and take avantage of persistance of vision.
2. Bits accuracy in the duty cycle is not very important since the PWM is
only for brightness control.
3. The outputs must at least be synchronized to the colour mixing intervals,
i.e. 3ms intervals. In other words, the PWM will further divide the 3ms
intervals to control brightness.
4. These will only be used in an RGB LED display application hence the only
real importance is the 10ms refresh limit.

Thank you for your input.
Peter.

"David Brooks" <davebXXX@iinet.net.au> wrote in message
news:435d7280$0$8621$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
Can you further tell us:
1. What pulse repetition frequency you want
2. How many bits accuracy in the duty cycle
3. Must the outputs be synchronised?
4. Are they to drive model-control servos? (Those often respond not to the
average energy in the signal, but to the actual width. You can have a very
long interval between pulses, & still have them work).

Emtech wrote:
I have an application where I need to implement 24 or up to 32 PWM
outputs (8-bit) and
am considering using a small CPLD to handle the PWMs instead of doing it
all in software.
This does add a CPLD to the design, but frees the micro do to other
things.

Any recommendations on the CPLD & CPLD size without completing the VHDL
first?
Click to expand...
 
I was always told not to use complicated C-style coding techniques.
Simpler styles generally results into better designs. Atleast, this is
what my instructor used to say. And he's one of the best in this field!

- Robert.
 
- As for the Block RAM - the SM can not fit in it as the device I am
using does not have enough of it:
synthesis report from XST: (not enough BRAM in this device).
But even then the SM is not fast enough.

- I have only 2 inferred Adders/Subtractors - I will see how i can
change them.

- Another thing -i have the following concurrent statement
sig1 <= '1' WHEN a=b else '0';
sig2 <= '1' WHEN c=d else '0';
sig1/2 are input of the SM. a,b,c,d are 13 bit values. Is this a
problem for 100Mhz (my target freq.).

- I thing that the high number of IF-ELSIF-ELSIF...-ELSE within a
single WHEN xxx =>
can be the reason.
 
Can you send me an e-mail, so we can discuss this privately?
Peter Alfke (peter@xilinx.com )
 
OK. Fair enough. And you could use SystemACE to do all that except for
programming the CPLD. Why use a CPLD and not just a small, cheap FPGA
like a Spartan3 or a variant?


Benjamin Todd wrote:
As also indicated, an interesting question to ask is why do you want to
configure your CPLD every time you power up? Is your design pattern
changing all the time? Is this some sort of demo board?


Not exactly, maybe i'm being a little ambitious...

I'm just doing some research into making a test apparatus for some designs
using various CPLDs. The idea was to make a discrete piece of hardware that
the UUT would be plugged into, and then a little report saying whether it
passes or fails - this needs to be rugged, and industrialised.

Using boundary scan I can only verify about half the board, and the less
critical half at that, so i'm wondering whether I could use one bit file to
run a sequence of test vectors in conjunction with the external tester, and
then once all the interconnects are established as correct, load the proper
bit file.

I guess you're wondering why I don't just go for a PC running impact... well
i'm trying to avoid having to maintain a PC with the manufacturer, including
the OS, the test software etc etc.

Ben
Click to expand...
 
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:436124b3$1@clear.net.nz...
Antti Lukats wrote:
NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but
rather asic with part of it as configurable fpga fabric.

Cypress is also out of PLD business silently, well that was to be
expected.

humm, who is next?

Yes, but ST has entered the fray, with new partial FPGA offerings, that
seem well thought out.
I did smile when I read one press release, that said they have two
versions of their eval boards, one that allowed an external FPGA to
develop, and then use their internal one.
A good idea, and usefull to the developer, but perhaps more indicative
of a Tool Flow that's just a little green, perhaps ?
Those issues improve over time.

-jg

hum, where did you find this?
Click to expand...
i am also looking at STW22000 news all the time, but its seems kinda
vaporware or at least not obtainable ?

antti
 
Paul,

In all fairness to the people who bring this up (over and over again),
is the "fear" that a defect will "develop" or "migrate" or somehow cause
a further problem.

That is what process qualification testing is all about. You take the
parts that you claim are good for 10, 15, or 20 years, and you test them
under commonly accepted conditions to see if you are right.

Every IC manufacturer out there does this.

If we pass XXXX? temp cycles, at YYYY? higher Vcc's, then there are
formuals which predict what the worst case failure rate will be. If you
have even one failure, the process is reset, corrective actions are
made, and you start the test again on the new corrected process parts.

This is not new at all, but something we have all done for years.

Yet, the fear, although irrational (as it applies to every device made
in silicon, ever), seems to resonate with people who really don't know
"what goes on under the hood."

For some, it is like making sausage, you really don't want to know how
it is done.

For others, once you know how it is done, you know the right questions
to ask: "Did your EasyPath program go through a standard qual process?"

Answer: "Yes, it did."

Austin
 
Cypress is also out of PLD business silently, well that was to be expected.
Click to expand...
Who is in the PLD business these days? Anybody still making 22V10s as
compared to CPLDs?

How about smaller parts? Are things like 20R8s pad limited now?

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Hal Murray wrote:
Cypress is also out of PLD business silently, well that was to be expected.


Who is in the PLD business these days? Anybody still making 22V10s as
compared to CPLDs?
Click to expand...
Yes, Atmel and ICT ( now Anachip ), and also Lattice and in phase-out
Cypress. Lattice do an ISP version of the venerable 22V10.
We still use 16V8s, which are actually the lowest cost PLDs
( in spite of the marketdroid claims from Altera...)

How about smaller parts? Are things like 20R8s pad limited now?
Click to expand...
Nope, they have not changed the die design on the smaller parts in
a long time.

To try and cover a little of the SPLD area, Xilinx did add MLF packages
to the coolrunner, [ but that is dual-voltage, and low Vcc only, so
there are some areas it cannot be applied to].

These pacakges also do not show yet on the Xilinx store....
-jg
 
Antti Lukats wrote:

"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:436124b3$1@clear.net.nz...

Antti Lukats wrote:

NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but
rather asic with part of it as configurable fpga fabric.

Cypress is also out of PLD business silently, well that was to be
expected.

humm, who is next?

Yes, but ST has entered the fray, with new partial FPGA offerings, that
seem well thought out.
I did smile when I read one press release, that said they have two
versions of their eval boards, one that allowed an external FPGA to
develop, and then use their internal one.
A good idea, and usefull to the developer, but perhaps more indicative
of a Tool Flow that's just a little green, perhaps ?
Those issues improve over time.

-jg


hum, where did you find this?
i am also looking at STW22000 news all the time, but its seems kinda
vaporware or at least not obtainable ?

antti
Click to expand...
Antti,
Here is the link
http://www.st.com/stonline/press/news/year2005/p1711p.htm

ST seem to have two branches of ARM+FPGA, this one they call SPEAr,
and they claim samples now, Eval PCBs in Dec....
Price of $12/Volume, 200K FPGA, ADC, 3 x HS-USB(!), Ethernet,
SDRAM and I think SPI-SerialFlash boot ?

-jg
 
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:43613aad@clear.net.nz...
Antti Lukats wrote:

"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:436124b3$1@clear.net.nz...

Antti Lukats wrote:

NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but
rather asic with part of it as configurable fpga fabric.

Cypress is also out of PLD business silently, well that was to be
expected.

humm, who is next?

Yes, but ST has entered the fray, with new partial FPGA offerings, that
seem well thought out.
I did smile when I read one press release, that said they have two
versions of their eval boards, one that allowed an external FPGA to
develop, and then use their internal one.
A good idea, and usefull to the developer, but perhaps more indicative
of a Tool Flow that's just a little green, perhaps ?
Those issues improve over time.

-jg


hum, where did you find this?
i am also looking at STW22000 news all the time, but its seems kinda
vaporware or at least not obtainable ?

antti

Antti,
Here is the link
http://www.st.com/stonline/press/news/year2005/p1711p.htm

ST seem to have two branches of ARM+FPGA, this one they call SPEAr,
and they claim samples now, Eval PCBs in Dec....
Price of $12/Volume, 200K FPGA, ADC, 3 x HS-USB(!), Ethernet,
SDRAM and I think SPI-SerialFlash boot ?

-jg

read carefully - the SPEAr is customized eAsic.
Click to expand...
the fabric is e-beam programmed.

antti
 
There are many ways to implement this, at your extremely low rate even
more than many.
But if the present state needs to be stored, you need 256 storage
elements on-chip, and that makes a CPLD rather expensive.
The smallest FPGA does this job hands down.
Your job is expensive in a CPLD, trivial in any FPGA.
If you only want to make one demonstrator, buy an FPGA eval board, and
finish the job in no time.

Peter Alfke
 
Antti Lukats wrote:
hum, where did you find this?
i am also looking at STW22000 news all the time, but its seems kinda
vaporware or at least not obtainable ?

antti

Antti,
Here is the link
http://www.st.com/stonline/press/news/year2005/p1711p.htm

ST seem to have two branches of ARM+FPGA, this one they call SPEAr,
and they claim samples now, Eval PCBs in Dec....
Price of $12/Volume, 200K FPGA, ADC, 3 x HS-USB(!), Ethernet,
SDRAM and I think SPI-SerialFlash boot ?

-jg


read carefully - the SPEAr is customized eAsic.
the fabric is e-beam programmed.
Click to expand...
Well, seems you are right, but one needs to go three layers down.

The marketdroid that wrote the link above, decided eBEAM
might scare off some customers, so better to use words
like "configurable logic" & "unprecedented flexibility and time to market".

You have to go deeper into the lower pages, and voila,
words like NRE and eBEAM start to appear.

Next questions most customers will ask, is what exaclty is 'low NRE',
and what volumes does this approach really kick-in at ?

-jg
 
Bob wrote:

How much does it cost to produce an ASIC? This is for a
simple customized 8-bit CPU and 64KB of on-chip RAM.


If you can do your own design, it can be a lot cheaper than the figures
Click to expand...
in some of your replies. We are doing a very tough mixed signal chip
with MOSIS, and the base price for the process we are using is about
$6000. I'm guessing that you might be able to cram that logic into the
minimum chip size (about 16 mm ^2, I think.) Our chip is about 7 x 7 mm,
and runs more than the minimum. The tough stuff is the design and mask
costs, once they are right, the chips are cheap.

If it is already working in an FPGA, can I count on the
ASIC also working?


If you roll your own, then success depends on how good and careful you are.
Click to expand...

Jon
Click to expand...
 
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