EDK : FSL macros defined by Xilinx are wrong

[Phil Hays]

Gert Baars wrote:

I am experienced with Electronics and programming but never had anything
to do with FPGA. I want to start with an FPGA from Altera and have
installed their Quartus II.
Now my guess is I have to learn a language like VHDL or Verilog. What
language is easiest/fastest to learn or what other programming-language
can you recommend?

VHDL.

Having said that, there is almost as strong of case for Verilog. VHDL
is somewhat harder to learn the basics of, and Verilog is harder to
master. The area under the learning curves is similar. There have
been religious wars over this in the past. At minimum, learning how
to read both is good.

One hint, don't think of it as programming. You are specifying
hardware. Try to work out what hardware will implement what you write
as you write it.


--
Phil Hays to reply solve: phil_hays at not(coldmail) dot com
If not cold then hot

 

[CMOS]

no, i've connected them according to what you've mentioned. But
translation error is still there.
CMOS

 

[young]

I have recoded a xilinx reference of UART and tested it in VIRTEX
II.The reference is in VHDL.And It can reach 115K when communication
with PC. If you interested it, you can contact me at
zhang.young@gmail.com.

 

[Antti Lukats]

"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch>
schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch...

I know this isn't exactly comp.arch.cpld...

does anyone know of a COTS solution for programming a (Xilinx) CPLD
without
using PC + Windows + Impact etc etc. (a stand alone chunk of hardware with
a
way for me to give it a set of bit files and a Program button would be
nice)

I want to load one bit-file into a device to run a test, then once the
test
is finished load a second bit-file - but i'm investigating a stand alone
solution not using a PC + Cable + Software etc etc.

Any pointers are welcome.
Thanks!
Ben
Benjamin TODD

Hi Ben,

as usually YES/NO.

1) if you badly want then you can use SystemACE to program PLDs in the way
you described. its not very reasonable but its sure is possible.

2) there is no direct COTS solution I think. you can use any small MCU to
re-configure the PLDs solutions for that exist.

reloading an PLD with test conf each time at power up isnt very nice thing
todo in generic. sure it depend on the PLD in use.

I think with machXO you have an option to load the flash or the PLD (what is
actually ram based)

antti

 

[fpgabuilder]

I started with vhdl and then saw communication industry shift to
verilog. Now I use verilog all the time. I find that there are more
resources dealing with verilog than vhdl. You mentioned you are
trying to start with altera devices, I notice that the newer design
examples and documentation on altera's website also uses verilog.

From a marketability standpoint - I see more job/contractor postings
that require verilog expertise than vhdl.

From language standpoint - I think both vhdl and verilog have made
strides towards ease of use with their latest standards. but you'll

have more fun with verilog once you master it.

Finally, to add to what others have said regarding thinking hardware -
do not choose verilog because it will let you write software like code.
For the best quality hardware it is imperative that you think hardware
when you are writing code...

-sanjay

 

[fpgabuilder]

I started with vhdl and then saw communication industry shift to
verilog. Now I use verilog all the time. I find that there are more
resources dealing with verilog than vhdl. You mentioned you are
trying to start with altera devices, I notice that the newer design
examples and documentation on altera's website also uses verilog.

From a marketability standpoint - I see more job/contractor postings
that require verilog expertise than vhdl.

From language standpoint - I think both vhdl and verilog have made
strides towards ease of use with their latest standards. but you'll

have more fun with verilog once you master it.

Finally, to add to what others have said regarding thinking hardware -
do not choose verilog because it will let you write software like code.
For the best quality hardware it is imperative that you think hardware
when you are writing code... or should I say describing hardware.

-sanjay

 

[fpgabuilder]

In addition, I like to always use binary notation after an arithmetic
operator. In past, I have seen different simulators behave differently
due to the way they may represent integers differently. I don't think
it is so much of a problem here. But things can get tricky if you are
addin negative nos or multiplying big nos.

overflow = overflow + 1 can be written as
overflow <= overflow + 1'b1

-sanjay

 

[Phil Hays]

"fpgabuilder" wrote:

From a marketability standpoint - I see more job/contractor postings
that require verilog expertise than vhdl.

Depends on location. For the USA as a whole, I just checked
Monster.com and found the following posted jobs:

113 hits for "fpga and verilog"
148 hits for "fpga and vhdl"

Looks to me like VHDL is still more popular.


--
Phil Hays to reply solve: phil_hays at not(coldmail) dot com
If not cold then hot

 

[fpgabuilder]

I stand corrected. Thanks for running that comparision.
-sanjay

 

[Peter Alfke]

If your 32 MHz clock is really derived from, and thus synchronous with,
the 128 MHz, then I would treat this as a synchronous FIFO.
Asynchronous means that you have no idea of, and no control over, the
phase relationship between the two clocks. And asynchronous FIFO
control is far trickier than synchronous, just because of the unknown
and shifting phase relationships, and the associated possible decoding
glitches and even metastability. Synchronism makes all this so much
easier.
Peter Alfke

 

[Kolja Sulimma]

Why does it not seem right that you as an author reserve at least a few
rights when giving most of your rights on a paper away for free to a
commercial publisher?

I think it is ridiculous that publisher ever demanded exclusive rights
without compensation. If you want to print conference proceedings you
can do that with nonexclusive rights.

And I am not the only one. A few years a ago a study was published that
showed, that papers that are available online for free are cited twice
as often as other papers.
As a result more and more authors refused to give away exclusive rights.
Universities made it their policy that the right to publish on the
university homepage must stay with the university.
http://www.nature.com/nature/focus/accessdebate/index.html

Publishers that did not want to play that game risked to lose conference
proceedings contracts. Most publishers now allow the author to keep the
right to publish on the authors webserver. This is a minimalisitc
compromise on the side of the authors.

O'reilly goes a large step further:
http://press.oreilly.com/pub/pr/1042

I suggest to every scientific author at least to try to retain the
rights for his work. Once your paper is accepted by a conference
committe, you get the copyright transferal from from the publisher with
a few weeks delay. Just refuse to sign it and send them a note that you
put the paper under a creative commons license.
I doubt that the publisher is going to explain to the conference chair
that they are not going to print your paper because they can not get
exclusive rights. After all you are offering them a full set of rights
for free.

Kolja Sulimma


Austin Lesea schrieb:

Kolja,

Interesting. I knew I could distribute it internally, but fram what you
say, it appears I may also publicly post it on the Xilinx web site
(external world)? That doesn't seem right to me...

Austin

Kolja Sulimma wrote:

Austin Lesea wrote:


Since we wrote this, IEEE owns the copyrights, and we can no longer
distribute the paper.



Not true. The IEEE copyright poolicy states that

"Upon transferring copyright to IEEE, authors and/or their companies
have the right to post their IEEE-copyrighted material on their own
servers without
permission, provided that the server displays a prominent notice
alerting readers to their obligations with respect to copyrighted
material and that the posted
work includes an IEEE copyright notice."

As Xilinx employees are authors and co-authors of quite a number of
papers, a collection - maybe on the XUP homepage - would be nice.

Kolja Sulimma

 

[Antti Lukats]

"Austin Franklin" <aus3tin@darkr00m.com> schrieb im Newsbeitrag
news:KIv7f.14466$xk2.151@fe06.lga...

Does anyone here have any experience with running Linux on the V2Pro?

Thanks,

Austin

I suppose quit a lot of people do. But what is what you need?

Antti

 

[Jan Panteltje]

On a sunny day (Tue, 25 Oct 2005 11:15:57 -0700) it happened Phil Hays
<Spampostmaster@comcast.net> wrote in
<patsl15a4mb135g980b8mqt1t66snnukgf@4ax.com>:

Depends on location. For the USA as a whole, I just checked
Monster.com and found the following posted jobs:

113 hits for "fpga and verilog"
148 hits for "fpga and vhdl"

Looks to me like VHDL is still more popular.
Google:

'fpga vhdl sucks' 2460 hits
'fpga verilog sucks' 1340 hits
;-)
_________________________________________
Usenet Zone Free Binaries Usenet Server
More than 140,000 groups
Unlimited download
http://www.usenetzone.com to open account

 

[Ben Twijnstra]

Hi Gert,

Fine, thanks for reply. I am aware that VHDL is a matter of specifying.
If you can recommend documents or books, please don't hesitate.

Noticing you're very probably Dutch, you could try Bert Molenkamp's VHDL
book - it's a bit dated but will give you a very thorough understanding of
the language and what which construct generates.

There's a PDF version that can be found here:

http://wwwhome.cs.utwente.nl/~molenkam/vhdl_boek/

Best regards,



Ben

 

[Nemesis]

Robert wrote:

This is not an answer to your query but rather a question to you:

How did you include the generated FIFO from Core Generator in your
project? (I am assuming you're using ISE)

Did you have to compile the cores seperately? Or did ISE take care of
it?

I use ISE7.1. FIFO Generator works exactly like other cores. I just
clicked on "Add new Source...".
When I used ISE6.3 I was not able to get FIFO Generator work, it always
generated empty cores!

 

[Nemesis]

Peter Alfke wrote:

If your 32 MHz clock is really derived from, and thus synchronous with,
the 128 MHz, then I would treat this as a synchronous FIFO.

In the final design they should be synchronous, I should get them from
a DCM with a 64MHz input. Now I just create them in the testbench.
Anyway I don't think this is the problem, the test I'm performing is
very simple, first I raise the wr_enable, I wait for the FULL signal,
and then I lower the wr_enable and after a little bit of time I raise
the rd_enable.

Asynchronous means that you have no idea of, and no control over, the
phase relationship between the two clocks. And asynchronous FIFO
control is far trickier than synchronous, just because of the unknown
and shifting phase relationships, and the associated possible decoding
glitches and even metastability. Synchronism makes all this so much
easier.

I understand that asynchronous FIFOs are more trickier than synchronous
ones ... but I don't want to use a synchronous FIFO, the clocks
relation is not fixed, their ratio could change in the future.
So I'm just asking, is possible to store 16 words in a 16 words deep
FIFO? Or "Deep N" means that I can only store N-1 words?
Is this problem somehow related to the old asynchronous-fifo core
behaviour? I remember that it let me chose only the length like
7,15,31,63 ... i.e. (2^N)-1.

 

[Nemesis]

Nemesis ha scritto:

[...]

Is this problem somehow related to the old asynchronous-fifo core
behaviour? I remember that it let me chose only the length like
7,15,31,63 ... i.e. (2^N)-1.

OK, I just read carefully the summary screens that appears at the of
the FIFO customization ...
When you chose an asynchronous FIFO it says: "Write Depth:15 Read
Depth:15. Actual FIFO depth differs from specified depth in this
configuration".
So this is a "limit" of the asyncrhonous FIFO.

 

[Hal Murray]

So I'm just asking, is possible to store 16 words in a 16 words deep
FIFO? Or "Deep N" means that I can only store N-1 words?

It's possible, but not simple. Keeping track of 0 to 16 words
in a FIFO requires 17 states. That won't fit in 4 bits.

--
The suespammers.org mail server is located in California. So are all my
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[Antti Lukats]

"mvetromille" <mvetromille@gmail.com> schrieb im Newsbeitrag
news:b1bb368c3bf24200aae1c08000ca3267@localhost.talkaboutelectronicequipment.com...

Hello! I instantiated SDRAM memory in an EDK project, but I don't know
what
I have to do in order to boot from it. I want to store my instructions and
data into it. Does anyone can help me?

Thank you!
Melissa

SDRAM is VOLATILE memory so you can not boot from it as it does not contain
any data.

you need some nonvolatile memory for booting, so you can copy this data to
the SDRAM and then start execution from SDRAM

antti

 

[Nemesis]

Hal Murray wrote:

So I'm just asking, is possible to store 16 words in a 16 words deep
FIFO? Or "Deep N" means that I can only store N-1 words?

It's possible, but not simple. Keeping track of 0 to 16 words
in a FIFO requires 17 states. That won't fit in 4 bits.

OK.
Is this true also for synchronous FIFO?
In this case FIFO Generator announce a depth equal to 16