EDK : FSL macros defined by Xilinx are wrong

[Eli Hughes]

vssumesh wrote:

Any body please suggest any good tool to convert simulink model to
equivalent RTL.

Look on the Xilinx website. There is a tool called System Generator for
DSP. You get a special simulink toolbox to create your logic.


-Eli

 

[Kolja Sulimma]

zqhpnp@gmail.com wrote:

Who can tell me where I can find the introductions to the IO interface
standard of fpga(For example,LV TTL,LV CMOS,GTL,GTL+,CTT)? If there is
some books,please tell me their names.

Most (if not all) of these are JEDEC-standards and can be downloaded from www.jedec.org.
Look for JESD8.

Kolja Sulimma

 

[Peter Alfke]

Well, veterans of the TTL days (and I am one of them) can exchange
horror stories about weird metastable behavior, but the modern CMOS
flip-flops that I have tested repeatedly during the past 17 years
behave much better. See XAPP094.
The problem with metastability is not the unpredictable 0 or 1 outcome
(who cares, either result is as justified as the other) or the strange
level ( does not exist in buffered CMOS, or if it existed it could
easily be fixed by biasing the buffer).
The real, and unsolvable, problem is that metastability will cause a
logic-level change at an uncontrollable moment. Most of the time just
delayed by picoseconds or one or a few ns. But, very rarely, it can be
more nanoseconds.
Novices, with their eyes glued to a simulator, must be told that X just
stands for "I do not know enough to tell you what it is", and not for
"strange electrical level".
Peter Alfke, Xilinx Applications

 

[Peter Alfke]

Claudio, your problem remains unsolved because you never told us what
your problem is.
If you want to select the best algorithm for a given FPGA family, that
is an easy issue.
If you want to compare different algorithms on different FPGA families
and/or different manufacturers: more work, but still easy.
If you are aiming for an ASIC: a totally different, and more difficult
issue.

Don't ask for help, when you are unwilling to tell us your parameters!
Peter Alfke

 

[Jeremy Stringer]

John_H wrote:

Even if your design runs very slow, the SDRAM module has high current
demands.

Since all the VSS and VDD pins are connected, you still need to connect
all the pins on the module. Would you consider it safe to ride in a
hot-air balloon where the basket is attached by one small rope? It may

[cut]

Did anyone else miss the message that this is in reply to? I found it
using google, but it didn't come down on my newsfeed.

Jeremy

 

[Peter Alfke]

Brad wrote:
"I especially like the high speed SMA(?) connectors.
Looks like gold plating. "

Yes, they are SMA, and the plating is "pure 24 carat gold, several
thousand nanometers thick" as they might say in marketing, using
in-terminolgy...
Peter

 

[Ken McElvain]

Synplify DSP can take simulink model to optimized (folding/retiming ...)
RTL.

A couple of links:

http://www.synplicity.com/products/synplifydsp/index.html
http://www.synplicity.com/literature/pdf/ss_signalcrafters05.pdf

vssumesh wrote:

Any body please suggest any good tool to convert simulink model to
equivalent RTL.

 

[Eric Smith]

"kmlpatel@gmail.com" <kmlpatel@gmail.com> writes:

What's more than likely going on is that you were given either:

1. An evaluation Registration ID
2. A Foundation Simulator Registration ID

Since both of these configurations are not currently supported on
Linux,

Will the Foundation ISE Simulator be available on Linux in a future
release (perhaps 7.2i)?

 

[jai.dhar@gmail.com]

Just out of curiosity John, it seems like you are suggesting designing
around your own SDRAM chips is much harder than using a module - while
I have used neither, I would think using SDRAM ic's are easier since
you can place them better - and I don't see the big issue about SI,
its' 100 MHz after all (or 133). I mean, I agree, you shouldn't use
2-layer, but with 4-layer, unless you are weaving in and out and going
all around the board, simple matched trace lengths with some series R's
should do it, no?

I ask because I'm doing my first design around SDRAM, and now would be
a good time to find out how doomed I

Regarding the original question however, John answered it well - don't
try and cheat by only connecting half the VDD's or whatever. They used
multiple VDDs for a reason, and they expect you to make use of that. On
a 4-layer board, this wouldn't be a problem if you had planes - but 2
layer, I can see why you want to minimize the pin usage. I think you
may waste more money than if you were to just have gone with a 4 layer
to start... $140 for 2 pieces isn't that bad, is it?

J

 

[Antti Lukats]

"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag
news:ee90d8e.-1@webx.sUN8CHnE...

Hi My company wanted to buy PCI core(33Mhz), and it should be fitted in
spartan-3 fpga and should not take not more than 350 slices Does any one

have got any idea from where i can get this PCI core ? pls mail to
pbijoy@rediffmail.com

rgds bijoy

there are several free PCI cores as well, one that is very simple and small
can be downloaded from the lattice website. it defenetly works in S3 and is
sure less than 350 slices. but I think the license doesnt promote using it
in non lattice silicon.

antti

 

[John_H]

<jai.dhar@gmail.com> wrote in message
news:1129295345.792785.282840@g47g2000cwa.googlegroups.com...

Just out of curiosity John, it seems like you are suggesting designing
around your own SDRAM chips is much harder than using a module - while
I have used neither, I would think using SDRAM ic's are easier since
you can place them better - and I don't see the big issue about SI,
its' 100 MHz after all (or 133). I mean, I agree, you shouldn't use
2-layer, but with 4-layer, unless you are weaving in and out and going
all around the board, simple matched trace lengths with some series R's
should do it, no?

SI is still an issue because it's not the frequency, it's the edge rates.
Working with ICs can be easier than working with modules for 1-3 chip
designs. The original poster wanted to use a single layer board (?!) which
wouldn't support most modern devices' current needs and still maintain any
semblence of logic levels.

If you *know* what you're doing, a 2-layer board can work. Decoupling
becomes more critical since the VCC impedance will be significantly
dependent on the caps and their locations versus the 4-layer board that has
a low impedance from many distributed decoupling caps to the chips. If
modules are used (my latest experience was DDR-2s) there may be a VCC
"region" separate from the grounds requiring decent decoupling between the
2-layer board's ground plane and the VCC pins for the module to keep the
return current for the address/control signals from crosstalking
significantly through the return paths.

SI for a single line can easily be tamed with appropriate termination
schemes. A multitude of signals, however, require good terminations *and*
good return paths. The larger problem on a 2-layer board may be the bounce
provided by poor VCC impedances even if the ground impedance is kept
reasonably solid. It's the edges we worry about most, not the frequency.

I ask because I'm doing my first design around SDRAM, and now would be
a good time to find out how doomed I

If you have the experience under your belt to understand what kind of
crosstalk and chip-rail related I/O overshoot/undershoot you get with chips
that handle the edge rates of your memories, you have a good chance of not
being doomed. If you push up to 4 layers to keep solid VCCs and grounds and
stay aware of the return paths for your signals (especially your clocks) you
should be golden.

Regarding the original question however, John answered it well - don't
try and cheat by only connecting half the VDD's or whatever. They used
multiple VDDs for a reason, and they expect you to make use of that. On
a 4-layer board, this wouldn't be a problem if you had planes - but 2
layer, I can see why you want to minimize the pin usage. I think you
may waste more money than if you were to just have gone with a 4 layer
to start... $140 for 2 pieces isn't that bad, is it?

J

The cost of 4 layer boards isn't outrageous these days even in prototype
quantities. The headaches from a 2-layer board aren't worth the difference
in prototype costs unless you have nothing better to do than enjoy the extra
weeks figuring out why your design is flakey (which some people might!)

- John_H

 

[jai.dhar@gmail.com]

Well put. I'm aware it's all about edge-rates, but not having the
Micron datasheet handy, it was easier to fire off the frequency
Besides, you rarely see a 10 MHz signal with the edge rate typically
found in a 10 Gbps signal... at least I haven't! I definitely recommend
a thorough 3+ readings of Howard johnson's High-speed digital design -
for those interested in SI (just as an aside).

I am definitely using 4-layer for my upcoming design, so return paths
shouldn't be a problem. I'm more concerned about how I can't verify the
SI on the board since I don't have a scope at all... are simple
series-end terminators sufficient for SDRAM, or are more complicated
termination schemes advised?

PS: I don't mean to hijack the thread - I just thought since my
questions are relevant, and potentially of interest to the poster, I
would post here...

 

[Hal Murray]

The cost of 4 layer boards isn't outrageous these days even in prototype
quantities. The headaches from a 2-layer board aren't worth the difference
in prototype costs unless you have nothing better to do than enjoy the extra
weeks figuring out why your design is flakey (which some people might!)

Even if you are sure that your final target is 2 layers, it might
be better to use 4 on the prototype stage to reduce the risk and
get the software guys off the ground and off your back.

Then you can work on making 2 layers work in parallel with software
development. And if your new/inexpensive boards crash occasionally
when the old/prototype ones don't, the software guys have a good claim
that their code is not the problem. (Assuming you didn't make many
other changes so you can run the same code.)

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

Aurelian Lazarut: Thanks for your answers,I'm a learner.I don't
understand what you said about it,can you say detaily.I use Synplify
Pro to synthesis it,it gives meE:Internal Error
@E:"F:\Xilinx\ColorConvertor\csc_top.vhd":95:8:95:14|Can't find library
simprim
@E:"F:\Xilinx\ColorConvertor\csc_top.vhd":96:27:96:27|use: simprim is
not a library
@E:"F:\Xilinx\ColorConvertor\csc_top.vhd":97:24:97:24|use: simprim is
not a library
@E:"F:\Xilinx\ColorConvertor\csc_top.vhd":96:27:96:27|Identifier
simprim is not declared
@E:"F:\Xilinx\ColorConvertor\csc_top.vhd":97:24:97:24|Identifier
simprim is not declared
what is it?Why?Thank you very much!

 

[dlharmon]

On 2005-10-15, Mika Leinonen <mika.leinonen@tut.fi> wrote:

Have You got any experiences running design software for windowses under
WINE & Linux? The devices I'd like to design for are Lattice
ispLSI1016/1032/E and Xilinx XC9572/XL.
I have ispDesignExpert 8.4 installed for Windows.
And a recent Xilinx Webpack.

For the Xilinx part, ISE Webpack is available for GNU/Linux. They
only claim to support only RHEL, but I got it running on Debian.
It does seem slower than the Windows version, but it is better than
using WINE. Actually the only slow thing about it is the GUI.

Darrell Harmon
http://dlharmon.com

 

[Slurp]

"David Geirsson" <alt.spam@gmail.com> wrote in message
news:1129406486.415303.231540@z14g2000cwz.googlegroups.com...

Hi all,

I am new to logic design in general, but I am getting an FPGA
development board (the Spartan-3 board from xilinx) and I hope to make
a small circuit for connecting to an old microcomputer and some SRAM.
For this project, I will need a bunch of (~60) 5V I/O lines, but the
FPGA's lines are all 3.3V logic. How do people generally go about
handling this sort of thing? It seems ridiculous to put 8-bit data
buffers on the lines, as there would be a ridiculous amount of them. Is
there a good level converter circuit with loads of I/O lines or some
such?

Any help would be appreciated!

-dsg

Don't know about Xilinx, but Altera parts generally have multivolt I/O. Some
of the older parts, for example the ACEX1k part has I/O which can run at
2.5, 3.3 and 5V at the same time.

I would imagine Xilinx would have the same capabilities.

Slurp

 

[Sylvain Munaut]

Waage wrote:

Has anyone gotten impact to work on Linux with the Platform USB Cable??

If so, what version of the kernel were you using?
What, if any debug did you have to do to get it to work?

I just got the Cable yesterday, and have so far been unable to get
impact
to even find the device.

I know the drivers are installed and the firmware is loaded.

Does it really work on Linux?

Thanks, Chris

I tried and never got it to work ... That really pisses me off actually
because // is quite slow when downloading data to SDRAM ...

Always get a "write cmdbuffer failed 20000015" in impact ...


Sylvain

 

[Philip Freidin]

On 15 Oct 2005 19:38:35 -0700, seabrench@163.com wrote:

Hello everybody!When I use synplify Pro to synthesis,it tells me:
@E:Internal Error
Why?How to solve it?Thanks!

Contact Synplicity at www.synplicity.com

 

[jai.dhar@gmail.com]

Hey everyone, thanks for the tips! Some follow up questions - I only
have the 2 SDRAM (16Mx16) Micron IC's left to route, so I thought I
would ask for advice. They are right up against the FPGA (Cyclone
EP1C12Q240 - QFP), with the long side against the long side of the FPGA
(as opposed to 'standing up') - I was thinking since I can choose pin
placement on the FPGA, I could route every other FPGA pin to the side
of the RAM facing closest to the FPGA, and then the alternate pins on
the bottom layer (4 layer board) under the SDRAM to the side further
away from the FPGA. Since it's only a 4-layer, getting decoupling may
be tricky with this way, but I'm using 0402's, so it may work. Also, is
there a specific FPGA pin I should use for the clock, and should I
buffer it? I have 2 modules, one of the top side of the FPGA, one on
the bottom, and they aren't sharing any signals. I suppose you could
argue that I should share address/control lines to form a x32 bus, but
I have the pins to spare and it saves on complexity. I'm not sure if it
would be possible on a 4-layer also (or is it?).

Any thoughts?

 

[Steven J. Hill]

dlharmon wrote:

For the Xilinx part, ISE Webpack is available for GNU/Linux. They
only claim to support only RHEL, but I got it running on Debian.
It does seem slower than the Windows version, but it is better than
using WINE. Actually the only slow thing about it is the GUI.

The only thing that really sucks is my new dual Opteron system that

cannot run the Webpack because it is 32-bit and my system is 64-bit.
And no, the 32-bit emulation does not work. Frustrating.

-Steve